L6983_V01 STMICROELECTRONICS | Alldatasheet
Document overview
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Technical content
Datasheet sections
- 1 Diagram
- 2 Pin configuration
- 3 Typical application circuit
- 4 Absolute maximum ratings
- 4.1 ESD protection
- 4.2 Thermal characteristics
- 5 Electrical characteristics
- 5.1 Frequency selection table
- 6 Functional description
- 6.1 Enable
- 6.2 Soft-start
- 6.3 Undervoltage lockout
- 6.4 Light-load operation
- 6.4.1 Low consumption mode (LCM)
- 6.4.2 Low noise mode (LNM)
- 6.4.3 Efficiency for low consumption mode and low noise mode part number
- 6.4.4 Load regulation for low consumption mode and Low noise mode part number
- 6.5 Switch-over feature
- 6.6 Spread spectrum
- 6.7 Overvoltage protection
- 6.8 Overcurrent protection
- 6.9 Thermal shutdown
- 6.10 Power Good
- 7 Closing the loop
- 7.1 GCO(s) control to output transfer function
- 7.2 Error amplifier compensation network
- 7.3 Voltage divider
- 8 Application notes
- 8.1 Programmable power up threshold
Features
- 3.5 V to 38 V operating input voltage
- Output voltage from 0.85 V to V IN
- 3.3 V and 5 V fixed output voltage versions
- 3 A DC output current
- 17 μA operating quiescent current
- Internal compensation network
- Two different versions: LCM for high efficiency at light loads and LNM for noise sensitive applications
- 2 μA shutdown current
- Internal soft-start
- Enable
- Overvoltage protection
- Output voltage sequencing
- Thermal protection
- 200 kHz to 2.3 MHz programmable switching frequency. Stable with low ESR capacitor
- Optional spread spectrum for improved EMC
- Power Good
- Synchronization to external clock for LNM devices
- QFN16 package
Applications
- Designed for 24 V buses industrial power systems
- 24 V battery powered equipment
- Decentralized intelligent nodes
- Sensors and always-on applications
- Low noise applications
Description
The L6983 is an easy to use synchronous monolithic step-down regulator capable of delivering up to 3 A DC to the load. The wide input voltage range makes the device suitable for a broad range of applications. The L6983 is based on a peak current mode architecture and is packaged in a QFN16 3x3 with internal compensation thus minimizing design complexity and size. The L6983 is available both in low consumption mode (LCM) and low noise mode (LNM) versions. LCM maximizes the efficiency at light-load with controlled output voltage ripple so the device is suitable for battery-powered applications. LNM makes the switching frequency constant and minimizes the output voltage ripple for light load operations, meeting the specification for low noise sensitive applications. The L6983 allows the switching frequency to be selected in the 200 kHz - 2.3 MHz range with optional spread spectrum for improved EMC. Maturity status link L6983
38 V, 3 A synchronous step-down converter with 17 µA quiescent current
DS13116 - Rev 2 - April 2020 For further information contact your local STMicroelectronics sales office.
The EN pin provides enable/disable function. The typical shutdown current is 2 µA when disabled. As soon as the EN pin is pulled up, the device is enabled and the internal 1.3 ms soft-start takes place. The L6983 features Power Good open collector that monitors the FB voltage. Pulse-by-pulse current sensing on both power elements implements an effective constant current protection and thermal shutdown prevents thermal run-away. L6983 DS13116 - Rev 2 page 2/63
1 Diagram
Figure 1. Block diagram
2 Pin configuration
Figure 2. Pin connection (top through view) Table 1. Pin description 2 VINLDO DC input voltage connected to the supply rail with a simple RC filter.
4 EN / CLKIN
signal, which synchronizes the device.
5 PGOOD
6 VBIAS
7 FB/VOUT
sensing with selected internal voltage divider.
8 FSW Connect an external resistor to program the oscillator frequency and
enable the optional dithering. capacitor (≥ 1 µF) to filter internal voltage reference.
11 BOOT
refreshed during the low-side switch conduction time.
12 VIN DC input voltage. 13 PGND Power ground. 14 SW Switching node. 15 SW Switching node. 16 PGND Power ground. - Exposed PAD Exposed pad must be connected to AGND and PGND. L6983 Pin configuration DS13116 - Rev 2 page 5/63
3 Typical application circuit
Figure 3. Basic application (adjustable version) Table 2. Typical application component
4 Absolute maximum ratings
rating conditions may affect device reliability. Table 3. Absolute maximum ratings
- Negative peak voltage during switching activities caused by parasitic layout elements.
4.1 ESD protection
Table 4. ESD performance
4.2 Thermal characteristics
Table 5. Thermal data
5 Electrical characteristics
TJ = 25 °C, VIN = 24 V unless otherwise specified. Table 6. Electrical characteristics
Electrical characteristics
Symbol Parameter Test conditions Min. Typ. Max. Unit TSS Internal soft-start 1 1.3 1.6 ms Error amplifier VFB Voltage feedback Adjustable version TJ = 25 °C 0.845 0.85 0.855 V Adjustable version TJ = - 40 °C ≤ TJ ≤ 125 ° (4) 0.842 0.85 0.858 V Fixed 3.3 V version TJ = 25 °C 3.27 3.3 3.33 V Fixed 3.3 V version TJ = -40 °C ≤ TJ ≤ 125 °C (4) 3.284 3.3 3.346 V Fixed 5.0 V version TJ = 25 °C 4.955 5.0 5.045 V Fixed 5.0 V version TJ = -40 °C ≤ TJ ≤ 125 °C (4) 4.93 5 5.07 V Overvoltage protection VOVP Overvoltage trip (VOVP/ VREF) 115 120 125 % VOVP_HYST Overvoltage hysteresis 1 2 6 % Synchronization (LNM versions only) fCLKIN (3) Synchronization range 200 2200 kHz VCLKIN_TH (3) Amplitude of synchronization clock 2.3 V VCLKIN_T (3) Synchronization pulse ON and OFF time 2.3 V ≤ VCLKIN_TH ≤ 2.5 V VCLKIN_TH = 2.3 V 60 ns Synchronization pulse ON and OFF time VCLKIN_TH > 2.5 V 20 ns Power Good VTHR PGOOD threshold Adjustable output version TJ = -40 °C ≤ TJ ≤ 125 °C (4) 87 90 93 % Fixed 3.3 output version TJ = -40 °C ≤ TJ ≤ 125 °C (4) 87 90 93 % Fixed 5.0 output version TJ = -40 °C ≤ TJ ≤ 125 °C (4) 87 90 93 % VTHR_HYST (4) PGOOD hysteresis 3 VPGOOD PGOOD open collector output VIN > VIN_H AND VFB < VTH 4 mA sinking load 0.4 V 2 < VIN < VIN_H 4 mA sinking load 0.8 V L6983
- Parameter tested in the static condition during testing phase. The parameter value may change over a dynamic application
- Specifications in the - 40 to 125 °C temperature range are assured by characterization and statistical correlation.
- Not tested in production.
5.1 Frequency selection table
characterization and statistical correlation. Table 7. FSW selection
6 Functional description
The L6983 device is based on a “peak current mode" architecture with constant frequency control. Therefore, the intersection between the error amplifier output and the sensed inductor current generates the PWM control signal to drive the power switch. The device features LNM (low noise mode) that is forced PWM control, or LCM (low consumption mode) to increase the efficiency at light-load on the selected part number. The main internal blocks shown in the block diagram in Figure 1. Block diagram and Figure 2. Pin connection (top through view) are:
- Embedded power elements
- A fully integrated adjustable oscillator which is able to set eight different switching frequencies from 200 to 2300 kHz
- The ramp for the slope compensation avoiding subharmonic instability
- A transconductance error amplifier with integrated compensation network
- The high-side current sense amplifier to sense the inductor current
- A “Pulse Width Modulator” (PWM) comparator and the driving circuitry of the embedded power elements
- The soft-start block ramps up the reference voltage on error amplifier thus decreasing the inrush current at power-up. The EN pin inhibits the device when driven low
- The EN/CLK pin section, which, for LNM versions, allows synchronizing the device to an external clock generator
- The pulse-by-pulse high-side / low-side switch current sensing to implement the constant current protection
- A circuit to implement the thermal protection function
- The OVP circuitry to discharge the output capacitor in case of overvoltage event
- The switchover capability of the internal regulator to supply a portion of the quiescent current when the VBIAS pin is connected to an external output voltage
- Enable/ disable dithering operation
6.1 Enable
The EN pin is a digital input that turns the device on or off. In order to maximize both the EN threshold accuracy and the current consumption, the device implements two different thresholds: 1. The wake-up threshold, V WAKE_UP = 0.5 V (see Table 6. Electrical characteristics) 2. The start-up threshold, V EN = 1.2 V (see Table 6. Electrical characteristics) The following picture shows the device behavior. L6983 Functional description DS13116 - Rev 2 page 11/63
Figure 4. Power-up/down behavior increasing the current consumption. Once the voltage becomes lower than VEN, FALLING, the device interrupts the switching activities. reducing the current consumption. Please refer to Table 6. Electrical characteristics for the reported thresholds.
6.2 Soft-start
The soft-start (SS) limits the inrush current surge and makes the output voltage increase monotonically.
Figure 5. Soft-start procedure
- EN pin rising over VEN threshold. Please refer to Table 6. Electrical characteristics
Figure 6. Soft-start phase with IOUT = 2.5 A
6.3 Undervoltage lockout
UVLO lasts more than 10 μs, the internal logic resets the device by turning off both LS and HS. After the reset, if the EN pin is still high, the device repeats the soft-start procedure.
6.4 Light-load operation
- Low consumption mode (LCM)
Please refer to Table 12. Order codes to select the part number with the preferred light load strategy.
6.4.1 Low consumption mode (LCM)
The LCM maximizes the efficiency at light load. Where VFB, LCM is 1.8% (typ.) higher than VFB.
- The peak inductor current required is lower than I SKIP
- The voltage on the FB pin is higher than VFB, LCM
Figure 7. Light load operation A new switching cycle takes place once the voltage on the FB pin becomes lower than VFB,LCM. The HS switch is kept on until the inductor current reaches ISKIP. than the defined threshold. Otherwise, as soon as the LS is turned off the HS is turned on.
Figure 12. LCM operation over loading condition (part 4-CCM)
6.4.2 Low noise mode (LNM)
Figure 13. Low noise mode operation at zero load
6.4.3 Efficiency for low consumption mode and low noise mode part number
Figure 14. Light-load efficiency for low consumption mode and low noise mode - linear scale, and Figure 15. Light-load efficiency for low consumption mode and low noise mode - log scale report the efficiency exactly the same efficiency at the medium / high load. Figure 14. Light-load efficiency for low consumption mode and low noise mode - linear scale Figure 15. Light-load efficiency for low consumption mode and low noise mode - log scale
6.4.4 Load regulation for low consumption mode and Low noise mode part number
Figure 16. Load regulation for LCM and LNM. VIN = 24 V; VOUT = 5 V; FSW = 400 kHz - linear scale and Figure 17. Load regulation for low noise mode. VIN = 24 V; VOUT = 5 V; FSW = 400 kHz - log scale report the load consumption mode (LCM) the behavior of the different part number is exactly the same. Figure 16. Load regulation for LCM and LNM. VIN = 24 V; VOUT = 5 V; FSW = 400 kHz - linear scale Figure 17. Load regulation for low noise mode. VIN = 24 V; VOUT = 5 V; FSW = 400 kHz - log scale
6.5 Switch-over feature
The switch-over maximizes the efficiency at light load that is crucial for low consumption application. Figure 18. Switch-over to an external voltage source in the range of 3.0 V < VBIAS < VIN.
6.6 Spread spectrum
selection). The internal dithering circuit changes the switching frequency in a range of ± 5%.
- Ramps up in 63 steps from minimum to maximum FSW
- Ramps down in 63 steps from maximum to minimum FSW The modulation shape is almost triangular with a frequency of: F D i t ℎ eri n g = F s w 126 (6)
6.7 Overvoltage protection
capacitor if the output voltage is 20% (typ.) over the nominal value. overvoltage threshold even during the worst-case scenario in term of load transitions. limitation to limit the maximum reversed switch current during the overvoltage operation.
6.8 Overcurrent protection
current (please refer to Table 6. Electrical characteristics) in overcurrent condition. the low-side sensing “valley”. The L6983 device assures an effective overcurrent protection sensing the current flowing in both power elements. the effectiveness of the overcurrent protection even in extreme duty cycle conditions. the high-side turn on, so the device can skip pulses decreasing the switching frequency. Figure 19. Over current protection behavior characteristics) and TMASKHS is the masking time of the high-side switch (75 ns typ.).
and so the peak current protection limits the switch current. Figure 20. Soft-start procedure with VOUT shorted to GND current protection with a persistent short circuit between VOUT and GND.
Figure 21. Over current procedure with persistent short circuit between VOUT and GND
6.9 Thermal shutdown
6.10 Power Good
- The FB pin voltage is lower than 90% (typ.) of the nominal internal reference for more than 10 µs
- The FB pin voltage is higher than 120% (typ.) of the nominal internal reference for more than 10 µs (see
- During the soft-start procedure also with pre-charged VOUT
- If a thermal shutdown event occurs
The PG pin is VIN compatible.
Figure 22. PGOOD thresholds
7 Closing the loop
The following picture shows the typical compensation network required to stabilize the system. Figure 23. Block diagram of the loop
7.1 GCO(s) control to output transfer function
amplifier that introduces a double pole at one half of the switching frequency. Where ISLOPE is equal to 1 A. implements the slope compensation to avoid sub-harmonic oscillations at duty cycle over 50%.
7.2 Error amplifier compensation network
The following figure shows the typical compensation network required to stabilize the system. Figure 24. Trans-conductance embedded error amplifier
7.3 Voltage divider
Figure 25. Leading network example
8 Application notes
8.1 Programmable power up threshold
Figure 26. Leading network example
8.2 External synchronization (available for low noise mode only)
The device allows a direct connection between a clock source and the EN/CLKIN pin. Figure 27. External synchronization. Direct connection. value of the applied signal.
Table 6. Electrical characteristics). The device allows also the AC coupling. Figure 28. External synchronization. AC coupling to EN/CLKIN pin and described on Section 8.1 Programmable power up threshold. allows the synchronization by keeping the selected power-up and down thresholds. Table 8. External synchronization AC coupling suggested operation range The minimum amplitude for the external clock signal is, for both the configurations, equal to 2.3 V. capacitor equal to 1 nF is a correct choice.
8.3 Output voltage adjustment
Figure 29. Application circuit
8.4 Switching frequency
Section 6.6 Spread spectrum).
8.5 Design of the power components
8.5.1 Input capacitor selection
The input capacitor voltage rating must be higher than the maximum input operating voltage of the application.
In the following table, some suitable capacitor part numbers are listed. Table 9. Capacitor part numbers
8.5.2 Inductor selection
Where QP has been defined in Section 7.1 GCO(s) control to output transfer function.
8.5.3 Output capacitor selection
output capacitor has to be selected in order to have a voltage ripple compliant with the application requirements.
C O UT , mi n , RIP P LE = ∆ I L , M A X 8 ∙ ∆ V O UT ∙ F S W (43) As the compensation network is internal, the output capacitor should be selected in order to have a proper phase margin and then a stable control loop. A good rule to obtain a proper dimensioning for the minimum amount of the output capacitor is set the target system bandwidth equal to FSW/8. The following equation keep into account the precedent consideration: C O UT , B W , mi n = 8.04 F s w 8 ∙ V O UT (44) The maximum amount of the output capacitor is given by: C O UT , B W , M A X = 0.960 ∙ 10 − 3 V O U T (45) L6983 Design of the power components DS13116 - Rev 2 page 33/63
9 Application board
Figure 30. Evaluation board schematic The additional input filter (C14, L3, C13, L2, C12, and C15) limits the conducted emission on the power supply.
Table 10. Bill of material
10 Efficiency curves
- C OUT: – 1 x CGA6P1X7R1C226M250AC 22 µF 16 V (TDK); – 2 x CGA5L3X5R1H106K160AB 10 µF 50 V (TDK).
- Inductor: – XAL6060-153ME (Coilcraft)
Figure 33. Efficiency VIN = 24 V; VOUT = 5 V; FSW = 0.4 MHZ Figure 34. Efficiency VIN = 24 V; VOUT = 5 V; FSW = 0.4 MHZ (log scale)
Figure 41. Power losses VIN = 24 V; VOUT = 3.3 V; FSW = 0.4 MHZ
- C OUT: – 2 x CGA6P1X7R1C226M250AC 22 µF 16 V (TDK); – 2 x CGA5L3X5R1H106K160AB 10 µF 50 V (TDK).
- Inductor: XAL6060-822ME (Coilcraft) L6983 Efficiency curves DS13116 - Rev 2 page 41/63
Figure 44. Power losses VIN = 12 V; VOUT = 3.3 V; FSW = 0.4 MHZ
- C OUT: – 1 x CGA6P1X7R1C226M250AC 22 µF 16 V (TDK); – 1 x CGA5L3X5R1H106K160AB 10 µF 50 V (TDK).
- Inductor: – XAL6060-472ME (Coilcraft). L6983 Efficiency curves DS13116 - Rev 2 page 43/63
Figure 47. Power losses VIN = 24 V; VOUT = 3.3 V; FSW = 1.0 MHZ
- C OUT: – 1 x CGA6P1X7R1C226M250AC 22 µF 16 V (TDK); – 1 x CGA5L3X5R1H106K160AB 10 µF 50 V (TDK).
- Inductor: – XAL6060-472ME (Coilcraft). L6983 Efficiency curves DS13116 - Rev 2 page 45/63
Figure 50. Power losses VIN = 12 V; VOUT = 3.3 V; FSW = 1.0 MHZ
- C OUT: – 1 x CGA6P1X7R1C226M250AC 22 µF 16V (TDK); – 2 x CGA5L3X5R1H106K160AB 10 µF 50V (TDK).
- Inductor: – XAL6060-472ME (Coilcraft). L6983 Efficiency curves DS13116 - Rev 2 page 47/63
- C OUT: – 1 x CGA6P1X7R1C226M250AC 22 µF 16 V (TDK); – 1 x CGA5L3X5R1H106K160AB 10 µF 50 V (TDK).
- Inductor: – XAL6060-472ME (Coilcraft).
Figure 54. Efficiency VIN = 12 V; VOUT = 5.0 V; FSW = 1.0 MHZ
11 Thermal dissipation
The thermal design is important in order to prevents thermal shutdown of the device if junction temperature goes above 165 °C. The three different sources of losses within the device are: 1. Conduction losses due to the on-resistance of high-side switch (R DSON_HS) and low-side switch (RDSON_LS); these are equal to: P CO N D = R D S O N _ HS ∙ I O UT 2 ∙ D + R D S O N _ LS ∙ I O UT 2 ∙ 1 − D (46) where D is the duty cycle of the selected application and is given by the following formula: D = V O U T + R D S O N _ LS + D CR l ∙ I O UT V IN − R D S O N HS − R D S O N _ LS ∙ I O UT (47) In order to obtain a more accurate extimation it is necessary to keep into account that the amount of resistance of the internal power MOSFET increases together with the temperature. For this reason, the value of RDSONHS and RDSONLS, should be increased from the typical of a factor equal to 15%. 1. Switching losses due to high-side power MOSFET turn-ON and OFF; these can be calculated as per below: P S W = V IN ∙ I O U T ∙ T RIS E + T F A L L
2 F S W = V I N ∙ I O UT ∙ T S W ∙ F S W (48)
where TRISE and TFALL are the overlap times of the voltage across the high side power switch (VDS) and the current flowing into it during turn-ON and turn-OFF phases, as shown in Figure 57. Switching losses. TSW is the equivalent switching time. For this device the typical value for the equivalent switching time is 20 ns. 1. Quiescent current losses, calculated as the equation below: P Q = V IN ∙ I Q , M A X (49) where IQ is the quiescent current and depends on the VBIAS connections. If VBIAS is connected to GND, the maximum is equal to 3 mA. Otherwise if VBIAS is connected to VOUT the quiescent current is given by: I Q , M A X = 0.8 m A + 1 η L 6983 V BI A S V IN ∙ 2.3 m A (50) The power losses are given by: P LO S S = P C O N D + P S W + P Q (51) The junction temperature TJ can be calculated as: T J = T A + R t ℎ J A ∙ P LO S S (52) where TA is the ambient temperature. RthJA is the equivalent thermal resistance junction to ambient of the device; it can be calculated as the parallel of many paths of heat conduction from the junctions to the ambient. For this device the path through the exposed pad is the one conducting the largest amount of heat. The RthJA measured on the demonstration board described in the following section is about 30 °C/W. L6983 Thermal dissipation DS13116 - Rev 2 page 51/63
Figure 57. Switching losses stationary application condition.
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. L6983
Package information
DS13116 - Rev 2 page 53/63
12.1 QFN16 (3x3 mm) package information
Figure 58. QFN16 (3x3 mm) package outline
Table 11. QFN16 (3x3 mm) mechanical data Figure 59. QFN16 (3x3 mm) recommended footprint
Table 12. Order codes
Ordering information
DS13116 - Rev 2 page 56/63
Revision history
Table 13. Document revision history 29-Oct-2019 1 Initial release. Table 6. Electrical characteristics, Section 8.5.2 Inductor selection, Figure 30. Evaluation board schematic and Table 10. Bill of material.
Contents
DS13116 - Rev 2 page 59/63