L6911E_07 STMICROELECTRONICS | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 34
Technical content
Datasheet sections
- 1 Block diagram
- 2 Pin settings
- 2.1 Pin connection
- 2.2 Pin description
- 3 Electrical data
- 3.1 Maximum ratings
- 3.2 Thermal data
- 4 Electrical characteristics
- 4.1 VID Setting
- 5 Device description
- 5.1 Oscillator
- 5.2 Digital to analog converter
- 5.3 Soft start and inhibit
- 5.4 Driver section
- 5.5 Monitor and protection
- 5.6 Inductor design
- 5.7 Output capacitor
- 5.8 Input capacitor
- 5.9 Compensation network design
- 6 VRM demo board description
- 6.1 Efficiency
- 6.2 Inductor design
- 6.3 Output capacitor
- 6.4 Input capacitor
- 6.5 Over-current protection
Features
■ Operating supply IC voltage from 5V to 12V buses ■ Up to 1.3A gate current capability ■ TTL-compatible 5 bit programmable output compliant with VRM 8.5 : 1.050V to 1.825V with 0.025V binary steps ■ Voltage mode PWM control ■ Excellent output accuracy: ±1% over line and temperature variations ■ Very fast load transient response: from 0% to 100% Duty Cycle ■ Power good output voltage ■ Overvoltage protection and monitor ■ Overcurrent protection realized using the upper MOSFET's R ds(ON) ■ 200kHz internal oscillator ■ Oscillator externally adjustable from 50kHz to 1MHz ■ Soft start and inhibit functions
Applications
■ Power supply for advanced microprocessor core ■ Distributed power supply
Description
The device is a power supply controller specifically designed to provide a high performance DC/DC conversion for high current microprocessors. A precise 5 bit digital to analog converter (DAC) allows to adjust the output voltage from 1.050 to 1.825 with 25mV binary steps. The high precision internal reference assures the selected output voltage to be within ±1%. The high peak current gate drive affords to have fast switching to the external power mos providing low switching losses. The device assures a fast protection against load overcurrent and load over-voltage. An external SCR is triggered to crowbar the input supply in case of hard overvoltage. An internal crowbar is also provided turning on the low side mosfet as long as the over-voltage is detected. In case of over-current detection, the soft start capacitor is discharged an the system works in HICCUP mode. SO-20 Table 1. Device summary
1 Block diagram
Figure 1. Block diagram
2 Pin settings
2.1 Pin connection
Figure 2. Pin connection (top view)
2.2 Pin description
Table 2. Pin description
1 VSEN Connected to the output voltage is able to manage over-voltage conditions and
3 SS/INH
Table 6 on page 9 and to set the overvoltage and power good thresholds. Connect to GND to program a ‘0’ while leave floating to program a ‘1’. the voltage control feedback loop.
10 FB This pin is connected to the error amplifier inverting input and is used to
compensate the voltage control feedback loop.
12 PGOOD
within the above specified threshlds. If not used may be left floating.
13 PHASE
14 UGATE High side gate driver output.
15 BOOT
a diode to Vcc (catode vs boot).
17 LGATE This pin is the lower mosfet gate driver output
18 VCC Device supply voltage. The operative supply voltage range is from 4.5 to 12V.
19 OVP
external SCR that crowbar the supply voltage. If not used, it may be left floating. If the pin is not connected, the switching frequency is 200KHz. built in oscillator stops to switch. Table 2. Pin description (continued)
3 Electrical data
3.1 Maximum ratings
3.2 Thermal data
Table 3. Absolute maximum ratings
- ESD immunity for pins 2 to 9 and 18 to 20 is guaranteed up to 1500V (Human Body Model).
Table 4. Thermal data
4 Electrical characteristics
Table 5. Electrical characteristic (VCC = 12V; TA = 25°C unless otherwise specified)
4.1 VID Setting
Table 5. Electrical characteristic (VCC = 12V; TA = 25°C unless otherwise specified) (continued) Table 6. VID Setting
5 Device description
The device is an integrated circuit realized in BCD technology. It provides complete control logic and protections for a high performance step-down DC-DC converter optimized for microprocessor power supply. It is designed to drive N Channel Mosfets in a synchronous- rectified buck topology. The device works properly with Vcc ranging from 5V to 12V and regulates the output voltage starting from a 1.26V power stage supply voltage (Vin). The output voltage of the converter can be precisely regulated, programming the VID pins, from 1.050V to 1.825V with 25mV binary steps, with a maximum tolerance of ±1% over temperature and line voltage variations. The device provides voltage-mode control with fast transient response. It includes a 200kHz free-running oscillator that is adjustable from 50kHz to 1MHz. The error amplifier features a 15MHz gain-bandwidth product and 10V/ms slew rate which permits high converter bandwidth for fast transient performance. The resulting PWM duty cycle ranges from 0% to 100%. The device protects against over- current conditions entering in HICCUP mode. The device monitors the current by using the r ds(ON) of the upper MOSFET which eliminates the need for a current sensing resistor. The device is available in SO20 package.
5.1 Oscillator
The switching frequency is internally fixed to 200kHz. The internal oscillator generates the triangular waveform for the PWM charging and discharging with a constant current an internal capacitor. The current delivered to the oscillator is tipically 50µA (F SW = 200KHz) and may be varied using an external resistor (RT) connected between RT pin and GND or VCC. Since the RT pin is maintained at fixed voltage (typ. 1.235V), the frequency is varied proportionally to the current sinked (forced) from (into) the pin. In particular connecting it to GND the frequency is increased (current is sinked from the pin), according to the following relationship: Equation 1 fS 200kHz 4.94 10 6⋅
Switching frequency variations vs. RT are reported in Figure 3 on page 11. delivered to the oscillator. Figure 3. Switching frequency variations vs. R T
5.2 Digital to analog converter
The built-in digital to analog converter allows the adjustment of the output voltage from 1.050V to 1.825V with 25mV binary steps as shown in the previous Table 6: VID Setting on page 9. The internal reference is trimmed to ensure the precision of 1%. The internal reference voltage for the regulation is programmed by the voltage identification (VID) pins. These are TTL compatible inputs of an internal DAC that is realised by means of a series of resistors rpoviding a partition of the internal voltage reference. The VID code drives a multiplexer that selects a voltage on a precise point of the divider. The DAC output is delivered to an amplifier obtaining the VPROG voltage reference (i.e. the set-point of the error amplifier). Internal pull-ups are provided (realized with a 5µA current generator); in this way, to program a logic "1" it is enough to leave the pin floating, while to program a logic "0" it is enough to short the pin to GND. The voltage identification (VID) pin configuration also sets the power-good thresholds (PGOOD) and the over- voltage protection (OVP) thresholds.
5.3 Soft start and inhibit
At start-up a ramp is generated charging the external capacitor CSS by means of a 10µA constant current, as shown in Figure 4 on page 13 When the voltage across the soft start capacitor (VSS) reaches 0.5V the lower power MOS is turned on to discharge the output capacitor. As VSS reaches 1V (i.e. the oscillator triangular wave inferior limit) also the upper MOS begins to switch and the output voltage starts to increase. The VSS growing voltage initially clamps the output of the error amplifier, and consequently VOUT linearly increases, as shown in Figure 4 on page 13. In this phase the system works in open loop. When VSS is equal to VCOMP the clamp on the output of the error amplifier is released. In any case another clamp on the non-inverting input of the error amplifier remains active, allowing to VOUT to grow with a lower slope (i.e. the slope of the VSS voltage, see Figure 4 on page 13). In this second phase the system works in closed loop with a growing reference. As the output voltage reaches the desired value VPROG, also the clamp on the error amplifier input is removed, and the soft start finishes. Vss increases until a maximum value of about 4V. The Soft-Start will not take place, and the relative pin is internally shorted to GND, if both VCC and OCSET pins are not above their own Turn-On thresholds; in this way the device starts switching only if both the power supplies are present. During normal operation, if any under-voltage is detected on one of the two supplies, the SS pin is internally shorted to GND and so the SS capacitor is rapidly discharged. The device goes in INHIBIT state forcing SS pin below 0.4V. In this condition both external MOSFETS are kept OFF .
Figure 4. Soft start
5.4 Driver section
MOS (also multiple MOS to reduce the Rds(ON)), maintaining fast switching transition. upper mos is in any case turned-on after 200nS from the low side turn-off. and the sink peak current is 1.3A @ VCC = 12V and 500mA @ VCC = 5V. and 550mA @ Vboot-Vphase = 5V.
5.5 Monitor and protection
The output voltage is monitored by means of pin 1 (VSEN). If it is not within ±10% (typ.) of the programmed value, the powergood output is forced low. The device provides overvoltage protection, when the output voltage reaches a value 17% (typ.) greater than the nominal one. If the output voltage exceed this threshold, the OVP pin is forced high (5V) and the lower driver is turned on as long as the over-voltage is detected. The OVP pin is capable to deliver up to 60mA (min) in order to trigger an external SCR connected to burn the input fuse. The low-side mosfet turn-on implement this function when the SCR is not used and helps in keeping the ouput low. To perform the overcurrent protection the device compares the drop across the high side MOS, due to its RDSON, with the voltage across the external resistor (R OCS) connected between the OCSET pin and drain of the upper MOS. Thus the overcurrent threshold (IP) can be calculated with the following relationship: Equation 4 where the typical value of IOCS is 200µA. To calculate the ROCS value it must be considered the maximum RDSON (also the variation with temperature) and the minimum value of IOCS. To avoid undesirable trigger of overcurrent protection this relationship must be satisfied: Equation 5 where ∆I is the inductance ripple current and IOUTMAX is the maximum output current. In case of output short circuit the soft start capacitor is discharged with constant current (10µA typ.) and when the SS pin reaches 0.5V the soft start phase is restarted. During the soft start the over-current protection is always active and if such kind of event occours, the device turns off both mosfets, and the SS capacitor is dicharged again after reaching the upper threshold of about 4V. The system is now working in HICCUP mode, as shown in Figure 7 on page 16 a. After removing the cause of the over-current, the device restart working normally without power supplies turn off and on. IP IOCS ROCS⋅ RDSON IP IOUTMAX 2-----+≥ IPEAK=
Figure 7. Hiccup mode and Inductor ripple current vs. V OUT
5.6 Inductor design
inductor, with vin = 5V and Vin = 12V.
The worst condition depends on the input voltage available and the output voltage selected. Anyway the worst case is the response time after removal of the load with the minimum output voltage programmed and the maximum input voltage available.
5.7 Output capacitor
Since the microprocessors require a current variation beyond 10A doing load transients, with a slope in the range of tenth A/µsec, the output capacitor is a basic component for the fast response of the power supply. In fact for first few microseconds they supply the current to the load. The controller recognizes immediately the load transient and sets the duty cycle at 100%, but the current slope is limited by the inductor value. The output voltage has a first drop due to the current variation inside the capacitor (neglecting the effect of the ESL): Equation 9 A minimum capacitor value is required to sustain the current during the load transient without discharge it. The voltage drop due to the output capacitor discharge is given by the following equation: Equation 10 Where D MAX is the maximum duty cycle value that is 100%. The lower is the ESR, the lower is the output drop during load transient and the lower is the output voltage static ripple. tapplication L ∆I⋅ tremoval L ∆I⋅ VOUT ∆VOUT = ∆IOUT · ESR ∆VOUT ∆IOUT 2 L
5.8 Input capacitor
upper MOS, so it must have a low ESR to minimize the losses. Where D is the duty cycle. The equation reaches its maximum value with D = 0.5.
5.9 Compensation network design
will be lower than the nominal value. Figure 8. Output transient response with out (a) and with (b) the droop function
introduces a static error (Vdroop in Figure 8 on page 18) proportional to the output current. Figure 9. Compensation network
Considering the previous relationships R2, R3, R8 and R9 may be determined in order to obtain the desired droop effect as follow:
- Choose a value for R2 in the range of hundreds of KΩ to obtain realistic values for the other components.
- From the above equations, it results: Equation 15 Equation 16 Where IMAX is the maximum output current.
- The component R3 must be chosen in order to obtain R3 << R8//R9 to permit these and successive simplifications. Therefore, with the droop function the output voltage decreases as the load current increases, so the DC output impedance is equal to a resistance ROUT. It is easy to verify that the output voltage deviation under load transient is minimum when the output impedance is constant with frequency. R8 ∆V+ R2⋅ VPROG R9 R8= VDROOP∆
1 VDROOP∆
Figure 10. Compensation network definition C(s) and ZL(s) are the output capacitor and inductor impedance respectively.
Where: τ1 = R4 × C20, τ2 = (R4+R3) × C20 and τd = Rd × C25. The regulator transfer function became now: Equation 19 Figure 10 on page 21 shows a method to select the regulator components (please note that the frequencies fEC and fCC corresponds to the singularities introduced by additional ceramic capacitors in parallel to the output main electrolytic capacitor).
- To obtain a flat frequency response of the output impedance, the droop time constant τ d has to be equal to the inductor time constant (see the note at the end of the section): Equation 20
- To obtain a constant -20dB/dec Gloop(s) shape the singularity f1 and f2 are placed in proximity of fCE and fLC respectively. This implies that: Equation 21
- To obtain a Gloop bandwidth of fC, results: Equation 22 Rd 1 s--- C25⋅⋅ Rd 1 s---+ C25⋅ R4 1 s--- C20⋅+⎝⎠ ⎛⎞ R3⋅ R4 1 s--- C20⋅+⎝⎠ ⎛⎞ R3+ Rd 1 s τ1 τd+() s2 R3 Rd 1s R3 Rd ⎛⎞ 1(⋅ Rs() 1s τ2⋅+() 1s τd⋅+()⋅ sC 1 8R d 1s R3 Rd τd Rd C25⋅ L RL ---- fLC fCE fCE ⎛⎞⋅== f1 f CE C20 1 2--- π R4 f CE⋅⋅⋅=⇒= fLC 1f C G0⇒⋅ A0 R0⋅ VIN fC fLC
and it was supposed that the droop network don't represent a charge for the inductor. Figure 11. Voltage regulation with droop function block scheme Because in the interested range |Gloop|>>1. To obtain a flat shape, the relationship considered will naturally follow.
6 VRM demo board description
developed for a VRM 8.5 Flexible Motherboard applicaton delivering up to 28.5A. enables the device together with the ENOUT input. Figure 12. Schematic circuit
6.1 Efficiency
Figure 13. In the application two Mosfets STS12NF30L (30V, 8.5mΩ typ with VGS = 12V) Figure 13. Efficiency vs. load current
6.2 Inductor design
6.3 Output capacitor
maximum duty cicle is equal to 100% results in 46.5mV with 1.85V of programmed output.
VRM demo board description L6911E
6.4 Input capacitor
For IOUT = 28.5A and with D = 0.5(worst case for input current ripple), Irms is equal to 17.8A. Three OSCON electrolityc capacitors 6SP680M, with a maximum ESR equal to 12mΩ, are chosen to substain the ripple. So the losses in worst case are: Equation 25
6.5 Over-current protection
Substituting the demo board parameters in the relationship reported in the relative section, (IOCSMIN = 170µA; IP =33A; RDSONMAX = 3mΩ) it results that ROCS = 1kΩ. PE S R I rms
7 Connector pin orientation
Table 7. Connector pin orientation
7 Reserved 44 No Contact
8 VID0 43 VID1
9 VID2 42 VID3
10 VID4 (25mV) 41 PWRGD
11 OUTEN 40 Ishare
13 Vss 38 Vss
14 Vcc
15 Vcc CORE 36 Vcc CORE
16 Vss 35 Vss
17 Vcc CORE 34 Vcc CORE
18 Vss 33 Vss
19 Vcc CORE 32 Vcc CORE
20 Vss 31 Vss
21 Vcc
22 Vss 29 Vss
23 Vcc CORE 28 Vcc CORE
24 Vss 27 Vss
25 Vcc
8 PCB and components layout
Figure 14. PCB and components layouts Figure 15. PCB and components layouts Figure 16. PCB and components layouts
Table 8. Part list
Table 8. Part list (continued)
9 Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com
Figure 17. SO20 Mechanical data & package dimensions
Table 9. Revision history 10-Apr-2007 3 Document has been reformatted, updated Table 3.