L6751B STMICROELECTRONICS | Alldatasheet
Document overview
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Technical content
Datasheet sections
- 1 Typical application circuit and block diagram
- 1.1 Application circuit
- 1.2 Block diagram
- 2 Pin description and connection diagram
- 2.1 Pin description
- 2.2 Thermal data
- 3 Electrical specifications
- 3.1 Absolute maximum ratings
- 3.2 Electrical characteristics
- 4 Device configuration and pinstrapping tables
- 4.1 JMode
- 4.2 Programming HiZ level
- 5 Device description and operation
- 6 Output voltage positioning
- 6.1 Multi-phase section - phase # programming
- 6.2 Multi-phase section - current reading and current sharing loop
- 6.3 Multi-phase section - defining load-line
- 6.4 Single-phase section - disable
- 6.5 Single-phase section - current reading
- 6.6 Single-phase section - defining load-line
- 6.7 Dynamic VID transition support
- 6.7.1 LSLESS startup and pre-bias output
- 6.8 DVID optimization: REF/SREF
- 7 Output voltage monitoring and protection
- 7.1 Overvoltage
- 7.2 Overcurrent and current monitor
- 7.2.1 Multi-phase section
Features
■ VR12 compliant with 25 MHz SVID bus rev1.5 – SerialVID with programmable IMAX, TMAX, VBOOT, ADDRESS ■ AMD SVI compliant ■ Second generation LTB Technology® ■ Flexible driver/DrMOS support ■ JMode support ■ Fully configurable through PMBus™ ■ Dual controller: – up to 6 phases for CORE and memory – 1 phase for graphics (GFX), system agent (VSA) or Northbridge (VDDNB) ■ Single NTC design for TM, LL and Imon thermal compensation (for each section) ■ VFDE and GDC - gate drive control for efficiency optimization ■ DPM - dynamic phase management ■ Dual remote sense; 0.5% Vout accuracy ■ Full-differential current sense across DCR ■ AVP - adaptive voltage positioning ■ Dual independent adjustable oscillator ■ Dual current monitor ■ Pre-biased output management ■ Average and per-phase OC protection ■ OV, UV and FB disconnection protection ■ Dual VR_RDY ■ VFQFPN68 8x8 mm package
Applications
■ High-current VRM / VRD for desktop / server / workstation Intel / AMD CPUs ■ DDR3 memory supply
Description
The L6751B is a universal digitally controlled dual PWM DC-DC designed to power Intel’s VR12 and AMD SVI processors and memories: all required parameters are programmable through dedicated pinstrapping and PMBus interface. The device features up to 6-phase programmable operation for the multi-phase section and a single- phase with independent control loops. When configured for memory supply, single-phase (VTT) reference is always tracking multi-phases (VDDQ) scaled by a factor of 2. The L6751B supports power state transitions featuring VFDE, programmable DPM and GDC maintaining the best efficiency over all loading conditions without compromising transient response. The device assures fast and independent protection against load overcurrent, under/overvoltage and feedback disconnections. The device is available in VFQFPN68 8x8 mm package. Table 1. Device summary
1 Typical application circuit and block diagram
1.1 Application circuit
Figure 1. Typical 6-phase application circuit
1.2 Block diagram
Figure 2. Block diagram
2 Pin description and connection diagram
Figure 3. L6751B pin connections (top view)
2.1 Pin description
Table 2. Pin description and holding the PWMx pin to the predefined fixed voltage. 4 PHASE A Connect through resistor divider to multi-phase channel1 switching node.
5 VR_RDY D
output-side of Rg with 100 nF (typ.) to GND. short to the regulated voltage. short to the regulated voltage.
10 CS5N A
output-side of Rg with 100 nF (typ.) to GND.
11 CS4N A
output-side of Rg with 100 nF (typ.) to GND.
12 CS4P A
short to the regulated voltage.
13 CS3P A
short to the regulated voltage.
14 CS3N A
output-side of Rg with 100 nF (typ.) to GND.
15 CS2N A
the phase-side of the channel 2 inductor. the phase-side of the channel 1 inductor.
18 CS1N A
Table 2. Pin description (continued)
19 SOSC A
frequency of 230 kHz. See Section 10 for details.
20 SREF A
implement small positive offset to the regulation.
21 TM A
mation to define the VR_HOT signal and temperature monitoring. and IMON/ILIM thermal compensation for the multi-phase section. In JMode, the pin disables the single-phase section if shorted to GND. Pull up to VCC5 with 1 kΩ to disable the thermal sensor.
22 SPWM /
to fixed voltage defined by PWMx strapping. Connect to VCC5 with 1 kΩ to disable the single-phase section.
23 SENDRV D
24 ILIM A
Multi-phase section current limit. through CLIM to GND to delay OC intervention.
25 VR_HOT D
low). See Section 8 for details.
26 TCOMP A
Thermal monitor sensor gain. pensation (but not thermal sensor). See Section 8 for details.
27 SCSP A
Single-phase section current senses positive input. Connect through an R-C filter to the phase-side of the channel 1 inductor.
28 SCSN A
Single-phase section current senses negative input. Connect through an Rg resistor to the output-side of the channel inductor. Filter the output-side of Rg with 100 nF (typ.) to GND.
29 SIMON A
A current proportional to the single-phase current is sourced from this pin. Connect through a resistor RSIMON to GND. intervention to be controlled.
30 DPM4-6 A
GDC strategies. See Table 11 and Table 12 for details.
31 SRGND A
32 DPM1-3 A
GDC strategies. See Table 11 and Table 12 for details.
33 SFBR A
Remote buffer positive sense.
34 SVSEN A
Output voltage monitor, manages OV and UV protection. Connect with a resistor RSFB // (RSI - CSI) to SFB.
35 SFB A
Error amplifier inverting input.
36 SCOMP A
37 IMAX /
SIMAX registers. See Table 8 and Table 6 for details.
38 GND A
39 SMDATA D
40 SMAL# D PMBus alert
41 SMCLK D PMBus clock
42 NC - Not internally bonded
43 ADDR A
ating mode. See Ta bl e 9 and Ta bl e 6 for details.
44 STM A
mation to define the VR_HOT signal and temperature monitoring. applicable. Short to GND if not used. See Section 8 for details.
45 STCOMP A
Thermal monitor sensor gain. pensation. See Section 8 for details.
46 OSC A
47 VIN A
48 EN D
Level sensitive enable pin (3.3 V compatible).
49 SVCLK
50 ALERT#
V_FIX (AMD mode). Pull to 3.3 V to enter V_FIX mode.
51 SVDATA
52 BOOT /
TMAX registers. See Table 10 for details. 53 VCC5 A Main IC power supply. Operative voltage is 5 V ±5%. Filter with 1 μF MLCC to GND (typ.).
54 GDC A
can be left floating. Always filter with 1 μF MLCC to GND. n/a NC - Not internally bonded.
55 VDRV A
Driving voltage for external drivers.
56 COMP /
57 FB A
Error amplifier inverting input. 58 VSEN A Output voltage monitor, manages OV and UV protection. Connect to the positive side of the load to perform remote sense.
59 FBR A
Remote buffer positive sense. 60 LTB A LTB T echnology input pin. See Section 11.2 for details.
61 RGND A
62 REF A
implement small positive offset to the regulation.
63 IMON A
filtered through CIMON to GND.
64 SVR_RDY
and pulled low when triggering any protection for the single-phase section. Pull up to a voltage lower than 3.3 V (typ.), if not used it can be left floating. device decodes SVC and SVD to determine the boot voltage.
65 ENDRV D
66 PWM6 D
67 PWM5 D
68 PWM4 D
2.2 Thermal data
Table 3. Thermal data
3 Electrical specifications
3.1 Absolute maximum ratings
3.2 Electrical characteristics
Table 4. Absolute maximum ratings Table 5. Electrical characteristics
Table 5. Electrical characteristics (continued)
- Guaranteed by design, not subject to test.
4 Device configuration and pinstrapping tables
spacing among SVI bus lines must be followed. are monitored at the IC power-up. See Table 6, 8, 9, 10 e 11 for details.
4.1 JMode
is recommended to provide both SFBR and SRGND with the same divider. Figure 4. JMode: voltage positioning
4.2 Programming HiZ level
driving different external drivers as well as DrMOS ICs. regulation, the Hiz level is used to force the external MOSFETs in high-impedance state. HiZ level used during the regulation is 1.4 V, if lower, PWM2 information is used. regulation is 2 V, if lower, 1.6 V. and the HiZ level requested. 1 Refer to Ta bl e 1 0 and choose any of the resistor combinations leading to the desired TMAX. 2 In DDR mode, single-phase reference is multi-phase Vout/2 (JMode disabled). Table 6. Device configuration Table 7. Phase number programming
Table 8. IMAX, SIMAX pinstrapping ( Note 1)
10 Open 25 5
Note: 1 Recommended values, divider needs to be connected between VCC5 pin and GND. 2 N is the number of phases programmed for the multi-phase section. Table 9. ADDR pinstrapping ( Note 1, 2)
Note: 1 Recommended values, divider needs to be connected between VCC5 pin and GND. 2 In DDR mode, when enabled, droop has 1/4th scaling factor. address defaults according to AMD specifications.
10 Open OFF
Table 9. ADDR pinstrapping ( Note 1, 2) (continued) Table 10. BOOT / TMAX pinstrapping ( Note 1, 2)
Note: 1 Recommended values, divider needs to be connected between VCC5 pin and GND. 2 BOOT is ignored in AMD mode, only TMAX is operative. 3 Operative mode defined by ADDR pin. See Table 9 for details.
10 Open 100
Table 10. BOOT / TMAX pinstrapping ( Note 1, 2) (continued)
Table 11. DPM pinstrapping ( Note 1)
1 DPM OFF
10 Open 0 0
Note: 1 Suggested values, divider needs to be connected between VCC5 pin and GND. 2 Transition between 1Phase and 2Phase operation is set to 12 A but disabled in PS00h. 3 Transition threshold specified as delta with respect to previous step (DPM23 is wrt DPM12).
4 GDC threshold is defined by combining GDC0 and GDC1 bits defined between the two
different pinstrappings DPM1-3 and DPM4-6. See Table 12 for details.
5 Dynamic phase management disabled, IC always working at maximum possible number of
phases except when in >PS00h when transitioning between 1Phase and 2Phase at 12 A. different pinstrappings DPM1-3 and DPM4-6. See Table 11 for details. 2 N is the number of phases programmed for the multi-phase section. Table 12. GDC threshold definition ( Note 1)
0 GDC OFF
5 Device description and operation
turn, also the system costs by providing the fastest response to a load transition. sense resistor in series to the inductor can also be considered to improve reading precision. current carried by each phase. may configure and program the defaults for the device through dedicated pinstrapping. gate driving voltage and switching frequency to optimize efficiency over the load range. The L6751B is available in VFQFPN68 8x8 mm package. a. VFDE feature can be enabled using dedicated PMBus command. See Section 12 for details. Figure 5. Device initialization
6 Output voltage positioning
Table 6 for the two sections and by programming the droop function effect (see Figure 6). Figure 6. Voltage positioning
6.1 Multi-phase section - phase # programming
required, according to Table 7. resistor used for the active phases.
6.2 Multi-phase section - current reading and current sharing
Figure 7. Current reading voltage error amplifier in order to equalize the current carried by each phase.
6.3 Multi-phase section - defining load-line
rent, causes the output voltage to vary according to the sensed current.
L6751B Output voltage positioning Doc ID 024028 Rev 1 31/58 Figure 7 shows the current sense circuit used to implement the load-line. The current flow- ing across the inductor(s) is read through the R-C filter across the CSxP and CSxN pins. RG programs a trans-conductance gain and generates a current ICSx proportional to the current of the phase. The sum of the ICSx current, with proper gain eventually adjusted by the PMBus commands, is then sourced by the FB pin (IDROOP). RFB gives the final gain to pro- gram the desired load-line slope (Figure 6). Time constant matching between the inductor (L / DCR) and the current reading filter (RC) is required to implement a real equivalent output impedance of the system, therefore avoid- ing over and/or undershoot of the output voltage as a consequence of a load transient. The output voltage characteristic vs. load current is then given by: Equation 4 where R LL is the resulting load-line resistance implemented by the multi-phase section. The RFB resistor can be then designed according to the RLL specifications as follows: Equation 5 Caution: When in DDR mode, and enabled, droop current has a scaling factor equal to 1/4. All the above equations must be scaled accordingly.
6.4 Single-phase section - disable
The single-phase section can be disabled by pulling high the SPWM pin. The related command is rejected.
6.5 Single-phase section - current reading
The single-phase section performs the same differential current reading across DCR as the multi-phase section. According to Section 6.2, the current that flows from the SCSN pin is then given by the following equation (see Figure 7): Equation 6
6.6 Single-phase section - defining load-line
This method introduces a dependence of the output voltage on the load current recovering part of the drop due to the output capacitor ESR in the load transient. Introducing a depen- VOUT VID R FB IDROOP⋅– VID R FB DCR RG RFB RLL RG ISCSN DCR RSG
Output voltage positioning L6751B 32/58 Doc ID 024028 Rev 1 dence of the output voltage on the load current, a static error, proportional to the output cur- rent, causes the output voltage to vary according to the sensed current. Figure 7 shows the current sense circuit used to implement the load-line. The current flow- ing across the inductor DCR is read through RSG. RSG programs a trans-conductance gain and generates a current ISDROOP proportional to the current delivered by the single-phase section that is then sourced from the SFB pin with proper gain eventually adjusted by the PMBus commands. R SFB gives the final gain to program the desired load-line slope (Figure 6). The output characteristic vs. load current is then given by: Equation 7 where RSLL is the resulting load-line resistance implemented by the single-phase section. RSFB resistor can be then designed according to the RSLL as follows:
6.7 Dynamic VID transition support
The L6751B manages dynamic VID transitions that allow the output voltage of both sections to be modified during normal device operation for power management purposes. OV, UV and OC signals are masked during every DVID transition and they are re-activated with proper delay to prevent from false triggering. When changing dynamically the regulated voltage (DVID), the system needs to charge or discharge the output capacitor accordingly. This means that an extra-current I DVID needs to be delivered (especially when increasing the output regulated voltage) and it must be con- sidered when setting the overcurrent threshold of both the sections. This current results: Equation 8 where dV OUT / dTVID depends on the specific command issued (20 mV/μsec. for SetVID_Fast and 5 mV/μsec. for SetVID_Slow). Overcoming the total OC threshold during the dynamic VID causes the device to latch and disable. Set proper filtering on ILIM to pre- vent from false total-OC tripping. As soon as the controller receives a new valid command to set the VID level for one (or both) of the two sections, the reference of the involved section steps up or down according to the target-VID with the programmed slope until the new code is reached. If a new valid command is issued during the transition, the device updates the target-VID level and performs the dynamic transition up to the new code. OV, UV are masked during the transition and re-activated with proper delay after the end of the transition to prevent from false triggering. VSOUT VID R SFB ISDROOP⋅–= VID R SFB DCR RSG RSFB RSLL RSG IDVID COUT dVOUT dTVID
6.7.1 LSLESS startup and pre-bias output
pulse, PWMx outputs switch between logic “0” and logic “1” and ENDRV is set to logic “1”. can occur if starting over a pre-biased output. still allowed to turn on the low-side MOSFET if overvoltage is needed.
6.8 DVID optimization: REF/SREF
remove any undershoot in the transition, each section features DVID optimization circuit. The reference used for the regulation is available on the REF/SREF pin (see Figure 10). V the gain for the voltage loop (see Section 11). the droop current compensating for undershoot on the regulated voltage. Figure 8. SLESS startup: enabled (left) Figure 9. LSLESS startup: disabled
Figure 10. DVID optimization circuit
7 Output voltage monitoring and protection
case the fixed threshold is 2.4 V. Table 13. L6751B protection at a glance. VSEN, SVSEN = +175 mV above reference. Action: IC latch; LS = ON & PWMx = 0 (if applicable); other section: HiZ. VR_READY of the latched section resets (only). Overcurrent (OC) Current monitor across inductor DCR. Dual protection, per-phase and total. Action: UV-Like. VR_READY of the latched section resets (only). Dynamic VID Protection masked with additional delay to prevent from false triggering.
L6751B Output voltage monitoring and protection Doc ID 024028 Rev 1 35/58
7.1 Overvoltage
When the voltage sensed by VSEN and/or SVSEN surpasses the OV threshold, the control- ler acts in order to protect the load from excessive voltage levels avoiding any possible undershoot. To reach this target, a special sequence is performed as per the following list: – The reference performs a DVID transition down to 250 mV on the section which triggered the OV protection. – The PWMs of the section which triggered the protection are switched between HiZ and zero (ENDRV is kept high) in order to follow the voltage imposed by the DVID on-going. This limits the output voltage excursion, protects the load and assures no undershoot is generated (if Vout < 250 mV, the section is HiZ). – The PWMs of the non-involved section are set permanently to HiZ (ENDRV is kept low) in order to realize a HiZ condition. – OSC/ FLT pin is driven high. – Power supply or EN pin cycling is required to restart operation. If the cause of the failure is removed, the converter ends the transition with all PWMs in HiZ state and the output voltage of the section which triggered the protection lower than 250 mV.
7.2 Overcurrent and current monitor
The overcurrent threshold must be programmed to a safe value, in order to be sure that each section does not enter OC during normal operation of the device. This value must take into consideration also the process spread and temperature variations of the sensing ele- ments (inductor DCR). Furthermore, since also the internal threshold spreads, the design must consider the mini- mum/maximum values of the threshold.
7.2.1 Multi-phase section
The L6751B features two independent load indicator signals, IMON and ILIM, to properly manage OC protection, current monitoring and DPM. Both IMON and ILIM source a current proportional to the current delivered by the regulator, as follows: Equation 10 The IMON and ILIM pins are connected to GND through a resistor (R IMON and RILIM respec- tively), implementing a load indicator with different targets.
- IMON is used for current reporting purposes and for the DPM phase shedding. RIMON must be designed considering that IMAX must correspond to 1.24 V (for correct IMAX detection).
- ILIM is used for the overcurrent protection only. RILIM must be designed considering that the OC protection is triggered when V(ILIM)=2.5 V. In addition, the L6751B also performs per-phase OC protection. – Per-phase OC. Maximum information current per-phase (IINFOx) is internally limited to 35 μA. This end-of-scale current (IOC_TH) is compared with the information current generated IMON ILIM DCR RG
Output voltage monitoring and protection L6751B 36/58 Doc ID 024028 Rev 1 for each phase (IINFOx). If the current information for the single-phase exceeds the end-of-scale current (i.e. if IINFOx > IOC_TH), the device turns on the LS MOSFET until the threshold is re-crossed (i.e. until IINFOx < IOC_TH). – Total current OC. The ILIM pin allows a maximum total output current for the system (IOC_TOT) to be defined. ILIM current is sourced from the ILIM pin. By connecting a resistor RILIM to GND, a load indicator with 2.5 V (VOC_TOT) end-of-scale can be implemented. When the voltage present at the ILIM pin crosses VOC_TOT, the device detects an OC and immediately latches with all the MOSFETs of all the sections OFF (HiZ). Typical design considers the intervention of the total current OC before the per-phase OC, leaving this last one as an extreme-protection in case of hardware failures in the external components. Per-phase OC depends on the R G design while total OC is dependant on the ILIM design and on the application TDC and max. current supported. Typical design flow is the following: – Define the maximum total output current (I OC_TOT) according to system requirements (IMAX, ITDC). Considering IMON design, IMAX must correspond to 1.24 V (for correct IMAX detection) while considering ILIM design IOC_TOT has to correspond to 2.5 V. – Design per-phase OC and R G resistor in order to have IINFOx = IOC_TH (35 μA) when IOUT is about 10% higher than the IOC_TOT current. It results: Equation 11 where N is the number of phases and DCR the DC resistance of the inductors. RG should be designed in worst-case conditions. – Design the R IMON in order to have the IMON pin voltage to 1.24 V at the IMAX current specified by the design. It results: Equation 12 where IMAX is max. current requested by the processor (see Intel docs for details). – Design the R ILIM in order to have the ILIM pin voltage to 2.5 V at the IOC_TOT current specified above. It results: Equation 13 where IOC_TOT is the overcurrent switch-over threshold previously defined. – Adjust the defined values according to application bench testing. ILIM in parallel to RILIM can be added with proper time constant to prevent false OC tripping and/or delay. RG
1.1 I OC_TOT⋅() DCR⋅
NI⋅ OCTH RIMON 1.24V R G⋅ RILIM 2.5V R G⋅
to prevent false total-OC tripping during DVID. settings and ratios between the per-phase OC threshold and the total current OC threshold. different than 110%: design flow should be modified accordingly. affecting the precision of the measurement.
7.2.2 Overcurrent and power states
OC level is then scaled as the controller enters >PS00h, as per Table 14.
7.2.3 Single-phase section
SINFOx) is internally limited to 35 μA. LS MOSFET until the threshold is re-crossed (i.e. until ISINFOx < ISOC_TH). Table 14. Multi-phase section OC scaling and power states
Output voltage monitoring and protection L6751B 38/58 Doc ID 024028 Rev 1 Typical design considers the intervention of the total current OC before the per-phase OC, leaving this last one as an extreme protection in case of hardware failures in the external components. Total current OC is, moreover, dependant on the SIMON design and on the application TDC and MAX current supported. Typical design flow is the following: – Define the maximum total output current (I SOC_TOT) according to system requirements (ISMAX, ISTDC). Considering ISMON design, ISMAX must correspond to
1.24 V (for correct SIMAX detection) so ISOC_TOT results defined, as a
consequence, as – Design per-phase OC and R SG resistor in order to have ISINFOx = ISOC_TH (35 μA) when ISOUT is about 10% higher than the ISOC_TOT current. It results: Equation 14 where DCR is the DC resistance of the inductors. RSG should be designed in worst-case conditions. – Design the total current OC and R SIMON in order to have the SIMON pin voltage to 1.24 V at the ISMAX current specified by the design. It results: Equation 15 where ISMAX is max. current requested by the processor (see Intel docs for details). – Adjust the defined values according to application bench tests. SIMON in parallel to RSIMON can be added with proper time constant to prevent false OC tripping. Note: This is the typical design flow. Custom design and specifications may require different settings and ratios between the per-phase OC threshold and the total current OC threshold. Applications with big ripple across inductors may be required to set per-phase OC to values different than 110%: design flow should be modified accordingly. ISOC_TOT ISMAX 1.55⋅ 1.24⁄= RSG
1.1 I SOC_TOT⋅() DCR⋅
1.24V R SG⋅ DCR RSG
8 Single NTC thermal monitor and compensation
sensor (NTC) to optimize the overall application cost without compromising performance. Thermal monitor is featured for both single-phase and multi-phase sections.
8.1 Thermal monitor and VR_HOT
observable at the TM/STM pin. characteristic with the one coming from the recommended NTC. as long as the overtemperature event lasts). Figure 11. Thermal monitor connections
8.2 Thermal compensation
Single NTC thermal monitor and compensation L6751B 40/58 Doc ID 024028 Rev 1 increases. Un-compensated systems show temperature dependencies on the regulated voltage, overcurrent protection and current reporting. The temperature information available on the TM/STM pin and used for thermal monitor may be used also for this purpose. By comparing the voltage on the TM/STM pin with the voltage present on the TCOMP/STCOMP pin, the L6751B corrects the I DROOP/ISDROOP current used for voltage positioning (see Section 6.3), so recovering the DCR temperature deviation. Depending on NTC location and distance from the inductors and the available airflow, the correlation between NTC temperature and DCR temperature may be different: TCOMP/STCOMP adjustments allow the gain between the sensed temperature and the correction made upon the I DROOP/ISDROOP current to be modified. Short TCOMP/STCOMP to GND to disable thermal compensation (no correction of IDROOP/ISDROOP is made).
8.3 TM/STM and TCOMP/STCOMP design
This procedure applies to both single-phase and multi-phase sections. 1. Properly choose the resistive network to be connected to the TM pin. Recommended values/network is reported in Figure 11. 2. Connect voltage generator to the TCOMP pin (default value 3.3 V). 3. Power on the converter and load the thermal design current (TDC) with the desired cooling conditions. Record the output voltage regulated as soon as the load is applied. 4. Wait for thermal steady-state. Adjust down the voltage generator on the TCOMP pin in order to get the same output voltage recorded at point #3. 5. Design the voltage divider connected to TCOMP (between VCC5 and GND) in order to get the same voltage set to TCOMP at point #4. 6. Repeat the test with the TCOMP divider designed at point #5 and verify the thermal drift is acceptable. In case of positive drift (i.e. output voltage at thermal steady-state is bigger than output voltage immediately after loading TDC current), change the divider at the TCOMP pin in order to reduce the TCOMP voltage. In case of negative drift (i.e. output voltage at thermal steady-state is smaller than output voltage immediately after loading TDC current), change the divider at the TCOMP pin in order to increase the TCOMP voltage. 7. The same procedure can be implemented with a variable resistor in place of one of the resistors of the divider. In this case, once the compensated configuration is found, simply replace the variable resistor with a resistor with the same value.
9 Efficiency optimization
improve overall system efficiency, according to Table 15.
9.1 Dynamic phase management (DPM)
according to the delivered current still maintaining the benefits of the multi-phase regulation. the current at which the controller changes from 2 to 3 phases and so on. interleaving mode with all the available phases enabled. compatible, DPM is re-enabled after proper delay. IMON pin. Increasing the capacitance results in increased delay in the DPM intervention. See Section 7.2.1 for guidelines in designing the IMON load indicator. Table 15. Efficiency optimization
Efficiency optimization L6751B 42/58 Doc ID 024028 Rev 1 ‘ILIM pin is lightly filtered in order to perform fast reaction of OC protection while IMON is heavily filtered to perform correct averaging of the information. While working continuously in DPM, the device compares the information of IMON and ILIM: ILIM voltage is divided in N steps whose width is VOCP/(2*N) (where VOCP = 2.5 V and N the number of stuffed phases). If the DPM phase number resulting from IMON is not coherent with the step in which ILIM stays, the phase number is increased accordingly. The mechanism is active only to increase the phase number which is reduced again by DPM.
9.2 Variable frequency diode emulation (VFDE)
As the current required by the load is reduced, the L6751B progressively reduces the number of switching phases according to DPM settings on the multi-phase section. If single- phase operation is configured, when the delivered current approaches the CCM/DCM boundary, the controller enters VFDE operation. Single-phase section, being a single- phase, enters VFDE operation always when the delivered current approaches the CCM/DCM boundary. In a common single-phase DC-DC converter, the boundary between CCM and DCM is when the delivered current is perfectly equal to 1/2 of the peak-to-peak ripple into the inductor (Iout = Ipp/2). Further decreasing the load in this condition maintaining CCM operation would cause the current into the inductor to reverse, so sinking current from the output for a part of the off- time. This results in a poorly efficient system. The L6751B is able (via the CSPx/CSNx pins) to detect the sign of the current across the inductor (zero cross detection, ZCD), so it is able to recognize when the delivered current approaches the CCM/DCM boundary. In VFDE operation, the controller fires the high-side MOSFET for a TON and the low-side MOSFET for a TOFF (the same as when the controller works in CCM mode) and waits the necessary time until next firing in high impedance (HiZ). The consequence of this behavior is a linear reduction of the “apparent” switching frequency that, in turn, results in an improvement of the efficiency of the converter when in very light load conditions. The “apparent” switching frequency reduction is limited to 30 kHz so as not to enter the audible range.
9.2.1 VFDE and DrMOS
9.3 Gate drive control (GDC)
through the PMBus, the device switches this pin (GDC) between VCC5 or VDRV (inputs). carefully control the external MOSFET driving voltage. according to the delivered current. automatically updated as lower power states are commanded through the SVI interface. threshold compared with DPM thresholds, it is possible to achieve different performances. achievable with the active and passive components available. Figure 12. Output current vs. switching frequency in PSK mode
10 Main oscillator
(number of configured phases). of 11.5 kHz/μA for the single-phase section, see Figure 14. Figure 14. R OSC vs. FSW per phase (ROSC to GND - left; ROSC to 3.3 V - right)
11 System control loop compensation
the number of the configured phases), see Figure 15. Figure 15. Equivalent control loop.
- RLL is the equivalent output resistance determined by the droop function (voltage positioning)
- ZP(s) is the impedance resulting from the parallel of the output capacitor (and its ESR) and the applied load RO
- ZF(s) is the compensation network impedance
- ZL(s) is the equivalent inductor impedance
- A(s) is the error amplifier gain
- is the PWM transfer function. The control loop gain is designed in order to obtain a high DC gain to minimize static error and to cross the 0 dB axes with a constant -20 dB/dec slope with the desired crossover frequency ω T. Neglecting the effect of ZF(s), the transfer function has one zero and two poles; both poles are fixed once the output filter is designed (LC filter resonance ωLC) and the zero (ωESR) is fixed by ESR and the droop resistance. Ref FB COMP VSEN RF CF RFB PWM L/N ESR CO RO d VCOMP VOUT ZF(s) ZFB(s) IDROOP FBR RGND VCOMP AM14846v1 GLOOP s() PWM Z F s() RLL ZP s()+()⋅⋅ ZP s() ZL s()+[] ZF s() ⎛⎞ RFB⋅+⋅ PWM 9 ΔVOSC
Figure 16. Control loop bode diagram and fine tuning. C resonance assures a simple -20 dB/dec shape of the gain. a frequency lower than the above reported zero.
11.1 Compensation network guidelines
F to increase the system bandwidth accordingly. – Decrease R F to decrease the system bandwidth accordingly. out (while it is charged by VIN-VOUT during a load appliance).
System control loop compensation L6751B 48/58 Doc ID 024028 Rev 1 Note: The introduction of a capacitor (C I) in parallel to RFB significantly speeds up the transient response by coupling the output voltage dV/dt on the FB pin, so using the error amplifier as a comparator. The COMP pin suddenly reacts and, also thanks to the LTB Technology control scheme, all the phases can be turned on together to immediately give the required energy to the output. Typical design considers starting from values in the range of 100 pF , validating the effect by bench testing. Additional series resistor (R I) can also be used.
11.2 LTB Technology
LTB Technology further enhances the performance of the controller by reducing the system latencies and immediately turning on all the phases to provide the correct amount of energy to the load optimizing the output capacitor count. LTB Technology monitors the output voltage through a dedicated pin detecting load- transients with selected dV/dt, it cancels the interleaved phase-shift, turning on simultaneously all phases. The LTB detector is able to detect output load transients by coupling the output voltage through an R LTB - CLTB network. After detecting a load transient, all the phases are turned on together and the EA latencies also result as bypassed. Sensitivity of the load transient detector can be programmed in order to control precisely both the undershoot and the ring-back. LTB Technology design tips. – Decrease R LTB to increase the system sensitivity making the system sensitive to smaller dVOUT – Increase C LTB to increase the system sensitivity making the system sensitive to higher dV/dt – Increase R i to increase the width of the LTB pulse – Increase C i to increase the LTB sensitivity over frequency.
12 PMBus support (preliminary)
documentation for further information (www.pmbus.org). Table 16. Supported commands
Note: 1 Applies to multi-phase only. 2 Applies to single-phase only.
12.1 Enabling the device through PMBus
12.2 Controlling Vout through PMBus
– Offset above SVI commanded voltage. – Fixed Vout regardless of SVI. voltage remains unchanged until the next SetVID command).
12.3 Input voltage monitoring (READ_VIN)
value of the input voltage measured as a voltage (linear format, N=-4). The divider needs to be programmed to have 1.24 V on the pin when VIN=15.9375 V. UP=118.5 kΩ and RDOWN=10 kΩ. Errors in defining the divider lead to monitoring errors accordingly. Filter VIN pin locally to GND to increase stability of the voltage being measured.
12.4 Duty cycle monitoring (READ_DUTY)
the aim of calculating input current inexpensively (no need for input current-sense resistors). the duty cycle as a percentage (linear format, N=-2). Figure 17. Device initialization: PMBus controlling Vout
12.5 Output voltage monitoring (READ_VOUT)
The dedicated PMBus command allows the user to monitor output voltage for both sections. The L6751B returns the value of the programmed VID in VID LSBs (i.e. number of LSBs.
12.6 Output current monitoring (READ_IOUT)
The dedicated PMBus command allows the user to monitor output current for both sections. VR12 register 15h) in Amperes (linear format, N=0).
12.7 Temperature monitoring (READ_TEMPERATURE)
12.8 Overvoltage threshold setting
single-phase sections to be programmed. configured for multi-phase and single-phase sections. Inc. This license does not extend to stand-lone power supply products. Table 17. OV threshold setting
Table 18. L6751B VFQFPN68 8x8 mm mechanical data
Figure 18. L6751B VFQFPN68 8x8 mm drawing
Table 19. Document revision history 07-Dec-2012 1 Initial release.