L6741 STMICROELECTRONICS | Alldatasheet
Document overview
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- PDF pages: 16
Technical content
Datasheet sections
- 1 Typical application cir cuit and block diagram
- 1.1 Application circuit
- 1.2 Block diagram
- 2 Pins description and connection diagrams
- 2.1 Pin description
- 3 Thermal data
- 4 Electrical specifications
- 4.1 Absolute maximum ratings
- 4.2 Electrical characteristics
- 5 Device description and operation
- 5.1 High-impedance (HiZ) management
- 5.2 Preliminary OV protection
- 5.3 Internal BOOT diode
- 5.4 Gate driver voltage flexibility
- 5.5 Power dissipation
- 5.6 Layout guidelines
- 6 Package mechanical data
- 7 Revision history
Features
■ Dual MOSFET driver for synchronous rectified converters ■ High driving current for fast external MOSFET switching ■ High frequency operation ■ Integrated bootstrap diode ■ Adaptive dead-time management ■ Flexible gate-drive: 5V to 12V compatible ■ High-impedance (HiZ) management for output stage shutdown ■ Preliminary OV protection ■ SO-8 package
Applications
■ High current VRM / VRD for Desktop / Server / Workstation CPUs ■ High current DC / DC converters
Description
L6741 is a flexible, high-frequency dual-driver specifically designed to drive N-channel MOSFETs connected in Synchronous-Rectified Buck topology. Combined with ST PWM controllers, the driver allows implementing complete voltage regulator solutions for modern high-current CPUs. L6741 embeds high-current drivers for both high-side and low-side MOSFETS. The device accepts flexible power supply (5V to 12V) to optimize the gate-drive voltage for High-Side and Low-Side maximizing the System Efficiency. The Bootstrap diode is embedded saving the use of external diodes. Anti shoot-through management avoids high-side and low-side mosfet to conduct simultaneously and, combined with Adaptive Dead-Time control, minimizes the LS body diode conduction time. L6741 embeds Preliminary OV Protection: after Vcc overcomes the UVLO and while the device is in HiZ, the Low-Side MOSFET is turned ON to protect the load in case the output voltage overcomes a warning threshold protecting the load from High-Side MOSFET failures. The driver is available is SOP8 package. SO-8 Table 1. Device summary
1 Typical application circuit and block diagram
1.1 Application circuit
Figure 1. Typical application circuit
1.2 Block diagram
Figure 2. Block diagram
2 Pins description and connection diagrams
Figure 3. Pins connection (Top view)
2.1 Pin description
Table 2. Pins descriptions
4 LGATE
1U G A T E High-side driver output. Connect to High-Side MOSFET gate. through a RBOOT - CBOOT capacitor to the PHASE pin. Section 5.3 for guidance in designing the capacitor value. Control input for the driver (5V compatible). which causes all mosfets to be OFF . See Section 5.1 for details about HiZ. useful to reduce dissipated power especially in high frequency applications. 12V. Bypass with low-ESR MLCC capacitor to GND.
7 PVCC
Integrated bootstrap diode anode supply.
8 PHASE
High-side driver return path. Connect to the high-side MOSFET source.
3 Thermal data
Table 3. Thermal data
4 Electrical specifications
4.1 Absolute maximum ratings
Table 4. Absolute maximum ratings
4.2 Electrical characteristics
Table 5. Electrical characteristics (VCC = 12V±15%, TJ = 0°C to 70°C unless otherwise specified).
- Parameter guaranteed by designed, not fully tested in production
5 Device description and operation
MOSFETS connected as Step-Down DC-DC Converter driven by an external PWM signal. multiple MOS to reduce the equivalent RdsON), maintaining fast switching transition. The driver for the High-Side MOSFET use BOOT pin for supply and PHASE pin for return. The driver for the Low-Side MOSFET use the VCC pin for supply and PGND pin for return. the current flowing in the inductor is negative, the source of highside mosfet will never drop. allows the system to regulate even if the current is negative. HiZ: both MOSFETS are kept in the OFF state until PWM transition. reset from a PWM transition. 5V, 12V bus or any intermediate bus that allows the conversion can be chosen freely. Figure 4. Timing diagram
Device description and operation L6741
5.1 High-impedance (HiZ) management
The Driver is able to manage High-Impedance state by keeping all MOSFETs in off state. If the PWM signal remains in the HiZ window for a time longer than the hold-off time, the device detects the HiZ condition so turning off all the MOSFETs. The HiZ window is defined as the PWM voltage range comprised between V PWM_IL and VPWM_IH. The device may exit from the HiZ state only after a PWM transition to logic zero (VPWM < VPWM_IL). See Figure 4 for details about HiZ timings. The implementation of the High-Impedance state allows the controller that will be connected to the driver to manage High-Impedance state of its output, avoiding to produce negative undershoot on the regulated voltage during the shut-down stage. Furthermore, different power management states may be managed such as pre-bias start-up.
5.2 Preliminary OV protection
After VCC has overcome its UVLO threshold and while the PWM signal is in the HiZ window, L6741 activate the Preliminary-OV protection. The intent of this protection is to protect the load especially from High-Side MOSFET fail- ures during the system start-up. In fact, VRM, and most in general PWM controllers, have a 12V bus compatible turn-on threshold and results to be non-operative if VCC is below that turn-on thresholds (that results being in the range of about 10V). In case of an High-Side mosfet failure, the controller won’t recognize the over voltage until VCC = ~10V (unless other special features are implemented): but in that case the output voltage is already at the same voltage (~10V) and the load (CPU in most cases) already burnt. L6741 by-pass the PWM controller by latching on the Low-Side MOSFET in case the PHASE pin voltage overcome 2V during the HiZ state. When the PWM input exits form the HiZ window, the protection is reset and the control of the output voltage is transferred to the controller connected to the PWM input. Since the Driver has its own UVLO threshold, a simple way to provide protection to the out- put in all conditions when the device is OFF consists in supplying the controller through the SB bus: 5VSB is always present before any other voltage and, in case of High-Side short, the Low-Side mosfet is driven with 5V assuring a reliable protection of the load. Preliminary OV is active after UVLO and while the Driver is in HiZ state and it is disabled after the first PWM transition. The controller will have to manage its output voltage from that time on.
5.3 Internal BOOT diode
L6741 embeds a boot diode to supply the High-Side driver saving the use of an external component. Simply connecting an external capacitor between BOOT and PHASE complete the High-Side supply connections. To prevent bootstrap capacitor to extra-charge as a consequence of large negative spikes, an external series resistance R BOOT (in the range of few ohms) may be required in series to BOOT pin.
bootstrap according to the desired discharge and depending on the selected mosfet. Figure 5. Bootstrap capacitance design
5.4 Gate driver voltage flexibility
range between 5V to 12V buses. impacting the bootstrap capacitor voltage) and can range between 5V to 12V buses.
5.5 Power dissipation
to avoid overcoming the maximum junction operative temperature. Two main terms contribute in the device power dissipation: bias power and drivers' power.
- Device Power (PDC) depends on the static consumption of the device through the supply pins and it is simply quantifiable as follow:
- Drivers' power is the power needed by the driver to continuously switch ON and OFF the external MOSFETs; it is a function of the switching frequency and total gate charge of the selected MOSFETs. It can be quantified considering that the total power P SW dissipated to switch the MOSFETs dissipated by three main factors: external gate resistance (when present), intrinsic MOSFET resistance and intrinsic driver resistance. 0.0 0.5 1.0 1.5 2.0 2.5 0 1 02 03 04 05 06 07 08 09 0 1 0 0 High-Side MOSFET Gate Charge [nC] BOOT Cap discharge [V] Cboot = 47nF Cboot = 100nF Cboot = 220nF Cboot = 330nF Cboot = 470nF 500 1000 1500 2000 2500 Boot Cap Delta Voltage [V] Bootstrap Cap [uF] Qg = 10nC Qg = 25nC Qg = 50nC Qg = 100nC PDC VCC ICC VPVCC IPVCC⋅+⋅=
consideration the effect of external gate resistors on the power dissipated by the driver. resulting in a general cooling of the device. Figure 6. Equivalent circuit for MOSFET drive.
5.6 Layout guidelines
L6741 provides driving capability to implement high-current step-down DC-DC converters. thermal cooling and airflow. needs to be minimized to reduce the related parasitic effect. The use of multi-layer printed circuit board is recommended. use wide copper traces to minimize parasitic inductance. but has an additional consequence: it causes the bootstrap capacitor to be over-charged. the limitation of the spike present on the BOOT pin. reach its best thermal performances. Figure 7. Driver turn-on and turn-off paths
Figure 8. External components placement example.
6 Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com
Figure 9. Package dimensions Table 6. SO-8 mechanical data
- Dimensions D does not include mold fl ash, protru-sions or gate burrs. Mold flash, potrusions or gate burrs
shall not exceed 0.15mm (.006inch) in total (both side).
7 Revision history
Table 7. Document revision history 20-Aug-2007 1 Initial release.