L6731D STMICROELECTRONICS | Alldatasheet
Document overview
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- PDF pages: 23
Technical content
Datasheet sections
- 1 Summary description
- 1.1 Functional description
- 2 Electrical data
- 2.1 Maximum rating
- 2.2 Thermal data
- 3 Pin connections and functions
- 4 Electrical characteristics
- 5 Device description
- 5.1 Oscillator
- 5.2 Internal LDO
- 5.3 Bypassing the LDO to avoid the voltage drop with low Vcc
- 5.4 Internal and external references
- 5.5 Error amplifier
- 5.6 Soft-start
- 5.7 Driver section
- 5.8 Monitoring and protections
- 5.9 HICCUP mode during an OCP
- 5.10 Thermal shutdown
- 5.11 Minimum on-time (TON, MIN)
- 6 Application details
- 6.1 Inductor design
- 6.2 Output capacitors
- 6.3 Input capacitors
- 6.4 Compensation network
- 7 Package mechanical data
- 8 Revision history
Features
■ Input voltage range from 1.8 V to 14 V ■ Supply voltage range from 4.5 V to 14 V ■ Adjustable output voltage down to 0.6 V with ±0.8 % Accuracy over line voltage and temperature (0 °C~125 °C) ■ Fixed frequency voltage mode control ■ TON lower than 100 ns ■ 0 % to 100 % duty cycle ■ VDDR input sense ■ Regulates VTT and VTTREF within 1 % of VDDQ ■ Soft-start and inhibit ■ High current embedded drivers ■ Predictive anti-cross conduction control ■ Programmable high-side and low-side RDS(on) sense over-current-protection ■ Selectable switching frequency 250 kHz / 500 kHz ■ Power good output ■ Sink/source capability for DDR memory and termination supply ■ Over-voltage protection ■ Thermal shutdown ■ Package: HTSSOP16
Applications
■ High performance / high density DC-DC modules ■ Low voltage distributed DC-DC ■ niPoL converters ■ DDR memory supply ■ DDR termination supply ■ Graphic cards HTSSOP16 (exposed pad) Table 1. Device summary
L6731D Summary description
1 Summary description
The controller is an integrated circuit realized in BCD5 (BiCMOS-DMOS, version 5) fabrication that provides complete control logic and protection for high performance step-down DC-DC and niPoL converters. It is designed to drive N-channel MOSFETs in a synchronous rectified buck topology. The output voltage of the converter can be precisely regulated down to 600 mV with a maximum tolerance of ±0.8 %. If an external reference is used, it will be transferred divided by 2 to the N.I. input of the error-amplifier, in accordance to the DDR memory specifications. An internal resistor divider and a voltage buffer allow to achieve an accuracy of 1 % on both Vtt and Vttref. It's possible to provide an external reference from 0V to 2.5 V in order to meet the specification for DDRI and DDRII. The input voltage can range from 1.8 V to 14 V, while the supply voltage can range from 4.5 V to 14 V. High peak current gate drivers provide for fast switching to the external power section, and the output current can be in excess of 20 A. The PWM duty cycle can range from 0 % to 100 % with a minimum on-time (T ON, MIN) lower than 100 ns making possible conversions with very low duty cycle at high switching frequency. The device provides voltage-mode control that includes a selectable frequency oscillator (250 kHz or 500 kHz). The error amplifier features a 10 MHz gain-bandwidth-product and 5 V/µs slew-rate that permits to realize high converter bandwidth for fast transient response. The device monitors the current by using the R DS(on) of both the high-side and low-side MOSFET(s), eliminating the need for a current sensing resistor and guaranteeing an effective over-current-protection in all the application conditions. When necessary, two different current limit protections can be externally set through two external resistors. During the soft-start phase a constant current protection is provided while after the soft-start the device enters in hiccup mode in case of over-current. The converter can always sink current. Other features are power good, not latched over-voltage-protection, feed-back disconnection and thermal shutdown. The HTSSOP16 package allows the realization of really compact DC/DC converters.
1.1 Functional description
Figure 1. Block diagram
2 Electrical data
2.1 Maximum rating
2.2 Thermal data
Table 2. Absolute maximum ratings Table 3. Thermal data
- Package mounted on demonstration board
3 Pin connections and functions
Figure 2. Pin connection (top view) Table 4. Pin functions
1 PGOOD
2 V TTREF
memory itself. Filter to GND with 10 nF capacitor. 3 SGND All the internal references are referred to this pin.
5 COMP This pin is connected to the error amplifier output and is used to
compensate the voltage control feedback loop.
6 SS/INH
7 DDR-IN
8 OCL
A resistor connected from this pin to ground sets the valley- current-limit.
9 OCH
10 PHASE
11 HGATE This pin is connected to the high-side MOSFET(s) gate.
12 BOOT
13 PGND This pin has to be connected closely to the low-side MOSFET(s) source in
order to reduce the noise injection into the device. 14 LGATE This pin is connected to the low-side MOSFET(s) gate.
15 V CCDR
5 V internally regulated voltage. It is used to supply the internal drivers. Filter it to ground with at least 1 µF ceramic cap.
16 V CC
The operative supply voltage range is from 4.5 V to 14 V. Table 4. Pin functions (continued)
4 Electrical characteristics
VCC = 12 V, TA = 25 °C unless otherwise specified. Table 5. Electrical characteristics
Table 5. Electrical characteristics (continued) Table 6. Thermal characteristics (V CC = 12 V)
5 Device description
5.1 Oscillator
5.2 Internal LDO
CC pin and the output (5 V) is the VCCDR pin (Figure 3.). Figure 3. LDO block diagram
5.3 Bypassing the LDO to avoid the voltage drop with low Vcc
avoid this the LDO can be bypassed.
5.4 Internal and external references
- VEAREF from 0 % to 80 % of VCCDR -> External reference/FSW = 250 kHz
- VEAREF from 80 % to 95 % of VCCDR -> VREF = 0.6 V/FSW = 500 kHz
- VEAREF from 95 % to 100 % of VCCDR -> VREF = 0.6 V/FSW = 250 kHz Providing an external reference from 0V to 450mV the output voltage will be regulated but some restrictions must be considered:
- OV threshold saturates to a minimum value of 300 mV (OV is tracking the reference; tracking small references will result in a narrow threshold reducing noise immunity)
- The under-voltage-protection doesn't work;
- The PGOOD signal remains low; To set the resistor divider it must be considered that a 100 k pull-down resistor is integrated into the device (see Figure 5.). Finally it must be taken into account that the voltage at the DDR-IN pin is captured by the device at the start-up when VCC is about 4 V.
Figure 4. Bypassing the LDO
5.5 Error amplifier
5.6 Soft-start
generator. The initial value for this current is 35 µA and charges the capacitor up to 0.5V. After that it becomes 10 µA until the final charge value of approximately 4 V (see Figure 6.). Figure 5. Error amplifier reference Figure 6. Device start-up: voltage at the SS pin
5.7 Driver section
is sinking current for example and, in this case, an adaptive dead time control operates.
5.8 Monitoring and protections
Figure 7. OVP
MOSFET as an over-voltage cause.
- Peak current limit
- Valley current limit The peak current protection is active when the high-side MOSFET(s) is turned on, after a masking time of about 100 ns. The valley-current-protection is enabled when the low-side MOSFET(s) is turned on after a masking time of about 400 ns. If, when the soft-start phase is completed, an over current event occurs during the on time (peak-current-protection) or during the off time (valley-current-protection) the device enters in HICCUP mode: the high- side and low-side MOSFET(s) are turned OFF , the soft-start capacitor is discharged with a constant current of 10 µA and when the voltage at the SS pin reaches 0.5 V the soft-start phase restarts. During the soft-start phase the OCP provides a constant-current-protection. If during the T ON the OCH comparator triggers an over current the high-side MOSFET(s) is immediately turned OFF (after the masking time and the internal delay) and returned on at the next PWM cycle. The limit of this protection is that the T ON can't be less than masking time plus propagation delay because during the masking time the peak-current-protection is disabled. In case of very hard short circuit, even with this short TON, the current could escalate. The valley-current-protection is very helpful in this case to limit the current. If during the off- time the OCL comparator triggers an over current, the high-side MOSFET(s) is not turned on until the current is over the valley-current-limit. This implies that, if it is necessary, some pulses of the high-side MOSFET(s) will be skipped, guaranteeing a maximum current due to the following formula:
Figure 8. OVP: the low-side MOSFET is turned-on in advance
over current condition that persists also in the soft-start phase. of the reference, the IC will enter HICCUP mode.
5.9 HICCUP mode during an OCP
5.10 Thermal shutdown
to 120 °C and, in any case, until the voltage at the soft-start pin reaches 500 mV.
5.11 Minimum on-time (T ON, MIN)
Figure 9. Constant current and hiccup mode during an OCP
6 Application details
6.1 Inductor design
The inductance value is defined by a compromise between the transient response time, the efficiency, the cost and the size. The inductor has to be calculated to sustain the output and the input voltage variation to maintain the ripple current (∆I L) between 20 % and 30 % of the maximum output current. The inductance value can be calculated with the following relationship: Equation 2 Where F SW is the switching frequency, Vin is the input voltage and Vout is the output voltage. Increasing the value of the inductance reduces the ripple current but, at the same time, increases the converter response time to a load transient. If the compensation network is well designed, during a load transient the device is able to set the duty cycle to 100 % or to 0 %. When one of these conditions is reached, the response time is limited by the time required to change the inductor current. During this time the output current is supplied by the output capacitors. Minimizing the response time can minimize the output capacitor size.
6.2 Output capacitors
The output capacitors are basic components for the fast transient response of the power supply. They depend on the output voltage ripple requirements, as well as any output voltage deviation requirement during a load transient. During a load transient, the output capacitors supply the current to the load or absorb the current stored in the inductor until the converter reacts. In fact, even if the controller recognizes immediately the load transient and sets the duty cycle at 100 % or 0 %, the current slope is limited by the inductor value. The output voltage has a first drop due to the current variation inside the capacitor (neglecting the effect of the ESL): Equation 3 Moreover, there is an additional drop due to the effective capacitor discharge or charge that is given by the following formulas: Equation 4 Equation 5 Formula (4) is valid in case of positive load transient while the formula (5) is valid in case of negative load transient. D MAX is the maximum duty cycle value that in the L6731D is 100%. Vin Vout IFsw VoutVinL L ⋅∆⋅ ESRIoutVoutESR ⋅∆=∆ )maxmin,(2 VoutDVinCout LIoutVoutCOUT −⋅⋅⋅ ⋅∆=∆ VoutCout LIoutVoutCOUT ⋅∆=∆ 2
Application details L6731D For a given inductor value, minimum input voltage, output voltage and maximum load transient, a maximum ESR and a minimum Cout value can be set. The ESR and Cout values also affect the static output voltage ripple. In the worst case the output voltage ripple can be calculated with the following formula: Equation 6 Usually the voltage drop due to the ESR is the biggest one while the drop due to the capacitor discharge is almost negligible.
6.3 Input capacitors
The input capacitors have to sustain the RMS current flowing through them, that is: Equation 7 Where D is the duty cycle. The equation reaches its maximum value, IOUT /2 with D = 0.5. The losses in worst case are: Equation 8
6.4 Compensation network
The loop is based on a voltage mode control (Figure 18.). The output voltage is regulated to the internal/external reference voltage and scaled by the external resistor divider. The error amplifier output V COMP is then compared with the oscillator triangular wave to provide a pulse-width modulated (PWM) with an amplitude of VIN at the PHASE node. This waveform is filtered by the output filter. The modulator transfer function is the small signal transfer function of V OUT/VCOMP. This function has a double pole at frequency FLC depending on the L-COUT resonance and a zero at FESR depending on the output capacitor's ESR. The DC Gain of the modulator is simply the input voltage VIN divided by the peak-to-peak oscillator voltage: VOSC. 1( FswCoutESRIVout L )1( DDIoutIrms −⋅⋅= 2)5.0( IoutESRP ⋅⋅=
- Modulator singularity frequencies: Equation 9 Equation 10
- Compensation network singularity frequencies: Equation 11
Figure 11. Compensation network
- Compensation network design: – Put the gain R 5/R3 in order to obtain the desired converter bandwidth Equation 15 – Place ωZ1 before the output filter resonance ωLC; – Place ωZ2 at the output filter resonance ωLC; – Place ωP1 at the output capacitor ESR zero ωESR; – Place ωP2 at one half of the switching frequency; – Check the loop gain considering the error amplifier open loop gain.
Figure 12. Asymptotic bode plot of converter's open loop gain
7 Package mechanical data
conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 13. HTSSOP16 mechanical data
8 Revision history
Table 7. Document revision history 21-Dec-2005 1 Initial release.