L6727 STMICROELECTRONICS | Alldatasheet
Document overview
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Technical content
Datasheet sections
- 1 Typical application cir cuit and block diagram
- 1.1 Application circuit
- 1.2 Block diagram
- 2 Pins description and connection diagrams
- 2.1 Pin descriptions
- 2.2 Thermal data
- 3 Electrical specifications
- 3.1 Absolute maximum ratings
- 3.2 Electrical characteristics
- 4 Device description
- 5 Driver section
- 5.1 Power dissipation
- 6 Soft Start and Disable
- 6.1 Low-Side-Less Start up (LSLess)
- 6.2 Enable / Disable
- 7 Over current protection
- 7.1 Over current threshold setting
- 8 Output voltage monitor and pr otections
- 8.1 Under voltage protection
- 8.2 Over voltage protection
- 8.3 Feedback disconnection protection
- 8.4 Under voltage lock out
Single phase PWM controller Feature ■ Flexible power supply from 5V to 12V ■ Power conversion input as low as 1.5V ■ 1% output voltage accuracy ■ High-current integrated drivers ■ Adjustable output voltage ■ 0.8V internal reference ■ Simple voltage mode control loop ■ Sensorless and programmable OCP across Low-Side RdsON ■ Oscillator internally fixed at 300kHz ■ Internal Soft-Start ■ LS-LESS to manage pre-bias start-up ■ Disable function ■ OV / UV protection ■ FB disconnection protection ■ SO-8 package
Applications
■ Subsystem power supply (MCH, IOCH, PCI...) ■ Memory and termination supply ■ CPU & DSP power supply ■ Distributed power supply ■ General DC / DC converters
Description
L6727 is a single-phase step-down controller with integrated high-current drivers that provides complete control logic, protections and reference voltage to realize in an easy and simple way general DC-DC converters by using a compact SO-8 package. Device flexibility allows managing conversions with power input V IN as low as 1.5V and device supply voltage in the range of 5V to 12V. L6727 provides simple control loop with voltage- mode error-amplifier. The integrated 0.8V reference allows regulating output voltages with ±1% accuracy over line and temperature variations. Oscillator is internally fixed to 300kHz. L6727 provides programmable over current protection as well as over and under voltage protection. Current information is monitored across the Low-Side mosfet R dsON saving the use of expensive and space-consuming sense resistors while output voltage is monitored through FB pin. FB disconnection protection prevents excessive and dangerous output voltages in case of floating FB pin. SO-8 Table 1. Device summary
1 Typical application circuit and block diagram
1.1 Application circuit
Figure 1. Typical application circuit
1.2 Block diagram
Figure 2. Block diagram
2 Pins description and connection diagrams
Figure 3. Pins connection (top view)
2.1 Pin descriptions
Table 2. Pins descriptions
4 VCC
and provide necessary bootstrap diode from VCC. 2 UGATE HS Driver Output. Connect to HS mosfet gate. 3G N D All internal references, logic and drivers are connected to this pin. Connect to the PCB ground plane. 4 LGATE LS Driver Output. Connect to LS mosfet gate. 5V C C Device and LS Driver power supply. Operative range from 4.1V to 13.2V. Filter with at least 1µF MLCC to GND. Error Amplifier Inverting Input.
7 COMP / DIS
compensate the control-loop. VCC > 5V, ROCSET need to be not-connected.
8 PHASE
HS Driver return path, current-reading and adaptive-dead-time monitor. monitor when HS mosfet is OFF .
2.2 Thermal data
Table 3. Thermal data
3 Electrical specifications
3.1 Absolute maximum ratings
Table 4. Absolute maximum ratings
- Measured with the component mounted on a 2S2P board in free air (6.7cm x 6.7cm, 35 µm (P) and 17.5µm
- ESD immunity for FB pin is guarant eed up to ±1000V (Human Body Model).
3.2 Electrical characteristics
Table 5. Electrical characteristics (VCC = 12V; TA = -20°C to +85°C, unless otherwise specified).
- Guaranteed by design, not subject to test.
Table 5. Electrical characteristics (continued) (VCC = 12V; TA = -20°C to +85°C, unless otherwise specified).
4 Device description
L6727 is a single-phase PWM controller with embedded high-current drivers that provides complete control logic and protections to realize in an easy and simple way a general DC- DC step-down converter. Designed to drive N-channel MOSFETs in a synchronous buck topology, with its high level of integration this 8-pin device allows reducing cost and size of the power supply solution. L6727 is designed to operate from a 5V or 12V supply bus. Thanks to the high precision 0.8V internal reference, the output voltage can be precisely regulated to as low as 0.8V with ±1% accuracy over line and temperature variations (between 0°C and +70°C). The switching frequency is internally set to 300kHz. This device provides a simple control loop with a voltage-mode error-amplifier. The error- amplifier features a 15MHz gain-bandwidth product and 8V/µs slew rate, allowing high regulator bandwidth for fast transient response. To avoid load damages, L6727 provides over current protection as well as over voltage, under voltage and feedback disconnection protection. When the device is supplied from 5V, over current trip threshold is programmable by a simple resistor. Output current is monitored across Low-Side MOSFET R dsON, saving the use of expensive and space-consuming sense resistor. Output voltage and feedback disconnection are monitored through FB pin. L6727 implements soft-start increasing the internal reference from 0V to 0.8V in 5.1ms (typ) in closed loop regulation. Low-Side-Less feature allows the device to perform soft-start over pre-biased output avoiding high current return through the output inductor and dangerous negative spike at the load side.
5 Driver section
The integrated high-current drivers allow using different types of power MOSFET (also multiple MOSFETs to reduce the equivalent RdsON), maintaining fast switching transition. The driver for the high-side MOSFET uses BOOT pin for supply and PHASE pin for return. The driver for low-side MOSFET uses the VCC pin for supply and GND pin for return. The controller embodies an anti-shoot-through and adaptive dead-time control to minimize low side body diode conduction time, maintaining good efficiency while saving the use of Schottky diode:
- to check high-side MOSFET turn off, PHASE pin is sensed. When the voltage at PHASE pin drops down, the low-side MOSFET gate drive is suddenly applied;
- to check low-side MOSFET turn off, LGATE pin is sensed. When the voltage at LGATE has fallen, the high-side MOSFET gate drive is suddenly applied. If the current flowing in the inductor is negative, voltage on PHASE pin will never drop. To allow the low-side MOSFET to turn-on even in this case, a watchdog controller is enabled: if the source of the high-side MOSFET doesn't drop, the low side MOSFET is switched on so allowing the negative current of the inductor to recirculate. This mechanism allows the system to regulate even if the current is negative. Power conversion input is flexible: 5V, 12V bus or any bus that allows the conversion (See maximum duty cycle limitation and recommended operating conditions, in Table 5) can be chosen freely.
5.1 Power dissipation
L6727 embeds high current MOSFET drivers for both high side and low side MOSFETs: it is then important to consider the power that the device is going to dissipate in driving them in order to avoid overcoming the maximum junction operative temperature. Two main terms contribute in the device power dissipation: bias power and drivers' power.
- Device Bias Power (PDC) depends on the static consumption of the device through the supply pins and it is simply quantifiable as follow (assuming to supply HS and LS drivers with the same VCC of the device):
- Drivers power is the power needed by the driver to continuously switch on and off the external MOSFETs; it is a function of the switching frequency and total gate charge of the selected MOSFETs. It can be quantified considering that the total power P SW dissipated to switch the MOSFETs (easy calculable) is dissipated by three main factors: external gate resistance (when present), intrinsic MOSFET resistance and intrinsic driver resistance. This last term is the important one to be determined to calculate the device power dissipation. The total power dissipated to switch the MOSFETs results: where V BOOT - VPHASE is the voltage across the bootstrap capacitor. External gate resistors helps the device to dissipate the switching power since the same power PSW will be shared between the internal driver impedance and the external resistor resulting in a general cooling of the device. PDC VCC ICC IBOOT+()⋅= PSW FSW QgHS VBOOT VPHASE–() QgLS VCC⋅+⋅[]⋅=
6 Soft Start and Disable
charging the output capacitors to the final regulation voltage. and over current threshold setting phase has been completed.
6.1 Low-Side-Less Start up (LSLess)
voltage that can happen if starting over a pre-biased output. will ramp up from there, without any drop or current return. the output to the final regulation value. view: protections by-pass LSLESS, turning ON the LS mosfet in case of need. Figure 4. LSLess Startup (left) vs. Non-LSLess Startup (right)
6.2 Enable / Disable
enables again performing a new SS. current for about 15µs. Once disabled, COMP output current drops to 20µA. Figure 5. Start Up sequence; V
L6727 Over current protection
7 Over current protection
The over current feature protects the converter from a shorted output or overload, by sensing the output current information across the Low Side MOSFET drain-source on- resistance, RdsON. This method reduces cost and enhances converter efficiency by avoiding the use of expensive and space-consuming sense resistors. The low side RdsON current sense is implemented by comparing the voltage at the PHASE node when LS MOSFET is turned on with the programmed OCP threshold voltage, internally held. If the monitored voltage drop (GND to PHASE) exceeds this threshold, an Over Current Event is detected. If two Over Current Events are detected in two consecutive switching cycles, the protection will be triggered and the device will turn off both LS and HS MOSFETs for 2048 clock cycles (plus internal SS remaining time, if triggered during a SS phase); then it will begin a new Soft Start. If the over current condition is not removed, the continuous fault will cause L6727 to go into a hiccup mode with a typical period of 13.6ms (Figure 5), guaranteeing safe load protection and very low power dissipation.
7.1 Over current threshold setting
When supplied with VCC = 5V, L6727 allows to easily program an Over Current Threshold ranging from 50mV to 500mV, simply by adding a resistor (ROCSET) between COMP and VCC. During a short period of time (5.5ms - 6.5ms) following the first enable (given VCC over UVLO threshold), an internal 60µA current (IOCSET) is sunk from COMP pin, determining a voltage drop across ROCSET. This voltage drop, differentially sensed between VCC and COMP , divided by a factor 3, will be sampled and internally held by the device as Over Current Threshold until next VCC cycling. Differential sensing versus VCC allows OCSET procedure to be fully independent from VIN rail. The OC setting procedure overall time length ranges from 5.5ms to 6.5ms, proportionally to the threshold being set. Connecting an R OCSET resistor between COMP and VCC, the programmed threshold will be: ROCSET values range from 2.5kΩ to 25kΩ. If the voltage drop across ROCSET is too low, the system will be very sensitive to start-up inrush current and noise. This can result in a continuous OCP triggering and hiccup mode. In this case, consider to increase R OCSET value. In case ROCSET is not connected (and VCC = 5V), the device will set the maximum threshold. If the device is supplied with a VCC higher than 7V, ROCSET must be not connected. In this case, as soon as VCC rises over VCC_OC (8V typ.), L6727 switches OC threshold to 400mV (internally fixed value). See Figure 5 for OC threshold setting and soft start oscilloscope sample waveforms. IOCth 3--- IOCSET ROCSET⋅ RdsON
Output voltage monitor and protections L6727
8 Output voltage monitor and protections
L6727 monitors the voltage at FB pin and compares it to internal reference voltage in order to provide Under Voltage and Over Voltage protections.
8.1 Under voltage protection
If the voltage at FB pin drops below UV threshold (0.6V typ), the device turns off both HS and LS MOSFETs, waits for 2048 clock cycles and then performs a new Soft Start. If under voltage condition is not removed, the device enters a hiccup mode with a typical period of 13.6ms. UVP is active from the end of soft start.
8.2 Over voltage protection
If the voltage at FB pin rises over OV threshold (1V typ), over voltage protection turns off HS MOSFET and turns on LS MOSFET overriding PWM logic as long as over voltage is detected. OVP is always active with top priority as soon as over current threshold setting phase has been completed.
8.3 Feedback discon nection protection
In order to provide load protection even if FB pin is not connected, a 100nA bias current is always sourced from this pin. If FB pin is not connected, this current will permanently pull up FB over OVP threshold: thus LS will be latched on preventing output voltage from rising out of control.
8.4 Under voltage lock out
In order to avoid anomalous behaviors of the device when the supply voltage is too low to support its internal rails, UVLO is provided: the device will start up when VCC reaches UVLO upper threshold and will shutdown when VCC drops below UVLO lower threshold. The 4.1V maximum UVLO upper threshold allows L6727 to be supplied from 5V and 12V busses in or-ing diode configuration.
9 Application details
9.1 Output voltage selection
(excluding output resistor divider tolerance, when present).
9.2 Compensation network
offset resistor between FB node and GND can be neglected in control loop calculation). amplitude. This waveform is filtered by the output filter. function ideally equal to -ZF/ZFB. Figure 6. PWM control loop
high bandwidth and good phase margin. has to cross 0dB axis with -20dB/decade slope. As an example, Figure 7 shows an asymptotic bode plot of a type III compensation. Figure 7. Example of type III compensation.
- Open loop converter singularities:
- Compensation Network singularities frequencies: Gain [dB] Log (Freq)0dB open loop EA gain closed loop gain compensation gain open loop converter gain FLC FESR FZ1 FZ2 FP1 FP2 20log (RF/RFB) 20log (VIN/∆VOSC) F0dB FLC 2π LC OUT⋅ FESR FZ1 FZ2 FP1 2π RF CF CP⋅ ⎛⎞⋅⋅ FP2
To place the poles and zeroes of the compensation network, the following suggestions may be followed: a) Set the gain R F/RFB in order to obtain the desired closed loop regulator bandwidth according to the approximated formula (suggested values for RFB range from 2kΩ to 5kΩ): b) Place F Z1 below FLC (typically 0.5*FLC): c) Place F P1 at FESR: d) Place F Z2 at FLC and FP2 at half of the switching frequency: e) Check that compensation network gain is lower than open loop EA gain; f) Estimate phase margin obtained (it should be greater than 45°) and repeat, modifying parameters, if necessary.
9.3 Layout guidelines
L6727 provides control functions and high current integrated drivers to implement high- current step-down DC-DC converters. In this kind of application, a good layout is very important. The first priority when placing components for these applications has to be reserved to the power section, minimizing the length of each connection and loop as much as possible. To minimize noise and voltage spikes (EMI and losses) power connections (highlighted in Figure 8) must be part of a power plane and anyway realized by wide and thick copper traces: loop must be anyway minimized. The critical components, i.e. the power MOSFETs, must be close one to the other. The use of multi-layer printed circuit board is recommended. The input capacitance (C IN), or at least a portion of the total capacitance needed, has to be placed close to the power section in order to eliminate the stray inductance generated by the copper traces. Low ESR and ESL capacitors are preferred, MLCC are suggested to be connected near the HS drain. Use proper VIAs number when power traces have to move between different planes on the PCB in order to reduce both parasitic resistance and inductance. Moreover, reproducing the RF RFB F0dB FLC VIN CF CP CF RS RFB FSW 2F⋅ LC CS
9.4 Embedding L6727-based VRs
When embedding the VR into the application, additional care must be taken since the whole VR is a switching DC/DC regulator and the most common system in which it has to work is a digital system such as MB or similar. In fact, latest MBs have become faster and more powerful: high speed data busses are more and more common and switching-induced noise produced by the VR can affect data integrity if additional layout guidelines are not followed. Few easy points must be considered mainly when routing traces in which switching high currents flow (switching high currents cause voltage spikes across the stray inductance of the traces causing noise that can affect the near traces): When reproducing high current path on internal layers, keep all layers the same size in order to avoid "surrounding" effects that increase noise coupling. Keep safe guard distance between high current switching VR traces and data busses, especially if high-speed data busses, to minimize noise coupling. Keep safe guard distance or filter properly when routing bias traces for I/O sub-systems that must walk near the VR. Possible causes of noise can be located in the PHASE connections, MOSFETs gate drive and Input voltage path (from input bulk capacitors and HS drain). Also GND connection must be considered if not insisting on a power ground plane. These connections must be carefully kept far away from noise-sensitive data busses. Since the generated noise is mainly due to the switching activity of the VR, noise emissions depend on how fast the current switches. To reduce noise emission levels, it is also possible, in addition to the previous guidelines, to reduce the current slope and thus to increase the switching times: this will cause, as a consequence of the higher switching time, an increase in switching losses that must be considered in the thermal design of the system.
conditions are also marked on the inner box label. ECOPACK is an ST trademark. Table 6. SO-8 Mechanical data
- D and F does not include mold flash or protrusions . Mold flash or potrusions shall not exceed 0.15mm
Figure 10. Package dimensions
Table 7. Revision history 04-Dec-2006 1 Initial release.