L6726A STMICROELECTRONICS | Alldatasheet
Document overview
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- PDF pages: 24
Technical content
Datasheet sections
- 1 Typical application cir cuit and block diagram
- 1.1 Application circuit
- 1.2 Block diagram
- 2 Pins description and connection diagrams
- 2.1 Pin descriptions
- 2.2 Thermal data
- 3 Electrical specifications
- 3.1 Absolute maximum ratings
- 3.2 Electrical characteristics
- 4 Device description
- 5 Driver section
- 5.1 Power dissipation
- 6 Soft start and disable
- 6.1 Low-Side-Less start up (LSLess)
- 6.2 Enable / Disable
- 7 Protections
- 7.1 Over current protection
- 7.1.1 Over current threshold setting
- 7.2 Feedback disconnection protection
- 7.3 Under Voltage Lock Out
Single phase PWM controller Feature ■ Flexible power supply from 5V to 12V ■ Power conversion input as low as 1.5V ■ 1% output voltage accuracy ■ High-current integrated drivers ■ Adjustable output voltage ■ 0.8V internal reference ■ Sensorless and programmable OCP across Low-side RdsON ■ Oscillator internally fixed at 270kHz ■ Programmable soft-start ■ LS-LESS start up ■ Disable function ■ FB disconnection protection ■ SO-8 package
Applications
■ Subsystem power supply (MCH, IOCH, PCI...) ■ Memory and termination Supply ■ CPU & DSP power supply ■ Distributed power supply ■ General DC / DC converters Order codes
Description
L6726A is a single-phase step-down controller with integrated high-current drivers that provides complete control logic, protections and reference voltage to realize in an easy and simple way general DC-DC converters by using a compact SO-8 package. Device flexibility allows managing conversions with power input V IN as low as 1.5V and device supply voltage ranging from 5V to 12V. L6726A provides simple control loop with trans- conductance error amplifier. The integrated 0.8V reference allows regulating output voltage with ±1% accuracy over line and temperature variations. Oscillator is internally fixed to 270kHz. L6726A provides programmable over current protection. Current information is monitored across the Low-Side mosfet R dsON saving the use of expensive and space-consuming sense resistors. FB disconnection protection prevents excessive and dangerous output voltages in case of floating FB pin. SO-8 Part Number Package Packing L6726A SO-8 Tube L6726ATR SO-8 Tape & Reel
1 Typical application circuit and block diagram
1.1 Application circuit
Figure 1. Typical application circuit
1.2 Block diagram
Figure 2. Block diagram
2 Pins description and connection diagrams
Figure 3. Pins connection (Top View)
2.1 Pin descriptions
Table 1. Pins descriptions and provide necessary bootstrap diode from VCC. 2 UGATE HS Driver Output. Connect to HS mosfet gate. 3G N D All internal references, logic and drivers are connected to this pin. Connect to the PCB ground plane.
4 LGATE / OC
LGATE. LS Driver Output. Connect to LS mosfet gate. VCC rising over UVLO threshold, a 10µA current is sourced from this pin. 5V C C Device and LS Driver power supply. Operative range from 4.1V to 13.2V. Filter with at least 1µF MLCC to GND. Error Amplifier Inverting Input.
7 COMP / DIS
compensate the device control loop in conjunction to the FB pin. compensation capacitors also act to program the SS time. DIS. The device can be disabled by pulling this pin lower than 0.4V (min). Setting free the pin, the device enables again.
8 PHASE
HS Driver return path, current-reading and adaptive-dead-time monitor. monitor when HS mosfet is OFF .
2.2 Thermal data
Table 2. Thermal data
- Measured with the component mounted on a 2S2P board in free air (6.7mm x 6.7mm, 35 µm (P) and
17.5µm (S) copper thickness).
3 Electrical specifications
3.1 Absolute maximum ratings
Table 3. Absolute maximum ratings
3.2 Electrical characteristics
Table 4. Electrical characteristics (VCC = 12V; TA = 25° C unless otherwise specified).
IOCSET OCSET current source Sourced from LGATE pin.
- Guaranteed by design, not subject to test.
Table 4. Electrical characteristics (continued) (VCC = 12V; TA = 25° C unless otherwise specified).
4 Device description
L6726A is a single-phase PWM controller with embedded high-current drivers that provides complete control logic and protections to realize in an easy and simple way a general DC- DC step-down converter. Designed to drive N-channel MOSFETs in a synchronous buck topology, with its high level of integration this 8-pin device allows reducing cost and size of the power supply solution. L6726A is designed to operate from a 5V or 12V supply bus. Thanks to the high precision 0.8V internal reference, the output voltage can be precisely regulated to as low as 0.8V with ±1% accuracy over line and temperature variations. The switching frequency is internally set to 270kHz. This device provides a simple control loop with externally compensated transconductance error-amplifier and programmable soft start. Low-Side-Less feature allows the device to perform soft-start over pre-charged output avoiding negative spikes at the load side. In order to avoid load damages, L6726A provides programmable threshold over current protection. Output current is monitored across Low-Side MOSFET R dsON, saving the use of expensive and space-consuming sense resistor. L6726A also features FB disconnection protection, preventing dangerous uncontrolled output voltages in case of floating FB pin.
5 Driver section
The integrated high-current drivers allow using different types of power MOSFET (also multiple MOSFETs to reduce the equivalent RdsON), maintaining fast switching transition. The driver for high-side MOSFET uses BOOT pin for supply and PHASE pin for return. The driver for low-side MOSFET uses the VCC pin for supply and GND pin for return. The controller embodies an anti-shoot-through and adaptive dead-time control to minimize low side body diode conduction time, maintaining good efficiency while saving the use of Schottky diode:
- to check for high-side MOSFET turn off, PHASE pin is sensed. When the voltage at PHASE pin drops down, the low-side MOSFET gate drive is suddenly applied;
- to check for low-side MOSFET turn off, LGATE pin is sensed. When the voltage at LGATE has fallen, the high-side MOSFET gate drive is suddenly applied. If the current flowing in the inductor is negative, voltage on PHASE pin will never drop. To allow the low-side MOSFET to turn-on even in this case, a watchdog controller is enabled: if the source of the high-side MOSFET doesn't drop, the low side MOSFET is switched on so allowing the negative current of the inductor to recirculate. This mechanism allows the system to regulate even if the current is negative. Power conversion input is flexible: 5V, 12V bus or any bus that allows the conversion (See maximum duty cycle limitation and recommended operating conditions) can be chosen freely.
5.1 Power dissipation
L6726A embeds high current MOSFET drivers for both high side and low side MOSFETs: it is then important to consider the power that the device is going to dissipate in driving them in order to avoid overcoming the maximum junction operative temperature. Two main terms contribute in the device power dissipation: bias power and drivers power.
- Device Bias Power (PDC) depends on the static consumption of the device through the supply pins and it is simply quantifiable as follow (assuming to supply HS and LS drivers with the same VCC of the device):
- Drivers power is the power needed by the driver to continuously switch on and off the external MOSFETs; it is a function of the switching frequency, the voltage supply of the driver and total gate charge of the selected MOSFETs. It can be quantified considering that the total power P SW dissipated to switch the MOSFETs (easy calculable) is dissipated by three main factors: external gate resistance (when present), intrinsic MOSFET resistance and intrinsic driver resistance. This last term is the important one to be determined to calculate the device power dissipation. The total power dissipated to switch the MOSFETs results: where V BOOT - VPHASE is the voltage across the bootstrap capacitor. PDC VCC ICC IBOOT+()⋅= PSW FSW QgHS VBOOT VPHASE–() QgLS VCC⋅+⋅[]⋅=
resulting in a general cooling of the device. Figure 4. Soft start (left) and Disable (right)
6 Soft start and disable
increasing width that charge the output capacitors. start sequence and will shut down the PWM logic and both the high side and low side gates. This condition is latched, cycle VCC to recover. threshold and over current threshold setting phase has been completed.
6.1 Low-Side-Less start up (LSLess)
Figure 5. LSLess startup (left) vs. Non-LSLess startup (right)
6.2 Enable / Disable
pin. Setting free the pin, the device enables again performing a new SS.
7 Protections
7.1 Over current protection
The over current feature protects the converter from a shorted output or overload, by sensing the output current information across the Low Side MOSFET drain-source on- resistance, R dsON. This method reduces cost and enhances converter efficiency by avoiding the use of expensive and space-consuming sense resistors. The low side RdsON current sense is implemented by comparing the voltage at the PHASE node when LS MOSFET is turned on with the programmed OCP threshold voltage, internally held. If the monitored voltage drop (GND to PHASE) exceeds this threshold, an Over Current Event is detected. If two Over Current Events are detected in two consecutive switching cycles, the protection will be triggered and the device will turn off both LS and HS MOSFETs in a latched condition. To recover from Over Current Protection triggered, VCC power supply must be cycled.
7.1.1 Over current threshold setting
L6726A allows to easily program an Over Current Threshold ranging from 50mV to 550mV, simply by adding a resistor (ROCSET) between LGATE and GND. During a short period of time (5.5ms - 6.5ms) following VCC rising over UVLO threshold, an internal 10µA current (IOCSET) is sourced from LGATE pin, determining a voltage drop across ROCSET. This voltage drop will be sampled and internally held by the device as Over Current Threshold. The OC setting procedure overall time length ranges from 5.5ms to 6.5ms, proportionally to the threshold being set. Connecting a R OCSET resistor between LGATE and GND, the programmed threshold will be: ROCSET values range from 5kΩ to 55kΩ. If the voltage drop across ROCSET is too low, the system will be very sensitive to start-up inrush current and noise. This can result in undesired OCP triggering. In this case, consider increasing R OCSET value. In case ROCSET is not connected, the device switches the OCP threshold to a 375mV default value: an internal safety clamp on LGATE is triggered as soon as LGATE voltage reaches 700mV (typ), enabling the 375mV default threshold and suddenly ending OC setting phase. See Figure 6 for OC threshold setting procedure timings picture and oscilloscope sample waveforms.
7.2 Feedback discon nection protection
In order to provide load protection even if FB pin is not connected, a 100nA bias current is always sourced from this pin. If FB pin is not connected, bias current will permanently pull up FB: this forces COMP pin low, avoiding output voltage rising to dangerous levels. IOCth IOCSET ROCSET⋅ RdsON
Figure 6. OC threshold setting procedure timings (top) and waveforms (bottom)
7.3 Under Voltage Lock Out
UVLO upper threshold and will shutdown when VCC drops below UVLO lower threshold. busses in or-ing diode configuration. Figure 7. OCP trip, default threshold, LS: STD38NH02L (left). UVLO turn off (right)
8 Application details
8.1 Output voltage selection
divider tolerance, when present).
8.2 Compensation network
compared to oscillator saw-tooth waveform to provide PWM signal to the driver section. filtered by the output filter. Figure 8. PWM control loop
voltage VIN divided by the peak-to-peak oscillator voltage ∆VOSC. VOUT is scaled and transferred to FB node by the output resistor divider. function ideally equal to -gm·ZF. high bandwidth and good phase margin. cross 0dB axis with -20dB/decade slope. As an example, Figure 9 shows an asymptotic bode plot of a type II compensation. Figure 9. Example of type II compensation.
- Open loop converter singularities:
- Compensation Network singularities frequencies: Gain [dB] Log (Freq)0dB OTA open loop gain closed loop gain compensation gain converter open loop gain FLC FESR FZ FP 20log (gm ·RF) 20log [VIN/∆VOSC·ROS/(RFB+ROS)] F0dB FLC 2π LC OUT⋅ FESR FZ FP 2π RF CF CP⋅ ⎛⎞⋅⋅
Type II compensation relies on the zero introduced by the output capacitors bank to achieve stability. Thus, a needed condition to successfully apply type II compensation is (usually true when output capacitor is based on electrolytic, aluminium electrolytic or tantalum capacitor). To define compensation network components values, the below suggestions may be followed: a) Set the output resistor divider in order to obtain the desired output voltage: Usual values of R FB and ROS ranges from some hundreds of Ω to some kΩ (consider trade-off between power dissipation on output resistor divider and offset introduced by FB bias current). If the desired output voltage is equal to internal reference, R OS has to be NC and FB pin can be directly connected to VOUT. b) Set R F in order to obtain the desired closed loop regulator bandwidth according to the approximated formula: If VOUT = VREF, just consider (RFB+ROS)/ROS factor equal to 1. c) Place F Z below FLC (typically 0.2·FLC): d) Place F P at 0.5·FSW: e) Check that compensation network gain is lower than open loop transconductance EA gain. f) Estimate phase margin obtained (it should be greater than 45°) and repeat, modifying parameters, if necessary.
8.3 Soft Start time calculation
To calculate SS time (tSS), the following approximated equation can be used (CP<<CF): FESR F0dB< RFB ROS VREF RF F0dB FESR⋅ FLC VIN ROS CF CP CF tSS CF VOUT VIN ISS
8.4 Layout guidelines
must be close one to the other. The use of multi-layer printed circuit board is recommended. Figure 10. Power Connections (heavy lines) connected near the HS drain. associated to that connection.
Application details L6726A
8.5 Embedding L6726A-based VRs…
When embedding the VR into the application, additional care must be taken since the whole VR is a switching DC/DC regulator and the most common system in which it has to work is a digital system such as MB or similar. In fact, latest MBs have become faster and more powerful: high speed data busses are more and more common and switching-induced noise produced by the VR can affect data integrity if additional layout guidelines are not followed. Few easy points must be considered mainly when routing traces in which switching high currents flow (switching high currents cause voltage spikes across the stray inductance of the traces causing noise that can affect the near traces): When reproducing high current path on internal layers, keep all layers the same size in order to avoid "surrounding" effects that increase noise coupling. Keep safe guard distance between high current switching VR traces and data busses, especially if high-speed data busses, to minimize noise coupling. Keep safe guard distance or filter properly when routing bias traces for I/O sub-systems that must walk near the VR. Possible causes of noise can be located in the PHASE connections, MOSFETs gate drive and Input voltage path (from input bulk capacitors and HS drain). Also GND connection must be considered if not insisting on a power ground plane. These connections must be carefully kept far away from noise-sensitive data busses. Since the generated noise is mainly due to the switching activity of the VR, noise emissions depend on how fast the current switches. To reduce noise emission levels, it is also possible, in addition to the previous guidelines, to reduce the current slope and thus to increase the switching times: this will cause, as a consequence of the higher switching time, an increase in switching losses that must be considered in the thermal design of the system.
9 Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com
Table 5. SO-8 Mechanical data
- D and F does not include mold flash or protrusions . Mold flash or potrusions shall not exceed 0.15mm
Figure 12. Package dimensions
Table 6. Revision history 16-Oct-2006 1.0 Initial release.