L6712AQTR

L6712 STMICROELECTRONICS | Alldatasheet

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■ 2 PHASE OPERATION WITH SYNCHRONOUS RECTIFIER CONTROL ■ ULTRA FAST LOAD TRANSIENT RESPONSE ■ INTEGRATED HIGH CURRENT GATE DRIVERS: UP TO 2A GATE CURRENT ■ 3 BIT PROGRAMMABLE OUTPUT FROM 0.900V TO 3.300V OR WITH EXTERNAL REF. ■ ±0.9% OUTPUT VOLTAGE ACCURACY ■ 3mA CAPABLE AVAILABLE REFERENCE ■ INTEGRATED PROGRAMMABLE REMOTE SENSE AMPLIFIER ■ PROGRAMMABLE DROOP EFFECT ■ 10% ACTIVE CURRENT SHARING ACCURACY ■ DIGITAL 2048 STEP SOFT-START ■ CROWBAR LATCHED OVERVOLTAGE PROT. ■ NON-LATCHED UNDERVOLTAGE PROT. ■ OVERCURRENT PROTECTION REALIZED USING THE LOWER MOSFET'S RdsON OR A SENSE RESISTOR ■ OSCILLATOR EXTERNALLY ADJUSTABLE AND INTERNALLY FIXED AT 150kHZ ■ POWER GOOD OUTPUT AND INHIBIT FUNCTION ■ PACKAGES: SO-28 & VFQFPN-36

APPLICATIONS

■ HIGH CURRENT DC/DC CONVERTERS ■ DISTRIBUTED POWER SUPPLY

DESCRIPTION

The device implements a dual-phase step-down con- troller with a 180 phase-shift between each phase optimized for high current DC/DC applications. Output voltage can be programmed through the in- tegrated DAC from 0.900V to 3.300V; program- ming the "111" code, an external reference from 0.800V to 3.300V is used for the regulation. Programmable Remote Sense Amplifier avoids use of external resistor divider and recovers loss- es along distribution line. The device assures a fast protection against load over current and Over / Under voltage.An internal crowbar is provided turning on the low side mosfet if Over-voltage is detected. Output current is limited working in Constant Cur- rent mode: when Under Voltage is detected, the device resets, restarting operation. SO28 VFQFPN-36 (6x6x1.0) ORDERING NUMBERS: Package Tube Tape & Reel SO L6712D, L6712AD L6712DTR, L6712ADTR VFQFPN L6712Q, L6712AQ L6712QTR, L6712AQTR TWO-PHASE INTERLEAVED DC/DC CONTROLLER BLOCK DIAGRAM CURRENT READING IDROOP TOTAL CURRENT CURRENT AVG CH1 OCP DAC LOGIC PWM ADAPTIVE ANTI CROSS CONDUCTION CH1 OCP

2 PHASE

REF_IN/OUT PGOOD DROOP BAND-GAP REFERENCE DIGITAL SOFT-START CH2 OCP VPROG IFB _START CURRENT READING IDROOP TOTAL CURRENT CURRENT AVG CH1 OCP DAC LOGIC PWM ADAPTIVE ANTI CROSS CONDUCTION CH1 OCP REF_IN/OUT PGOOD DROOP BAND-GAP REFERENCE DIGITAL SOFT-START CH2 OCP VPROG IFB _START

PIN CONNECTION (Top view) Symbol Parameter Value Unit VCC, VCCDR To PGN D 15 V VBOOT-VPHASE Boot Voltage 15 V VUGATE1-VPHASE1 VUGATE2-VPHASE2 15 V LGA TE1, PHASE1, LGA TE2, PHASE2 to PGND -0.3 to Vcc+0.3 V VID0 to VID2 -0.3 to 5 V All other pins to PGND -0.3 to 7 V V PHASEx Sustainable Peak Voltage. T<20ns @ 600kHz 26 V UGA TEX Pins Maximum Withstanding Voltage Range Test Condition: CDF-AEC-Q100-002”Human Body Model” Acceptance Criteria: “Normal Performance” ±1500 V OTHER PINS ±2000 V Symbol Parameter SO28 VFQFPN36 Unit Rthj-amb Thermal Resistance Junction to Ambient 4 layer PCB (2s2p) 60 30 °C/W Tmax Maximum junction temperature 150 150 °C Tstg Storage temperature range -40 to 150 -40 to 150 °C Tj Junction Temperature Range -40 to 125 -40 to 125 °C PMAX Max power dissipation at Tamb = 25°C 23 . 5 W 1 2 3 4 5 6 7 8 9 27 26 25 24 23 22 21 20 19 N.C. FBG FBR VID0 VID1 VID2 PGOOD BOOT2 DROOP FB COMP SGND SGND VCC N.C. BOOT1 N.C N.C. REF_IN/OUT VSEN ISEN1 PGNDS1 PGNDS2 ISEN2 N.C. OSC UGATE1 PHASE1 VCCDR LGATE1 PGND PGND LGATE2 PHASE2 UGATE2 1 2 3 4 5 6 7 8 9 27 26 25 24 23 22 21 20 19 N.C. N.C. REF_IN/OUT VSEN ISEN1 PGNDS1 PGNDS2 ISEN2 N.C. OSC PHASE1 VCCDR LGATE1 PGND PGND LGATE2 PHASE2 SO28 VFQFPN-36 Corner Pin internally connected to the Exposed Pad. LGATE1 VCCDR PHASE1 FB BOOT1 UGATE1 DROOP VCC SGND COMP ISEN1 PGNDS1 REF_IN/OUT VSEN VID1 VID0 FBR VID2 BOOT2 PGOOD UGATE2 PHASE2 LGATE2 PGND OSC/INH/FAULT ISEN2 PGNDS2 FBG

(VCC = 12V±10%, TJ = 0°C to 70°C unless otherwise specified) Symbol Parameter Test Condition Min. Typ. Max. Unit Vcc SUPPLY CURRENT ICC VCC supply current HGATEx and LGA TEx open VCCDR=BOOTx=12V 7.5 10 12.5 mA ICCDR VCCDR supply current LGA TEx open; VCCDR=12V 1.5 3 4 mA IBOOTx Boot supply current HGATEx open; PHASEx to PGND; VCC=BOOTx=12V 0 . 511 . 5 m A POWER-ON Turn-On VCC threshold VCC Rising; VCCDR=5V 8.2 9.2 10.2 V Turn-Off VCC threshold VCC Falling; VCCDR=5V 6.5 7.5 8.5 V Turn-On VCCDR Threshold VCCDR Rising VCC=12V 4.2 4.4 4.6 V Turn-Off VCCDR Threshold VCCDR Falling VCC=12V 4.0 4.2 4.4 V OSCILLATOR AND INHIBIT f OSC Initial Accuracy OSC = OPEN OSC = OPEN; Tj=0°C to 125°C 135 127 150 165 178 kHz kHz INH Inhibit threshold I SINK=5mA 0.5 V dMAX Maximum duty cycle L6712, OSC = OPEN: IDROOP=0 OSC = OPEN; IDROOP=70µA L6712A, OSC = OPEN 85 90 % ∆Vosc Ramp Amplitude 3 V FAULT Voltage at pin OSC OVP Active 4.75 5.0 5.25 V REFERENCE AND DAC VOUT (1) Output Voltage Accuracy VIDx See Table 1, VID ≠ “11x“ -0.9 - 0.9 % REF_IN/OUT Reference Accuracy VIDx See Table 1, VID ≠ “111” V OUT -5 V OUT VOUT+5 mV Current Capability 3 mA Load Regulation I REF = from 0 to 3mA 5.0 mV VPROG / REF_IN/ OUT Accuracy with external reference VID=“111”; REF_IN/OUT = 0.8V to 3.3V -2.0 2.0 % REF_IN/OUT Input impedance 400 kΩ IVID VID pull-up Current VIDx =SGND 5 µA VVID VID pull-up Voltage VIDx = OPEN 3 V VIDIL VID Input Levels Input Low 0.4 V VIDIH Input High 1.0 V ERROR AMPLIFIER VOS_EA Offset FB = COMP -5 5 mV DC Gain 80 dB SR Slew-Rate COMP=10pF 15 V/µs IFB_START Start-up Current FB=SGND; During Soft Start… 65 µA DIFFERENTIAL AMPLIFIER (REMOTE BUFFER) VOS_RA Offset VSEN = FBG -8 8 mV

Note: 1. Output voltage is specified including Error Amplifier Offset in the trimming chain. Remote Amplifier is not included. Table 1. Voltage Identification (VID) Codes.

N. (*) Name DescriptionSO VFQFPN 1 33 LGA TE1 Channel 1 LS driver output. A little series resistor helps in reducing device-dissipated power. 2 34 VCCDR LS drivers supply: it can be varied from 5V to 12V buses. Filter locally with at least 1µF ceramic cap vs. PGND. 3 35 PHASE1 Channel 1 HS driver return path. It must be connected to the HS1 mosfet source and provides the return path for the HS driver of channel 1. 4 36 UGATE1 Channel 1 HS driver output. A little series resistor helps in reducing device-dissipated power. 5 2 BOOT1 Channel 1 HS driver supply. This pin supplies the relative high side driver. Connect through a capacitor (100nF typ.) to the PHASE1 pin and through a diode to VCC (cathode vs. boot). 6 4 VCC Device supply voltage. The operative supply voltage is 12V ±10%. Filter with 1µF (Typ.) capacitor vs. GND. 7 5,6 SGND All the internal references are referred to this pin. Connect it to the PCB signal ground. 8 7 COMP This pin is connected to the error amplifier output and is used to compensate the control feedback loop. 9 8 FB This pin is connected to the error amplifier inverting input and is used to compensate the control feedback loop. 10 9 DROOP A current proportional to the sum of the current sensed in both channel is sourced from this pin (50µA at full load, 70µA at the Constant Current threshold). Short to FB to implement the Droop effect: the resistor connected between FB and VSEN (or the regulated output) allows programming the droop effect. Otherwise, connect to GND directly or through a resistor (43k Ω max) and filter with 1nF capacitor. In this last case, current information can be used for other purposes. 11 11 REF_IN / OUT Reference input/output. Filter vs. GND with 1nF ceramic capacitor (a total of 100nF capacitor is allowed). It reproduces the reference used for the regulation following VID code: when VID=111, the reference for the regulation must be connected on this pin. References ranging from 0.800V up to 3.300V can be accepted. 12 12 VSEN Connected to the output voltage it is able to manage Over & Under-voltage conditions and the PGOOD signal. It is internally connected with the output of the Remote Sense Amplifier for Remote Sense of the regulated voltage. Connecting 1nF capacitor max vs. GND can help in reducing noise injection at this pin. If no Remote Sense is implemented, connect it directly to the regulated voltage in order to manage OVP , UVP and PGOOD. 13 13 ISEN1 Channel 1 current sense pin. The output current may be sensed across a sense resistor or across the low-side mosfet R dsON. This pin has to be connected to the low-side mosfet drain or to the sense resistor through a resistor Rg. The net connecting the pin to the sense point must be routed as close as possible to the PGNDS net in order to couple in common mode any picked-up noise. 14 14 PGNDS1 Channel 1 Power Ground sense pin. The net connecting the pin to the sense point must be routed as close as possible to the ISEN1 net in order to couple in common mode any picked-up noise. 15 15 PGNDS2 Channel 2 Power Ground sense pin. The net connecting the pin to the sense point must be routed as close as possible to the ISEN2 net in order to couple in common mode any picked-up noise.

(*) Pin not reported in QFN column have to be considered as Not Connected, not internally bonded. 16 16 ISEN2 Channel 2 current sense pin. The output current may be sensed across a sense resistor or across the low-side mosfet RdsON. This pin has to be connected to the low-side mosfet drain or to the sense resistor through a resistor Rg. The net connecting the pin to the sense point must be routed as close as possible to the PGNDS net in order to couple in common mode any picked-up noise. 17 18 OSC/INH FAULT Oscillator pin. It allows programming the switching frequency of each channel: the equivalent switching frequency at the load side results in being doubled. Internally fixed at 1.24V, the frequency is varied proportionally to the current sunk (forced) from (into) the pin with an internal gain of 6kHz/µA (See relevant section for details). If the pin is not connected, the switching frequency is 150kHz for each channel (300kHz on the load). The pin is forced high (5V Typ.) when an Over Voltage is detected; to recover from this condition, cycle VCC. Forcing the pin to a voltage lower than 0.6V , the device stops operation and enters the inhibit state. 18 20 FBG Remote sense amplifier inverting input. It has to be connected to the negative side of the load to perform programmable remote sensing through apposite resistors (see relative section). 19 21 FBR Remote sense amplifier non-inverting input. It has to be connected to the positive side of the load to perform programmable remote sensing through apposite resistors (see relative section). 20 to 22 22 to 24 VID0-2 Voltage IDentification pins. These input are internally pulled-up. They are used to program the output voltage as specified in Table 1 and to set the PGOOD, OVP and UVP thresholds. Connect to GND to program a ‘0’ while leave floating to program a ‘1’. 23 25 PGOOD This pin is an open collector output and is pulled low if the output voltage is not within the above specified thresholds and during soft-start. It cannot be pulled up above 5V . If not used may be left floating. 24 27 BOOT2 Channel 2 HS driver supply. This pin supplies the relative high side driver. Connect through a capacitor (100nF typ.) to the PHASE2 pin and through a diode to VCC (cathode vs. boot). 25 28 UGATE2 Channel 2 HS driver output. A little series resistor helps in reducing device-dissipated power. 26 29 PHASE2 Channel 2 HS driver return path. It must be connected to the HS2 mosfet source and provides the return path for the HS driver of channel 2. 27 30 LGA TE2 Channel 2 LS driver output. A little series resistor helps in reducing device-dissipated power. 28 31, PGND LS drivers return path. This pin is common to both sections and it must be connected through the closest path to the LS mosfets source pins in order to reduce the noise injection into the device. PAD THERMAL PA D Thermal pad connects the silicon substrate and makes a good thermal contact with the PCB to dissipate the power necessary to drive the external mosfets.Connect to the GND plane with several vias to improve thermal conductivity. PIN FUNCTION (continued) N. (*) Name DescriptionSO VFQFPN

The device is an integrated circuit realized in BCD technology. It provides complete control logic and pro- tections for a high performance dual-phase step-down converter optimized for high current DC/DC appli- cations. It is designed to drive N-Channel Mosfets in a two-phase synchronous-rectified buck topology. A 180 deg phase shift is provided between the two phases allowing reduction in the input capacitor current ripple, reducing also the size and the losses. The output voltage of the converter can be precisely regu- lated, programming the VID pins, from 0.900 to 3.300V with a maximum tolerance of ±0.9% over temper- ature and line voltage variations. The programmable Remote Sense Amplifier avoids the use of external resistor divider allowing recovering drops across distribution lines and also adjusting output voltage to dif- ferent values from the available reference. The device provides an average current-mode control with fast transient response. It includes a 150kHz free-running oscillator externally adjustable through a resistor. The error amplifier features a 15V/µs slew rate that permits high converter bandwidth for fast transient per- formances. Current information is read across the lower mosfets RdsON or across a sense resistor placed in series to the LS mos in fully differential mode. The current information corrects the PWM outputs in order to equalize the average current carried by each phase. Current sharing between the two phases is then limited at ±10% over static and dynamic conditions unless considering the sensing element spread. Droop effect can be programmed in order to minimize output filter and load transient response: the function can be disabled and the current information available on the pin can be used for other purposes. The device protects against Over-Current, with an OC threshold for each phase, entering in constant current mode. Since the current is read across the low side mosfets, the device keeps constant the bottom of the induc- tors current triangular waveform. When an Under Voltage is detected the device resets with all mosfets OFF and suddenly re-starts. The device also performs a crowbar Over-Voltage protection that immediate- ly latches the operations turning ON the lower driver and driving high the FAULT pin. PGOOD PGND PGNDS2 ISEN2 LGATE2 VSEN PHASE2 UGATE2 BOOT2 VCC SGND OSC / INH VID0 VID1 VID2 REF_IN/OUT PGNDS1 ISEN1 LGATE1 PHASE1 UGATE1 BOOT1 VCCDR FBR FBG Rg Rg LS2 HS2 CIN COUT Rg LS1 HS1 Vin GNDin PGOOD L6712 L6712A LOAD Rg FB COMP DROOP RFB RF CF

cillator so that the resulting switching frequency at the load side results in being doubled. proportionally to the current sunk (forced) from (into) the pin considering the internal gain of 6KHz/ µA. Figure 1. ROSC vs. Switching Frequency acts as a resistor divider (See relevant section). is delivered to an amplifier obtaining the VPROG voltage reference (i.e. the set-point of the error amplifier).

the RdsON), maintaining fast switching transition. at VCCDR pin is required to start operations of the device. of 30ns. If the current flowing in the inductor is negative, the source of high-side mosfet will never drop. even if the current is negative. cation. Power conversion is also flexible; 5V or 12V bus can be chosen freely. current is 2A with VCCDR = 12V. Figure 3. Drivers peak current: High Side (left) and Low Side (right)

imum rating overcome on ISENx pin). time must be at least 200ns to make proper reading of the delivered current. use this pin as a reference keeping the ISENx pin to this voltage. current carried by the two phases. Figure 4. Current reading timing (left) and circuit (right)

spond to IINFOx = 17.5µA (IFB = 35µA). then implemented allowing the device to recover if the over load cause has been removed. stant current are still valid in this case. in figure 7 to implement a differential remote sense amplifier. Figure 7. Remote Sense Amplifier Connections to regulate a voltage double of the reference, the above reported gain must be equal to ½. ages lower than the programmed reference.

plifier saves its offset in the accuracy calculation but doesn't allow remote sensing. ulation). In this way, a part of the drop due to the output capacitor ESR in the load transient is recovered. of the output voltage is minimized. with a remote amplifier gain of 1/2, the regulated output voltage results in being doubled. is sunk from the FB pin. The device regulates at the voltage programmed by the VID. Figure 8. Load Transient response (Left) and DROOP pin connection (Right). age the OVP / UVP conditions. implemented (Classic Voltage Mode).

is finished (2048 clock cycles after start-up). During Soft-Start this pin is forced low. start phase (hiccup mode, see figure 9). on both the low-side mosfets and switches off both the high-side mosfets in order to protect the load. threshold is the final reference programmed by the VID pins or available on the REF_IN/OUT pin. Figure 9. UVP Protection & Hiccup Mode. VID in 2048 clock periods as shown in figure 10. Good comparator is enabled and the PGOOD signal is then driven high (See fig. 10). comparator is always active with a threshold equal to the +15%_min of the final reference. The Soft-Start will not take place, if both VCC and VCCDR pins are not above their own turn-on thresholds. fets and protections are turned off until the condition is removed.

Figure 10. Soft Start. comparing with a single-phase operation. worst case condition that happens for D=0.25 and D=0.75. efits in high frequency noise de coupling, noise generated by parasitic components along power path. Figure 11. Input RMS Current vs. Duty Cycle (D) and Driving Relationships.

2048 Clock Cycles

The output capacitor is a basic component for the fast response of the power supply. Two-phase topology reduces the amount of output capacitance needed because of faster load transient response (switching frequency is doubled at the load connections). Current ripple cancellation due to the 180° phase shift between the two phases also reduces requirements on the output ESR to sustain a spec- ified voltage ripple. Moreover, if DROOP function is enabled, bigger ESR can be used still keeping the same transient toler- ances. In fact, when a load transient is applied to the converter's output, for first few microseconds the current to the load is supplied by the output capacitors. The controller recognizes immediately the load transient and increases the duty cycle, but the current slope is limited by the inductor value. The output voltage has a first drop due to the current variation inside the capacitor (neglecting the effect of the ESL): A minimum capacitor value is required to sustain the current during the load transient without discharge it. The voltage drop due to the output capacitor discharge is given by the following equation: Where DMAX is the maximum duty cycle value. The lower is the ESR, the lower is the output drop during load transient and the lower is the output voltage static ripple. INDUCTOR DESIGN The inductance value is defined by a compromise between the transient response time, the efficiency, the cost and the size. The inductor has to be calculated to sustain the output and the input voltage variation to maintain the ripple current ∆IL between 20% and 30% of the maximum output current. The inductance value can be calculated with this relationship: Where FSW is the switching frequency, VIN is the input voltage and VOUT is the output voltage. Increasing the value of the inductance reduces the ripple current but, at the same time, reduces the con- verter response time to a load transient. The response time is the time required by the inductor to change its current from initial to final value. Since the inductor has not finished its charging time, the output current is supplied by the output capacitors. Minimizing the response time can minimize the output capacitance required. The response time to a load transient is different for the application or the removal of the load: if during the application of the load the inductor is charged by a voltage equal to the difference between the input and the output voltage, during the removal it is discharged only by the output voltage. The following ex- pressions give approximate response time for ∆I load transient in case of enough fast compensation net- work response: The worst condition depends on the input voltage available and the output voltage selected. Anyway the ∆VOUT ∆IOUT ESR⋅= ∆VOUT ∆I2 OUT L⋅ L VIN VOUT– VOUT VIN tapplication L ∆I⋅ L ∆I⋅ VOUT

and the maximum input voltage available. function not active) a Voltage Mode topology must be considered instead. block diagram of the main control loop. Figure 12. Main Control Loop Diagram Active current sharing is implemented using the information from Trans conductance differential amplifier. cycle whose dominant value is set by the error amplifier at COMP pin (See fig. 13). The current sharing control is a high bandwidth control loop allowing current sharing even during load transients.

Figure 13. Current Sharing Control Loop. Where ∆IREAD is the difference between one phase current and the ideal current (IMAX/2). the DROOP pin flows into RFB implementing the dependence of the output voltage from the read current. ■ RA_Gain is the Remote Amplifier Gain.

Figure 14. ACM Control Loop Gain Block Diagram (left) and Bode Diagram (right). designed and the zero is fixed by ESR and the Droop resistance. RF-CF zero in correspondence with the L-C filter resonance.

2 RDROOP

things to consider when designing such high current applications. drivers, reducing the board space. the length of each connection as much as possible. plane and anyway realized by wide and thick copper traces. Figure 15. Power connections and related connections layout guidelines (same for both phases). due to multiple connections. ■ Power Connections Related. copper traces are so minimized. sequence, the higher are the voltage spikes corresponding to the gate PWM rising and falling signals.

that the switching losses for the high side mosfet are significantly increased. excess of 2A (30 mils wide is suggested). imize the loop that is created. – Decoupling capacitor from VCC and SGND placed as close as possible to the involved pins. itor sustains the peak currents requested by the low-side mosfet drivers. (output capacitor) if Remote Sense is not implemented to avoid undesirable load regulation effect. Figure 16. Device orientation (left) and sense nets routing (right).

sible to the sensing elements, dedicated current sense resistor or low side mosfet RdsON. with HGATEx) with a wide net (30 mils) and the ISENx pin to the LS Drain (route together with PGNDSx). mosfet source (together with ISENx net). Right and wrong connections are reported in Figure 17. Symmetrical layout is also suggested to avoid any unbalance between the two phases of the converter. Figure 17. PCB layout connections for sense nets. Wrong (left) and correct (right) connections for the current reading sensing nets.

DIM. mm inch A1 0.020 0.050 0.0008 0.0019 A2 0.650 1.000 0.025 0.039 A3 0.250 0.01 ddd 0.080 0.003 VFQFPN-36 (6x6x1.0mm) Very Fine Quad Flat Package No lead 7185332 F

DIM. mm inch A 2.65 0.104 a1 0.1 0.3 0.004 0.012 b 0.35 0.49 0.014 0.019 b1 0.23 0.32 0.009 0.013 C 0.5 0.020 c1 45 ° (typ.) D 17.7 18.1 0.697 0.713 E 10 10.65 0.394 0.419 e 1.27 0.050 e3 16.51 0.65 F 7.4 7.6 0.291 0.299 L 0.4 1.27 0.016 0.050 S8 ° (max.) OUTLINE AND MECHANICAL DATA

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publicati on are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectro nics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners © 2004 STMicroelectronics - All rights reserved STMicroelectronics GROUP OF COMPANIES Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Ital y - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States L6712A L6712