L6701 STMICROELECTRONICS | Alldatasheet
Document overview
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- PDF pages: 44
Technical content
Datasheet sections
- 1 Device Description
- 2 Pins description and connection diagrams
- 2.1 Pin description
- 3 Maximum Ratings
- 3.1 Absolute maximum ratings
- 3.2 Thermal data
- 4 Electrical specifications
- 4.1 Electrical characteristics
- 5 Typical application circuit and block diagram
- 5.1 Application circuit
- 5.2 Block diagram
- 6 VID Tables
- 7 Configuring the Device: DAC Selection
- 7.1 Single-Wire CPU Automatic Detection
- 8 Driver Section
- 8.1 Power Dissipation
- 9 Current Sharing Loop and Current Reading
- 9.1 Current Sharing Loop
- 9.2 Current Reading for Current Sharing
- 10 Output Voltage Positioning
- 10.1 Load-Line (Droop Function - Optional)
- 10.2 Fully-Differential Load-Line (Droop Function - Optional)
- 10.3 Offset (Optional)
- 10.4 Remote Voltage Sense
- 10.5 Maximum Duty Cycle limitation
Features
■ MULTI-DAC: VR9, VR10 AND K8 DAC SELECTABLE THROUGH SINGLE PIN ■ 0.7% OUTPUT VOLTAGE ACCURACY ■ ADJUSTABLE REFERENCE OFFSET ■ HIGH CURRENT INTEGRATED DRIVERS ■ DYNAMIC VID MANAGEMENT ■ ACCURATE FULLY-DIFFERENTIAL LOAD- LINE CURRENT-SENSE ACROSS MAIN INDUCTORS MAKES BOM INDEPENDENT ON THE LAYOUT ■ PRECISE CURRENT-SHARING AND OCP ACROSS LS MOSFETS ■ CONSTANT OVER-CURRENT PROTECTION ■ FEEDBACK DISCONNECTION PROTECTION ■ PRELIMINARY OV PROTECTION ■ OSCILLATOR INTERNALLY FIXED AT 100kHz (300kHz RIPPLE) EXT ADJUSTABLE ■ SS_END / PGOOD SIGNAL ■ INTEGRATED REMOTE-SENSE BUFFER ■ PWSSO36 PACKAGE WITH EXPOSED PAD
Applications
■ HIGH CURRENT VRM / VRD FOR DESKTOP / SERVER/ WORKSTATION CPUs ■ HIGH DENSITY DC / DC CONVERTERS
Description
L6701 is an extremely simple, low-cost solution to implement a three phase step-down controller with integrated high-current drivers in a compact PowerSSO-36 package with exposed pad. The device embeds three selectable DACs: with a single pin it is possible to program the device to work in compatibility with VR9, VR10 or K8 applications managing D-VID with ±0.7% output voltage accuracy over line and temperature variations. Additional programmable offset can be added to the reference voltage with a single external resistor. Fast protection against load over current let the system works in Constant Current mode until UVP. Preliminary OVP allows full load protection in case of startup with failed HS. Furthermore, feedback disconnection prevents from damaging the load in case of misconnections in the system board. Combined use of DCR and R DS(on) current sensing assures precision in voltage positioning and safe current sharing and OCP per each phase. PowerSSO-36 Order codes Part number Package Packing L6701 PowerSSO-36 Tube L6701TR PowerSSO-36 Tape & Reel
1 Device Description L6701
1 Device Description
L6701 is multi-phase PWM controller with embedded high-current drivers that provides complete control logic and protections for a high-performance step-down DC-DC voltage regulator, optimized for advanced microprocessor power supply. Multi-phase buck is the simplest and most cost-effective topology employable to satisfy the increasing current demand of newer microprocessors and the modern high-current DC/DC converters and POLs requirements. It allows distributing equally load and power between the phases using smaller, cheaper and most common external power MOSFETs and inductors. Moreover, thanks to the equal phase-shift between each phase, the input and output capacitor count results in being reduced. Phase-interleaving causes in fact input rms current and output ripple voltage reduction and shows an effective output switching frequency increase: the 100kHz free-running frequency per phase, externally adjustable through a resistor, results multiplied on the output by the number of phases so reaching 300kHz in free-running. L6701 includes multiple DACs, selectable through an apposite pin, allowing compatibility with both Intel VR9, VR10 and AMD Hammer specifications, also performing D-VID transitions accordingly. In particular for Intel CPUs, it allows to automatically recognize the CPU with a single-wire connection, without any additional external component, by proper connecting the selector pin to the proper CPU pin. Precise voltage positioning (LL) is possible thanks to an accurate fully-differential current-sense across the main inductors still using only two pins for current-reading (pat. pend.): this makes any BOM insensitive to the board layout saving time in the design stage. The device internally balance the current driven by each phase by sensing the voltage drop across the LS MOSFET R DS(on). OC protection is effective with a threshold for each phase causing the device to work in constant-current mode. The controller provides output voltage protections to avoid any load damage due to failed components and/or feedback misconnections. Over-Voltage protects the load from dangerous over stress latching immediately the device by turning-on the lower driver and driving high the FAULT pin. Furthermore, preliminary-OVP protection also allows the device to protect the load from dangerous OVP when V CC is not above the UVLO threshold. Under-Voltage protection causes the device to stop switching when set while Over-Current protection, with a threshold for each phase, causes the device to enter in constant current mode until the latched UVP. L6701 implements soft-start increasing the reference up to the final value in 2048 clock cycles in closed loop regulation. Low-Side-Less feature allows the device to perform soft-start over pre-biased output avoiding dangerous current return through the main inductors as well as negative spike at the load side. The compact PowerSSO-36 package with exposed thermal pad allows dissipating the power to drive the external MOSFET through the system board.
2 Pins description and connection diagrams
Figure 1. Pins connection (Top view)
2.1 Pin description
Table 1. Pins description 2V C C Device Power Supply and LS driver supply. Operative voltage is 12V ±15%. Filter with at least 1 µF MLCC vs. ground. 3L G A T E 1 Channel 1 LS Driver Output. A small series resistor helps in reducing device-dissipated power. 4 PGND LS Drivers return path. Connect to Power ground Plane. 5L G A T E 2 Channel 2 LS Driver Output. A small series resistor helps in reducing device-dissipated power. 6L G A T E 3 Channel 3 LS Driver Output. A small series resistor helps in reducing device-dissipated power.
7 BOOT1
8U G A T E 1 Channel 1 HS driver output. A small series resistors helps in reducing device-dissipated power.
9 PHASE1
Channel 1 HS driver return path.
2 Pins description and connection diagrams L6701
10 BOOT2
11 UGATE2 Channel 2 HS driver output. A small series resistors helps in reducing device-dissipated power.
12 PHASE2
Channel 2 HS driver return path.
13 BOOT3
14 UGATE3 Channel 3 HS driver output. A small series resistors helps in reducing device-dissipated power.
15 PHASE3
Channel 3 HS driver return path.
16 SSEND /
SSEND - Intel VR10 Mode. Soft Start END Signal. any protection. Pull up to 5V (typ) or lower, if not used it can be left floating. PGOOD - Intel VR9 & AMD Hammer Mode .
17 DAC_SEL
It allows programming the DAC table for the regulation. Internally pulled-up to 5V. connect to GND through 82kΩ to program VR10 DAC. Section 7.1 for connections to enable CPU auto-detection.
18 OSC / EN /
resets the device from any latching condition. from this condition, cycle VCC or the OSC pin. See Section 13 for details. Table 1. Pins description (continued)
19 REF_IN
Reference Input for the regulation. details. This pin is used as input for the protections.
20 REF_OUT
Voltage IDentification Pins. Table 5, Table 6 and Table 7 according to DAC_SEL status.
27 FBR
Remote Buffer Non Inverting Input. Connect to the positive side of the load to perform remote sense. See Section 16 for proper layout of this connection.
28 FBG
Remote Buffer Inverting Input. Connect to the negative side of the load to perform remote sense. See Section 16 for proper layout of this connection. Section 9 and Section 13.6 for details.
32 CS+
Droop Current Sense non-inverting input.
33 CS-
Droop Current Sense inverting input. (when applicable). See Section 13 for details.
36 COMP
Error Amplifier Output. Connect with an R F - CF vs. FB. The device cannot be disabled by pulling down this pin. with the PCB to dissipate the power necessary to drive the external MOSFETs. Connect to the PGND plane with several VIAs to improve thermal conductivity.
3 Maximum Ratings L6701
3 Maximum Ratings
3.1 Absolute maximum ratings
3.2 Thermal data
Table 2. Absolute Maximum Ratings Table 3. Thermal data
4 Electrical specifications
4.1 Electrical characteristics
Table 4. Electrical Characteristics (VCC = 12V±15%, TJ = 0°C to 70°C unless otherwise specified).
4 Electrical specifications L6701
Table 4. Electrical Characteristics (continued) (VCC = 12V±15%, TJ = 0°C to 70°C unless otherwise specified).
5 Typical application circuit and block diagram
5.1 Application circuit
Figure 2. Typical application circuit
31 RISEN
29 RISEN
5 Typical application circuit and block diagram L6701
Figure 3. Typical Application Circuit: Fully Differential Current Sense (Pat.Pend.)
5.2 Block diagram
Figure 4. Block diagram
3 PHASE
6 VID Tables L6701
6 VID Tables
Table 5. Voltage IDentification (VID) for Intel VR10 DAC .
- Since the VIDx pins program the maximum output voltage, according to VR10.x specifications, the device automatically
the system tolerance performance since the reference already offset is trimmed in production within ±0.7%. Table 6. Voltage IDentification (VID) for Intel VR9 DAC (VID5 doesn’t care)
- Since the VIDx pins program the maximum output voltage, the device automatically regulates to a voltage 19mV lower
since the reference already offset is trimmed in production within ±0.7%. Table 5. Voltage IDentification (VID) for Intel VR10 DAC . (continued)
Table 7. Voltage IDentification (VID) for AMD Hammer DAC
11111 O F F 11111 O F F
7 Configuring the Device: DAC Selection
VID5 gives the option to introduce +25mV offset to the regulation (See Table 7). realized by means of a series of resistors providing a partition of the internal voltage reference. DAC output is delivered to an amplifier obtaining the voltage reference available on REF_OUT. consequence of different CPU specifications, see Table 8 for details.
7.1 Single-Wire CPU Automatic Detection
See CPU related documentation for further details about compatibility. Table 8. L6701 Configuration
8 Driver Section L6701
8 Driver Section
The integrated high-current drivers allow using different types of power MOS (also multiple MOS to reduce the equivalent R DS(on)), maintaining fast switching transition. The drivers for the high-side MOSFETs use BOOTx pins for supply and PHASEx pins for return. The drivers for the low-side MOSFETs use the VCC pin for supply and PGND pin for return. The controller embodies a anti-shoot-through and adaptive dead-time control to minimize low side body diode conduction time maintaining good efficiency saving the use of Schottky diodes: when the high-side MOSFET turns off, the voltage on its source begins to fall; when the voltage reaches 2V, the low-side MOSFET gate drive is suddenly applied. When the low-side MOSFET turns off, the voltage at LGATEx pin is sensed. When it drops below 1V, the high-side MOSFET gate drive is suddenly applied. If the current flowing in the inductor is negative, the source of high-side MOSFET will never drop. To allow the low-side MOSFET to turn-on even in this case, a watchdog controller is enabled: if the source of the high-side MOSFET does not drop, the low side MOSFET is switched on so allowing the negative current of the inductor to recirculate. This mechanism allows the system to regulate even if the current is negative. Power conversion input is flexible: 5V, 12V bus or any bus that allows the conversion (See maximum duty cycle limitations) can be chosen freely.
8.1 Power Dissipation
L6701 embeds high current MOSFET drivers for both high side and low side MOSFETs: it is then important to consider the power that the device is going to dissipate in driving them in order to avoid overcoming the maximum junction operative temperature. In addition, since the device has an exposed pad to better dissipate the power, the thermal resistance between junction and ambient consequent to the layout is also important: thermal pad need to be soldered to the PCB ground plane through several VIAs in order to facilitate the heat dissipation. Two main terms contribute in the device power dissipation: bias power and drivers' power.
- Device Power (PDC) depends on the static consumption of the device through the supply pins and it is simply quantifiable as follow (assuming to supply HS and LS drivers with the same VCC of the device):
- Drivers' power is the power needed by the driver to continuously switch on and off the external MOSFETs; it is a function of the switching frequency and total gate charge of the selected MOSFETs. It can be quantified considering that the total power P SW dissipated to switch the MOSFETs (easy calculable) is dissipated by three main factors: external gate resistance (when present), intrinsic MOSFET resistance and intrinsic driver resistance. This last term is the important one to be determined to calculate the device power dissipation. The total power dissipated to switch the MOSFETs results: External gate resistors helps the device to dissipate the switching power since the same power P SW will be shared between the internal driver impedance and the external resistor resulting in a general cooling of the device. PDC VCC ICC 3I CCDRx⋅ 3I BOOTx⋅++()⋅= PSW 3F SW QGHS VBOOT⋅ QGLS VCCDRx⋅+()⋅⋅=
Figure 5. Dissipated Power
9 Current Sharing Loop and Current Reading L6701
9 Current Sharing Loop and Current Reading
9.1 Current Sharing Loop
the voltage error amplifier in order to equalize the current carried by each phase.
9.2 Current Reading for Current Sharing
chip between ISENx and the reading point (usually the LS MOSFET Drain). Figure 6. Current Sharing Loop and Current Reading Connections
10 Output Voltage Positioning
to the resistance RFB connected. Figure 7. Voltage Positioning
10.1 Load-Line (Droop Function - Optional)
the output current causes the output voltage to vary according to the sensed current. (IDROOP). RFB gives the final gain to program the desired load-line slope.
10 Output Voltage Positioning L6701
Where RLL is the resulting load-line resistance implemented by the system. equivalent output resistance R LL and a voltage value of VID. where RD is typically designed to have I CS = 35µA at the maximum output current (OCP). Figure 8. Droop Function Current Reading Network
10.2 Fully-Differential Load-Line (Droop Function - Optional)
the desired load-line slope. LLDIFF and a voltage value of VID. where RD is typically designed to have I CS = 35µA at the maximum output current (OCP). Figure 9. Fully Differential Load-Line Current-Reading (pat. pend.)
Table 9. Comparison between different load-line implementations.
10.3 Offset (Optional)
10.4 Remote Voltage Sense
guarded by a power plane results in common mode coupling for any picked-up noise.
10.5 Maximum Duty Cycle limitation
response at light load as well as assuring robust over-current protection. Figure 10. Maximum Duty Cycle limitation
0.80 T SW IISENx 0µA=⋅
0.40 T SW IISENx 35µA=⋅⎩
0.40 VIN
0.80 VIN
Limted-TON Output Char. Limted-TON Output Char.
11 Dynamic VID Transitions L6701
11 Dynamic VID Transitions
slowing down the output voltage dV/dt also causing the failure in the D-VID test. Figure 11. Dynamic VID Transitions and K8, this frequency is lowered to F DVID = FSW.
L6701 11 Dynamic VID Transitions Caution: If the new VID code is more than 1 LSB different from the previous, the device will execute the transition stepping the reference with the DVID-clock frequency F DVID until the new code has reached: for this reason it is recommended to carefully control the VID change rate in order to carefully control the slope of the output voltage variation especially in VR10 mode. Warning: DVID sample and hold clock depends on the switching frequency F SW. To correctly perform DVID transition so following the VID change rate, it is required to have at least 2 complete cycles of the FDVID clock between every VID transition. If the VID update-rate is, for example, 5µsec., the minimum operating frequency results to be F SW > 133kHz in VR10 mode.
12 Soft Start L6701
12 Soft Start
closed loop regulation. At the end of the digital Soft-Start, SSEND/PGOOD signal is set free. Operative Mode. DAC table information is frozen just before initializing the Soft-Start. thresholds and the EN pin is set free.
12.1 Low-Side-Less Startup (LSLess)
biased output (See Figure 12). view: protections by-pass this turning ON the LS MOSFET in case of need. Figure 12. LSLess Startup (left) vs. Non-LSLess Startup (right)
L6701 13 Output voltage Monitor and Protections
13 Output voltage Monitor and Protections
L6701 monitors through pin VSEN the regulated voltage in order to manage the OVP , UVP and PGOOD (when applicable) conditions. Protections are active also during soft-start (See Section 12 for details) while are masked during D-VID transitions with an additional 32 clock cycle delay after the transition has finished to avoid false triggering. In addition, preliminary over-voltage protection is also provided to protect the load from high- side MOSFET failures before the system turn-ON.
13.1 Under Voltage
If the output voltage monitored by VSEN drops more than -400mV below the programmed reference for more than one clock period, the device turns off all MOSFETs driving high the FAULT pin and latches the condition: to recover it is required to cycle Vcc or the EN pin. This is independent by the selected operative mode.
13.2 Preliminary Over Voltage
To provide a protection while VCC is below the UVLO VCC threshold is fundamental to avoid damage to the load in case of failed HS MOSFETs. In fact, since the device is supplied from the 12V bus, it is basically “blind” for any voltage below the turn-on threshold (UVLO VCC). In order to give full protection to the load, a preliminary-OVP protection is provided while VCC is within UVLO VCC and UVLOOVP. According to the DAC_SEL pin status, this protection turns-on the low side MOSFETs as long as the FBR pin voltage is greater than 1.9V for VR10 and 2.1V for VR9 and K8 with a 300mV hysteresis (See Table 10). When set, the protection drives the LS MOSFET with a gate-to- source voltage depending on the voltage applied to VCC. This protection depends also on the EN pin status as detailed in Figure 13. Preliminary OVP is always active before UVLO VCC for all operative modes with intervention thresholds dependent on the DAC_SEL pin status. A simple way to provide protection to the output in all conditions when the system is OFF (then avoiding the unprotected red region in Figure 13-Left) consists in supplying the controller through the 5VSB bus with an OR-ing diode solution as shown in Figure 13-Right: 5VSB is always present before +12V and, in case of HS short, the LS MOSFET is driven with 5V assuring a reliable protection of the load. When using the OR-ing diode solution, OR-ing diodes need to be sized according to the device current consumption: the two diodes will then results to be different since the diode connected to the 12V bus needs to carry the current for normal operations (I RMS) and the diode connected to the 5VSB (IRMS-PREOVP) need to carry only the current in case of Pre-OVP protection is active. Device current consumption (I RMS) in normal operations depends on the external MOSFET configuration as follow: Device current consumption when Pre-OVP is active depends on the output filter configuration since LS MOSFETs switching frequency depends on the leakage that is charging the output filter. Test on the bench is required but, for an over-sized solution, the same diode identified for the +12V bus can be used. IRMS 3F SW QGHS QGLS+() ICC 3I CCDRx⋅ 3I BOOTx⋅++()+⋅⋅=
13 Output voltage Monitor and Protections L6701
Figure 13. Output Voltage Protections and typical principle connections
13.3 Over Voltage
low-side MOSFETs and switches off all the high-side MOSFETs in order to protect the load.
13.4 Feedback Disconnection
- Remotely, through the remote buffer, across VSEN
- Locally across the CS- pin (negligibly offset by ). By comparing the voltage present at these two different locations, L6701 is able to understand if the output voltage feedback is connected. When CS- is more than 1V higher than VSEN, (See Figure 14) the device stops switching with the low side MOSFETs permanently ON and drives high the FAULT pin. The condi tion is latched until VCC or EN cycled.
Table 10. OVP and Preliminary OVP Thresholds
Figure 14. Feedback Disconnection
13.5 PGOOD (Only for VR9 and K8 Modes)
when the output voltage drops below -230mV of the programmed voltage.
13.6 Over Current Protection
and the HS is turned on with a duty cycle driven by the PWM comparator. off and the device works in the usual way until another OCP event is detected. the UVP threshold causes the device to latch driving high the OSC pin. stops working. Cycle the power supply or the EN pin to restart operation. Figure 15. Constant Current Operation
L6701 13 Output voltage Monitor and Protections The trans-conductance resistor R ISENx can be designed considering that the device limits the bottom of the inductor current ripple and also considering the additional current delivered during the quasi-constant-current behavior as previously described in the worst case conditions. Moreover, when designing D-VID compatible syst ems, the additional current due to the output filter charge during dynamic VID transitions must be considered. where RISENx IOCPx max() RdsON max()⋅ IOCTH min() IOUT OCP() ∆IPP IDV I D–
14 Oscillator L6701
14 Oscillator
side results in being tripled (300kHz). power dissipation must be checked prior to design high switching frequency systems. Figure 16. R
15 System Control Loop Compensation
Figure 17. Main Control Loop
- is the equivalent output resistance determined by the droop function ( for fully differential current sense);
- ZP(s) is the impedance resulting by the parallel of the output capacitor (and its ESR) and the applied load RO;
- ZF(s) is the compensation network impedance;
- ZL(s) is the parallel of the three inductor impedance;
- A(s) is the error amplifier gain; PWM3 PWM2 PWM1 Reference ERROR AMPLIFIER COMP FB ZF(s) ZF(s) IDROOP COUT ROUT CURRENT SHARING DUTY CYCLE CORRECTION IINFO1 IINFO3 IINFO2 GLOOP s() PWM Z F s() RDROOP ZP s()+()⋅⋅ ZP s() ZL s()+[] ZF s() ⎛⎞ RFB⋅+⋅ RDROOP DCR RD RDROOP 3 DCR RD
15 System Control Loop Compensation L6701
- is the PWM transfer function where ∆VOSC is the oscillator ramp amplitude and has a typical value of 3V. Removing the dependence from the Error Amplifier gain, so assuming this gain high enough, and with further simplifications, the control loop gain results: The system Control Loop gain (See Figure 18) is designed in order to obtain a high DC gain to minimize static error and to cross the 0dB axes with a constant -20dB/dec slope with the desired crossover frequency ω T. Neglecting the effect of Z F(s), the transfer function has one zero and two poles; both the poles are fixed once the output filter is designed (LC filter resonance ω LC) and the zero (ωESR) is fixed by ESR and the Droop resistance.
Figure 18. Equivalent Control Loop Block Diagram (left) and Bode Diagram (right). resonance assures a simple -20dB/dec shape of the gain. frequency lower than the above reported zero.
3 RO⋅
15.1 Compensation Network Guidelines
- Increase RF to increase the system bandwidth accordingly;
- Decrease RF to decrease the system bandwidth accordingly;
- Increase CF to move ωF to low frequencies increasing as a consequence the system phase margin. Having the fastest compensation network gives not the confidence to satisfy the requirements of the load: the inductor still limits the maximum dI/dt that the system can afford. In fact, when a load transient is applied, the best that the controll er can do is to “saturate” the duty cycle to its maximum (d MAX) or minimum (0) value. The output voltage dV/dt is then limited by the inductor charge / discharge time and by the output capacitance. In particular, the most limiting transition corresponds to the load removal since the inductor results being discharged only by V OUT (while it is charged by d MAXVIN-VOUT during a load appliance). Referring to Figure 19-left, further tuning the Compensation network cannot give any improvements unless the output filter changes: only modifying the main inductors or the output capacitance improves the system response.
Figure 19. Best Load Transient achievable (d=0) and R
16 Layout Guidelines L6701
16 Layout Guidelines
Since the device manages control functions and high-current drivers, layout is one of the most important things to consider when designing such high current applications. A good layout solution can generate a benefit in lowering power-dissipation on the power paths, reducing radiation and a proper connection between signal and power ground can optimize the performance of the control loops. Two kind of critical components and connections have to be considered when layouting a VRM based on L6701: power components and connections and small signal components connections.
16.1 Power Components and Connections
These are the components and connections where switching and high continuous current flows from the input to the load. The first priority when placing components has to be reserved to this power section, minimizing the length of each connection and loop as much as possible. To minimize noise and voltage spikes (EMI and losses) these interconnections must be a part of a power plane and anyway realized by wide and thick copper traces: loop must be anyway minimized. The critical components, i.e. the power transistors, must be close one to the other. The use of multi-layer printed circuit board is recommended. Figure 20 shows the details of the power connections involved and the current loops. The input capacitance (C IN), or at least a portion of the total capacitance needed, has to be placed close to the power section in order to eliminate the stray inductance generated by the copper traces. Low ESR and ESL capacitors are preferred, MLCC are suggested to be connected near the HS drain. Use proper VIAs number when power traces have to move between different planes on the PCB in order to reduce both parasitic resist ance and inductance. Moreover, reproducing the same high-current trace on more than one PCB layer will reduce the parasitic resistance associated to that connection. Connect output bulk capacitor as near as possible to the load, minimizing parasitic inductance and resistance associated to the copper trace also adding extra decoupling capacitors along the way to the load when this results in being far from the bulk capacitor bank. Gate traces must be sized according to the driver RMS current delivered to the power MOSFET. The device robustness allows managing applications with the power section far from the controller without losing performances. Anyway, when possible, it is suggested to minimize the distance between controller and power section.
16.2 Small Signal Components and Connections
driving net for this pin in order to minimize coupled noise. from the load will cause a non-optimum load regulation, increasing output tolerance. possible to the sensing elements. – using non-capacitive boot diodes (such as standard diodes). Figure 20. Power connections and related connections layout (same for all phases).
16.3 Embedding L6701-based VRs
When embedding the VR into the application, additional care must be taken since the whole VR is a switching DC/DC regulator and the most common systems in which it has to work are digital systems such as MB or similar. In fact, latest MB has become faster and powerful: high speed data bus are more and more common and switching-induced noise produced by the VR’ MOSFETs can affect data integrity if not following additional layout guidelines. Few easy points must be considered mainly when routing traces and planes in which high switching currents flow (high switching currents cause voltage spikes across the stray inductance of the trace causing noise that can affect the near traces): Keep safe guarding distance between high current switching VRD traces and data buses, especially if high-speed data bus to minimize noise coupling. Keep safe guard distance or filter properly when routing bias traces for I/O sub-systems that must walk near the VRD. Possible causes of noise can be located in the PHASE connections, MOSFET gate drive and Input voltage path (from input bulk capacitors and HS drain). Also PGND connections must be considered if not insisting on a power ground plane. These connections must be carefully kept far away from noise-sensitive data bus. Since the generated noise is mainly due to the switching activity of the VR, noise emissions depend on how fast the current switches. To reduce noise emission levels, it is also possible, in addition to the previous guidelines, to reduce the current slope by properly tuning the HS gate resistor and the PHASE snubber network.
In order to meet environmental requirements, ST offers these devices in ECOPACK ® packages. These packages have a Lead-free second level interconnect . The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
- “D and E” do not include mold flash or protusions. Mold flash or protusions shall not exceed 0.15mm (0.006”)
- No intrusion allowed inwards the leads.
- Flash or bleeds on exposed die pad shall not exceed 0.4 mm per side
Figure 21. Package Dimensions
Date Revision Description of Changes 13-Dec-2005 1 First draft
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the con sequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publicatio n are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics produ cts are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectron ics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners © 2005 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Ital y - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America