L6699 STMICROELECTRONICS | Alldatasheet
Document overview
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- PDF pages: 38
Technical content
Datasheet sections
- 1 Description
- 2 Electrical ratings
- 3 Thermal data
- 4 Pin connections
- 5 Electrical data
- 6 Application information
- 6.1 Oscillator
- 6.2 Adaptive deadtime
- 6.3 Safe-start procedure
- 7 Operation at no load or very light load
- 8 Current sensing, OCP and OLP
- 9 Capacitive-mode detection function
- 10 Line sensing function
- 11 Latched shutdown
- 12 Bootstrap section
- 13 Package information
- 14 Revision history
Features
■ Symmetrical duty cycle, variable frequency control of resonant half bridge ■ Self-adjusting adaptive deadtime ■ High-accuracy oscillator ■ 2-level OCP: frequency-shift and immediate shutdown ■ Interface with PFC controller ■ Anti-capacitive-mode protection ■ Burst-mode operation at light load ■ Input for brownout protection or power-on/off sequencing ■ “Safe-start” procedure prevents hard switching at startup ■ 600 V rail compatible high-side gate driver with integrated bootstrap diode and high dv/dt immunity ■ -300/800 mA high-side and low-side gate drivers with UVLO pull-down ■ SO16N package
Applications
■ SMPS for LCD TVs, desktop and AIO PCs, servers, Telecom power ■ AC-DC adapter, open frame SMPS Figure 1. Block diagram Table 1. Device summary
1 Description
The L6699 is a double-ended controller specific to series-resonant half bridge topology. Both LLC and LCC configurations are supported. It provides symmetrical complementary duty cycle: the high-side switch and the low-side switch are driven ON/OFF 180° out-of- phase for exactly the same time. Output voltage regulation is obtained by modulating the operating frequency. The deadtime inserted between the turn-off of one switch and the turn- on of the other one is automatically adjusted to best fit the transition times of the half bridge midpoint. To drive the high-side switch with the bootstrap approach, the IC incorporates a high voltage floating structure able to withstand more than 600 V with a synchronous-driven high voltage DMOS that replaces the external fast-recovery bootstrap diode. The IC enables the user to set the operating frequency range of the converter by means of a high-accuracy externally programmable oscillator. At startup, in addition to the traditional frequency-shift soft-start (the switching frequency starts from a preset maximum value and then decays as far as the steady-state value determined by the control loop), a proprietary circuit controls the half bridge to prevent hard- switching from occurring in the initial cycles because of the unbalance in the V·s applied to the transformer. At light load the IC can be forced to enter a controlled burst-mode operation that keeps the converter input consumption as low as possible. IC protection functions include a current sense input for OCP with frequency shift and delayed shutdown with automatic restart. Fast shutdown with automatic restart occurs if this first-level protection cannot control the primary current. Additionally, the IC prevents the converter from working in or too close to the capacitive mode, to guarantee soft-switching. A latched disable input (DIS) can be used to implement OTP and/or OVP . The combination of these protection features offers the highest degree of safety. Other functions include a not-latched active-low disable input with current hysteresis, useful for power sequencing or for brownout protection, and an interface with the PFC controller that enables the switching-off of the pre-regulator during fault conditions or during burst- mode operation.
2 Electrical ratings
3 Thermal data
Table 2. Absolute maximum ratings Table 3. Thermal data
4 Pin connections
Figure 2. Pin connections (top view) Table 4. Pin functions
1 CSS
or in, the capacitive-mode operation. very low input average power. as the voltage drops below 0.3 V.
the phototransistor of an optocoupler is connected to this pin through a resistor. frequency shift at startup to prevent excessive energy inrush (soft-start). (see Figure 1: Block diagram). Tie the pin to RFmin if burst-mode is not used.
6 ISEN
peak primary current. This condition is allowed for a maximum time set at pin 2. restart delay procedure (see DELAY pin description for more information). prevent the device from operating correctly. CC with a =100 kΩ resistor if not used. CC pin goes below the UVLO threshold. Tie the pin to GND if the function is not used. UVLO, it is open. Leave the pin unconnected if not used. Table 4. Pin functions (continued)
Figure 3. Typical system block diagram
10 GND
11 LVG
is actively pulled to GND during UVLO.
12 V CC
Supply voltage of both the signal part of the IC and the low-side gate driver. obtain a clean bias voltage for the signal part of the IC.
14 OUT
15 HVG
replaces the normally used external diode.
5 Electrical data
RFmin = 12 KΩ; unless otherwise specified. Table 5. Electrical characteristics
Table 5. Electrical characteristics (continued)
- Values tracking each other.
- Refer to adaptive deadtime section, Figure 9.
6 Application information
The L6699 is an advanced double-ended controller specific to resonant half bridge topology. efficiency and low EMI emissions. under a broader load range, from full to light load.
- Variable frequency at heavy and medium/light load. A relaxation oscillator (see
- Burst-mode control with no or very light load. When the load falls below a value, the
Figure 4. Multimode operation of the L6699
6.1 Oscillator
- a resistor RFmin connected between the pin and ground that determines the minimum
- a resistor RFmax connected between the pin and the collector of the (emitter-
bridge is operated at when the phototransistor is fully saturated. the setting up of a frequency shift at startup (see Section 6.3: Safe-start procedure). Note that the contribution of this branch is zero during steady-state operation. Figure 5. Oscillator's internal block diagram
Figure 6. Oscillator waveforms and their relationship with gate-driving signals Section 7: Operation at no load or very light load). Section 12: Bootstrap section). Table 6. Recommended values for CF as a function of the startup frequency f start
6.2 Adaptive deadtime
A deadtime TD inserted between the turn-off of either switch and the turn-on of the complementary one, where both switches are in the OFF-state, is essential to achieve soft- switching. Its value must be larger than the time T T needed for the rail-to-rail swing of the half bridge midpoint. This duration TT depends on the total parasitic capacitance of the half bridge midpoint, which must be completely charged or depleted and the value of the resonant tank current during the transition. With good approximation, the tank current during the transition time T T can be considered constant and equal to the “switched current” IS, i.e. the value of the tank current as the transition begins. If CHB denotes the total parasitic capacitance of the half bridge midpoint (it includes the Coss of the MOSFETs, the transformer's primary winding parasitic capacitance, plus other stray contributors), the condition for soft-switching is: Equation 3 which should be met under all operating conditions. This formula suggests that T D should be large enough to always exceed TT, especially with maximum Vin and at no load, where IS is at a minimum and TT at a maximum. However, a too long deadtime may lead to the loss of soft-switching too: in fact, the tank current must not change its sign within the deadtime, which could lead to the turn-on of either MOSFET with a non-zero drain-to-source voltage or, even worse, with the body diode of the other MOSFET conducting (capacitive mode operation - see Section 9: Capacitive-mode detection function for more details). This may occur at maximum load and minimum Vin, especially when the tank circuit is designed for a low magnetizing current to optimize light load efficiency. Additionally, a too long deadtime may increase conduction losses in the body diodes and significantly limit the operating frequency of the half bridge. A good approach is to automatically adjust T D so that it tracks TT, keeping TT ≤ T D under all operating conditions. This is the objective of the adaptive deadtime function in the L6699. Figure 7 and Figure 8 show the principle schematic and its key waveforms. An edge detector (the |d/dt| block) senses that the half bridge midpoint (connected to the OUT pin) is swinging from B+ to GND or vice versa through the VBOOT pin, which moves exactly following the OUT pin (due to Cboot there is a DC voltage difference between them). The output of the |d/dt| block is high as long as the OUT pin is swinging and, as the transition is completed, the output goes low. A monostable circuit, sensitive to negative-going edges, releases a pulse that marks the end of the deadtime. D S HB T TVinI C=T ≤
There are three contributors to TD:
- The turn-off delay tOFF of the Power MOSFET, which depends on the input characteristics of the specific MOSFET and the speed its gate is driven
- The transition time TT the half bridge midpoint takes for a rail-to-rail swing
- The detection time tdet that elapses from the end of the half bridge midpoint swing to the gate-drive signal of the other MOSFET going high; this includes the detection time as well as the propagation delay along the downstream logic circuitry up to the driver output. It is important to point out that the value of T D_MIN specified in the electrical characteristics is essentially tdet: therefore the minimum observable TD is always longer. TD_MAX, on the other hand, is counted starting from the negative-going edge of the gate-drive signal, so it actually fixes a maximum limit for T D: TD ≤ T D_MAX. Finally, it is worth stating that the adaptive deadtime function does not significantly increase efficiency by itself. It is a degree of freedom that must be exploited for this purpose when designing the resonant tank. Essentially, it allows the use of a higher magnetizing inductance in the transformer, which minimizes the magnetizing current and, then, the conduction losses associated to it. Additionally, this may reduce the switched current I S to the minimum required to achieve soft-switching, therefore reducing turn-off switching losses in MOSFETs. Efficiency at medium and light load greatly benefits from this optimization.
6.3 Safe-start procedure
In the L6699 a new startup procedure, termed “safe-start”, has been implemented to prevent loss of soft-switching during the initial switching cycles, which is not 100% guaranteed by the usual soft-start procedure. Sweeping the operating frequency from an initial high value, that should not exceed 300 kHz, down to the point where the control loop takes over, which is commonly referred to as soft-start, has a twofold benefit. On the one hand, since the deliverable power depends inversely on frequency, it progressively increases the converter's power capability, therefore avoiding excessive inrush current. On the other hand, it makes the converter initially work at frequencies higher than the upper resonance frequency of the LLC tank circuit, which ensures inductive-mode operation (i.e. with the tank current lagging the square wave voltage generated by the half bridge) and, therefore, soft-switching. However, the last statement is true under a quasi-static approximation, i.e. when the operating point of the resonant tank is slowly varying around a steady-state condition. This approximation is not correct during the very first switching cycles of the half bridge, where the initial conditions of the tank circuit can be away from those under steady-state. Therefore, hard-switching is possible during the transient period needed to reach the slowly varying steady-state condition dictated by the soft-start action. A non-zero initial voltage on the resonant capacitor Cr and transformer flux imbalance during the previously mentioned transient period are the possible causes of hard-switching in the initial cycles. In high voltage half bridge controllers it is customary to start the switching activity by turning on the low-side MOSFET for a preset time to pre-charge the bootstrap capacitor (see Section 12: Bootstrap section) and ensure proper driving of the high-side MOSFET from the first cycle. In traditional controllers, normal switching starts right at the end of the pre-charge time, as shown in the left-hand image in Figure 10.
7 Operation at no load or very light load
consumption from achieving very low values anyhow. facilitating the converter to comply with energy saving specifications. unbalance in the transformer are minimized. input voltage range (e.g. when there is a PFC front-end). Figure 14. Narrow input voltage range Figure 15. Wide input voltage range
8 Current sensing, OCP and OLP
- Primary overcurrent protection (OCP function).
- Hard-switching cycles prevention at startup (see
Section 6.3: Safe-start procedure).
- Capacitive-mode detection during operation (see Section 9: Capacitive-mode detection
In this section the discussion is concentrated on the OCP function. Figure 18 and 19 a couple of current sensing methods are illustrated. ns) hard-switching under the above mentioned conditions becomes very likely. Figure 18. Current sensing techniques Figure 19. Current sensing techniques
Current sensing, OCP and OLP L6699 26/38 Doc ID 022835 Rev 2 therefore providing the system with immunity to short duration phenomena. If, instead, TSH is exceeded, an overload protection (OLP) procedure is activated that shuts down the L6699 and, in case of continuous overload/short-circuit, results in continuous intermittent operation with a user-defined duty cycle. This function is realized on pin 2 (DELAY), with a capacitor C Delay and a parallel resistor RDelay connected to ground. As the voltage on the ISEN pin exceeds 0.8 V, the first OCP comparator, in addition to turning on the switch that discharges CSS, turns on a current generator that sources 350 µA for 50 µs from the DELAY pin and charges CDelay. During an overload/short-circuit the OCP comparator and the internal current source is repeatedly activated and C Delay is charged with an average current depending essentially on CSS, RSS, the characteristics of the resonant circuit, and the short-circuit impedance; the discharge due to R Delay is negligible because the associated time constant is typically much longer. This operation continues until the voltage on CDelay, V(DELAY), reaches 2 V, which defines the time TSH, or until the overload/short-circuit disappears, whichever occurs first. There is not a simple relationship that links TSH to CDelay, so it is more practical to determine CDelay experimentally. As a rough indication, using 1 µF for CDelay, TSH should be around 100 ms in case of a dead short on the output. In the case of an overload lasting less than TSH, CDelay is no longer charged, so its voltage decays with the time constant CDelay·RDelay. Note that the value of TSH for the next overload is shorter if this occurs before CDelay is totally discharged. If, on the other hand, it is charged up to 2 V, the internal switch that discharges CSS is continuously turned on, the PFC_STOP pin is pulled low, and the 350 µA current source is forced continuously on until V(DELAY) reaches 3.5 V. This phase lasts: Equation 10 with T MP expressed in ms and CDelay in µF . During this time the L6699 runs at a frequency close to fstart (see Section 6.3: Safe-start procedure) to minimize the energy inside the resonant circuit. As V(DELAY) equals 3.5 V, the L6699 stops switching and the internal 350 µA generator is turned off, so that C Delay is slowly discharged by RDelay. The IC restarts when V(DELAY) falls below 0.3 V, which takes: Equation 11 The timing diagram of Figure 20 shows this operation. Note that if during TSTOP the supply voltage of the L6699 (VCC) falls below the UVLO threshold the IC records the event and does not restart immediately after VCC exceeds the startup threshold, if V(DELAY) is still higher than 0.3 V. Also the PFC_STOP pin stays low as long as V(DELAY) is greater than 0.3 V . De layMP C ·3.4T ≈ DelayDelayDelayDelaySTOP C ·R · 4.2ln ·C ·R=T 33.0 5.3 ≈
Figure 20. Soft-start and delayed shutdown upon overcurrent timing diagram (safe- restarts when V(DELAY) falls below 0.3 V.
9 Capacitive-mode detection function
order for soft-switching to occur (zero-voltage switching, ZVS at turn-on for both MOSFETs).
- Both MOSFETs feature hard-switching at turn-on, like in conventional PWM-controlled
handle this abnormal condition.
- The body diode of the MOSFET just switched off conducts current during deadtime and
diode simultaneously high during part of its recovery.
- There is an extremely high reverse dv/dt (many tens of V/ns!) experienced by the
conducting body diode at the end of its recovery with the other MOSFET turned on. a dv/dt exceeding the AMR (50 V/ns). Figure 21. Details of hard-switching transition during capacitive-mode operation
L6699 Capacitive-mode detection function Doc ID 022835 Rev 2 29/38 4. When either MOSFET is turned on, the other one can be parasitically turned on too, if the current injected through its Cgd and flowing through the gate driver's pull-down is large enough to raise the gate voltage close to the turn-on threshold This would be a lethal shoot-through condition for the half bridge leg. 5. The recovery of the body diodes generates large and energetic negative voltage spikes because of the unavoidable parasitic inductance of the PCB subject to its di/dt. These are coupled to the OUT pin and may damage the L6699. 6. There is a large common-mode EMI generation that adversely affects EMC. Resonant converters work in capacitive mode when their switching frequency falls below a critical value that depends on the loading conditions and the input-to-output voltage ratio. They are especially prone to enter capacitive-mode when the input voltage is lower than the minimum specified and/or the output is overloaded or short-circuited. Designing a converter so that it never works in capacitive-mode, even under abnormal operating conditions, is definitely possible but this may pose unacceptable design constraints in some cases. To prevent the severe drawbacks of capacitive-mode operation, while enabling a design that needs to ensure inductive-mode operation only in the specified operating range, neglecting abnormal operating conditions, the L6699 provides the capacitive-mode detection function. The IC monitors the phase relationship between the tank current circuit sensed on the ISEN pin and the voltage applied to the tank circuit by the half bridge, checking that the former lags behind the latter (inductive-mode operation). If the phase-shift approaches zero, which is indicative of impending capacitive-mode operation, the monitoring circuit activates the OCP procedure (see Section 8: Current sensing, OCP and OLP) so that the resulting frequency rise keeps the converter away from that dangerous condition. Also in this case the DELAY pin is activated, so that the OLP function, if used, is eventually tripped after a time T SH causing intermittent operation and reducing thermal stress. If the phase relationship reverses abruptly (which may happen in case of dead short at the converter's output), the L6699 is stopped immediately, the soft-start capacitor CSS is totally discharged and a new soft-start cycle is initiated after 50 µs idle time. During this idle period the PFC_STOP pin is pulled low to stop the PFC stage as well.
Line sensing function L6699 30/38 Doc ID 022835 Rev 2
10 Line sensing function
This function basically stops the IC as the input voltage to the converter falls below the specified range and lets it restart as the voltage goes back within the range. The sensed voltage can be either the rectified and filtered mains voltage, in which case the function acts as a brownout protection, or, in systems with a PFC pre-regulator front-end, the output voltage of the PFC stage, in which case the function serves as a power-on and power-off sequencing. L6699 shutdown upon input undervoltage is accomplished by means of an internal comparator, as shown in the block diagram of Figure 22, whose non-inverting input is available at pin 7 (LINE). The comparator is internally referenced to 1.22 V and disables the IC if the voltage applied at the LINE pin is below the internal reference. Under these conditions the soft-start is discharged, the PFC_STOP pin is open and the consumption of the IC is reduced. PWM operation is re-enabled as the voltage on the pin is above the reference. The comparator is provided with current hysteresis instead of a more usual voltage hysteresis: an internal 13 µA current sink is ON as long as the voltage applied at the LINE pin is below the reference and is OFF if the voltage is above the reference. This approach provides an additional degree of freedom: it is possible to set the ON threshold and the OFF threshold separately by properly choosing the resistors of the external divider (see below). With voltage hysteresis, on the other hand, fixing one threshold automatically fixes the other one depending on the built-in hysteresis of the comparator. With reference to Figure 22, the following relationships can be established for the ON (VinON) and OFF (VinOFF) thresholds of the input voltage: Equation 12 which, solved for RH and RL, yields: Equation 13 LH OFF L H ON R 25.1= R 25.1Vin; R 25.1+10 ·13= R 25.1Vin - - - 25.1Vin 25.1R=R; 10 · 13 VinVin=R OFF HL6 OFFON H
11 Latched shutdown
The L6699 is equipped with a comparator having the non-inverting input externally available on pin 8 (DIS) and with the inverting input internally referenced to 1.85 V. As the voltage on the pin exceeds the internal threshold, the IC is immediately shut down, the PFC_STOP pin is asserted low and the quiescent consumption reduced to a low value. The information is latched and it is necessary to let the voltage on the V CC pin go below the UVLO threshold to reset the latch, de-assert the pin PFC_STOP , and restart the IC. This function is useful to implement a latched overtemperature protection very easily by biasing the pin with a divider from an external reference voltage (e.g. pin 4, RFmin), where the upper resistor is an NTC physically located close to a heating element like the MOSFET, or a secondary diode or the transformer. An OVP can be implemented as well, e.g. by sensing the output voltage and transferring an overvoltage condition via an optocoupler. A latch-mode OCP protection can be implemented by connecting this pin to DELAY (pin 2).
12 Bootstrap section
The supply of the floating high-side section is obtained by means of a bootstrap circuitry. This solution normally requires a high voltage fast-recovery diode (D BOOT, Figure 23) to charge the bootstrap capacitor CBOOT. In the L6699 a patented integrated structure, replaces this external diode. It is realized by means of a high voltage DMOS, working in the third quadrant and driven synchronously with the low-side driver (LVG), with a diode in series to the source, as shown in Figure 24. The diode prevents that any current can flow from the VBOOT pin back to VCC if the supply is quickly turned off when the internal capacitor of the pump is not fully discharged. To drive the synchronous DMOS, a voltage higher than the supply voltage V CC is necessary. This voltage is obtained by means of an internal charge pump (Figure 24). The bootstrap structure introduces a voltage drop while recharging CBOOT (i.e. when the low side driver is on), which increases with the operating frequency and with the size of the external Power MOSFET. It is the sum of the drop across the R DS(on) and the forward drop across the series diode. At low frequency this drop is very small and can be neglected but, as the operating frequency increases, it must be taken into account. In fact, the drop reduces the amplitude of the driving signal and can significantly increase the R DS(on) of the external high-side MOSFET and then its conductive loss.
Figure 25. SO16N dimensions
Figure 26. Package drawing
Figure 27. Recommended footprint (dimensions are in mm)
Table 7. Document revision history 12-Apr-2012 1 Initial release. 16-Jan-2013 2 Updated T able 2: Absolute maximum ratings on page 5.