L6660

L6660 STMICROELECTRONICS | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 9

Technical content

4.5 TO 13.2V OPERATIVE VOLTAGE ±25 TO ±35V OUTPUT VOLTAGE RANGE SELECTABLE BY EXTERNAL RESISTORS FULL-WAVE RESONANT DC-DC CON- VERTER USING SINGLE COIL FOR DUAL HIGH VOLTAGE GENERATOR WITH OUT- PUT SLEW RATE CONTROL AND SELF CURRENT LIMITING FOR LOW EMI ±35V OR 0/+70V OPERATIVE VOLTAGE DRIVING CONFIGURATION MODES: 1. SINGLE ENDED VOLTAGE MODE 2. DIFFERENTIAL VOLTAGE MODE 3. SINGLE ENDED CHARGE MODE DOUBLE OPERATIONAL AMPLIFIERS WITH 500KHZ GAIN BANDWIDTH PRODUCT AND LOAD DRIVING CAPABILITY FROM 0.4nF UP TO 24nF ANALOG VOLTAGE SHIFTING CIRCUITRY INTERNAL 2.5V VOLTAGE REFERENCE POWER SAVING SLEEP MODE USER SPECIFIED INPUT REFERENCE (2.25V DC)

DESCRIPTION

The L6660 is a piezoelectric actuator driver. This is preliminary information on a new product now in development. Details are subject to change without notice. December 2000 HVM -35V V512 +35V Rfdb1 Rfdb2 HVP=VrefIN(1+Rfdb1/Rfdb2) From DAC OUTPUT 2.2nF47µH 220nF 68nF 220nF 47nF Rs V5/12 1 K 1 K HVP HVM 1 K 1 K HVP HVM B A Internal Current Bias DC-DC LOGICBack-Up Oscill. [12] GND-A [21] Vfdb [22] RCcomp [2] GND-P [3] COIL [5] OUT1-A [6] OUTK-A [23] HVM [19] OUT1-B [18] OUTK-B [24] HVP MUX Controll Logic Internal Band-gap and 2.5 reference Voltage Digital Pwr Supply Shifter Vosh=Vin-Vref SLEEP [15] WENA [17] INB(inv) [16] INB(not inv) [9] INA(not inv) [8] INA(inv) [4] AorB [1] AandB [20] V5/12AP [14] IN Vref [7] SLEEP [10] Vosh [11] Vin0-5 [13] Vref out A-GND 100nF BLOCK AND APPLICATION DIAGRAM SO24(Shrink) L6660 MILLI-ACTUATOR DRIVER PRODUCT PREVIEW

A or B. OUT1-A SLEEP OUTK-A INA(inv) INA(not inv) INB(not inv) INB(inv) OUTK-B V5/12-AP OUT1-B RC comp HVM HVP1 WENA PINCON Vin 0-5 Vref IN11 14 1312GND-A Vref OUT VOSH VFDB PIN CONNECTION SO24-SHIRINK (Top view) PIN FUNCTIONS N. Name Description 1 AandB MUX Enable (see Tab. 1). 2 GND-P Power ground. 3 COIL Coil for positive step UP and capacitor for negative charge. 4 AorB MUX command Aor B input selection (0 = A; 1 = B). 5 OUT1-A Output ampl.A. 6 OUTK-A Hi current output ampl.A. 7 SLEEP Sleep mode for stand-by condition (0=SLEEP 1=operative). 8 INA (inv) Inverting input of A-amplifier. 9 INA (not inv) Non Inverting input of A-amplifier. 10 Vosh Analog level shifter output Vin-Vref (-2.5 to +2.5 dynamic range) 11 Vin 0-5 Analog level shifter input positive voltage. 12 GND-A Analog ground. 13 V ref OUT Precise 2.5V reference voltage. 14 V ref IN Input for external reference voltage. 15 WENA Multiplexer Enable, Falling Edge sensitive. 16 INB (not inv) Non Inverting input of B-amplifier. 17 INB (inv) Inverting input of B-amplifier. 18 OUTK-B Hi current output ampl.B. 19 OUT1-B Output ampl.B. 20 V5/12-AP Analog&Power voltage supply 5 to 12V. 21 Vfdb Feedback voltage for HVP regulator. 22 RC comp DC-DC converter compensation network. 23 HVM Negative High voltage generated op. amp. supply. 24 HVP Positive High voltage generated op. amp. supply. L6660

ELECTRICAL CHARACTERISTICS

(All the following parameters are specified @ 27°C and V5/12 = 12V ±5%, unless otherwise specified.) Symbol Parameter Test Condition Min. Typ. Max. Unit V5/12 Main power supply 4.5 13.2 V HVP (1) Output positive Voltage Double Supply Voltage V512 ≥ 8 Double Supply Voltage V512 < 8 V V Single Supply Voltage V512 ≥ 8 Single Supply Voltage V512 < 8 V V HVripple HVP, HVM ripple Characterized only, Not Tested External filter cap. 100nF ILOAD = 0mA 0.8 V I, hvp Output current (see figure 1) I, hvm Top Time to operating condition 5 ms Fswitch (2) Switching Frequency Refer to Block diagram page1/10 300 kHz R ds, on Boost transistor ON resistance 4 Ω Iboost Boost transistor current limiting 850 mA Vsup Minimum OpAmp supply Voltage (HVP if externally given) Double Supply V512 V Single Supply V512 V DC gain OpAmp DC gain 130 dB GBW OpAmp Gain Bandwidth product Cload 0.4nF to 24nF Double Supply Voltage

500 KHz

DCinp OpAmp Input dynamic voltage Double supply -3.5 4.5 V Single supply 1.2 5 V V out OpAmp Output dynamic voltage Capacitive load HVM HVP V DC, Ibias OpAmp Bias supply current (both) |HVP| = |HVM| = 35V 9 mA Iout (3) OpAmp Dynamic Output Average current with external supply -75 +75 mA PSRR,P OpAmp Positive power supply rejection ratio @ 50kHz not tested in production -50 dB PSRR,N OpAmp Negative power supply rejection ratio @ 50kHz not tested in production -50 dB C load OpAmp Load capacitance range Voltage mode Gain min 20dB 0.4 24 nF C int OpAmp Integration capacitance Charge mode Gain min 20dB 0.4 24 nF K OpAmp Current ratio OUTK/OUT1 9.8 10 10.2 ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value Unit V512 Supply voltage pin 17 referred to Ground 14 V HVP Positive high voltage referred to HVM 75 V HVM Negative high voltage referred to Ground -38 V IN A&B Amplifier input voltage common mode ±6V ΔV Maximum difference between pin 20 and pins 8, 9, 16 & 17 17 V Tamb Operative Ambient Temperature -20 to +80 °C Tstg Storage Temperature -40 to +125 °C All the voltage value are referred to ground unless otherwise specified. L6660

Note 1: Selectable by external resistors. Note 2: Set by external Coil and Capacitor from 80 to 550KHz. Note 3: Take into account the total power dissipation. Figure 1. Load Regulation

input common mode dynamic range. Figure 2. Charge Mode Configuration (configuration example; the final application depends on user needs according with Electrical Characteristics). AorB (pin 4) will not change MUX state. AorB (pin 4) will not change MUX state. put stage is designed with high impedance stage.

Figure 3. Not selected driver return to Zero Output voltage. Both drivers have the same behavior. condition. The external feedback programmed for a DC gain value <30V/V.

"long time" with controlled slope see table 1. ways present even in sleep mode condition. gether VrefOUT and VrefIN (PIN13 and PIN14). put typical tranfer function is plotted in Fig. 4. For more details see the application note. ence voltage and resistor voltage divider. single supply, HVM must be connected to GND. switching and furthermore controlled rectification. output and input voltage...). output has to be connected to V5/12. tween GND and HVM must be lower than 35V. Figure 4. Shifter DC transfer function

D L C E K SSO24ME Seating Plane 0.10mm .004 DIM. mm inch A 2.00 0.079 A1 0.25 0.010 A2 1.51 2.00 0.060 0.079 C 0.10 0.35 0.004 0.014 D 8.35 9.35 0.33 0.37 E 7.60 8.70 0.30 0.34 e 0.65 0.025 k 0˚ (min), 10˚ (max) SSO24 (SHRINK) L6660

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics © 2000 STMicroelectronics – Printed in Italy – All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com L6660