L6585DE STMICROELECTRONICS | Alldatasheet
Document overview
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Technical content
Datasheet sections
- 1 Pin settings
- 1.1 Connection
- 1.2 Functions
- 2 Electrical data
- 2.1 Maximum ratings
- 3 Electrical characteristics
- 4 Device description
- 5 Application information
- 5.1 VCC section
- 5.2 PFC section
- 5.2.1 TM PFC operation
- 5.2.2 Leading edge blanking
- 5.2.3 THD optimizer feature
- 5.2.4 Over-voltage protection
- 5.2.5 Disabling the L6585DE
- 5.2.6 Feedback disconnection protection
- 5.2.7 PFC over-current protection
- 6 Ballast section
- 6.1 Half-bridge drivers and integrated bootstrap diode
- 6.2 Normal start-up description
- 6.3 Startup sequence with old or damaged lamps
- 6.4 Old lamp management during run mode
- 6.5 Rectifying effect
- 6.6 Over-current protection
- 6.7 Hard switching protection
Features
■ PFC section – transition mode PFC with over-current protection – over-voltage protection – feedback disconnection – under-voltage lockout – PFC choke saturation detection – THD optimizer ■ Half-bridge section – preheating and ignition phases independently programmable – 3 % oscillator precision – 1.2 µs dead time – programmable and precise end-of-life protection compliant with all ballast configurations – smart hard swit ching detection – fast ignition voltage control with choke saturation detection – half-bridge over-current control SO-20 Figure 1. Block diagram
1 Pin settings
1.1 Connection
Figure 2. Pin connection (top view)
1.2 Functions
Table 1. Pin functions pin fixes the switching frequency of the half-bridge for each operating state. combined with the capacitor connected to the pin OSC. frequency during preheating combined with RRUN and COSC.
Pin for setting the preheating time and protection intervention. Connect an RC parallel network (Rd and Cd) to ground. ignition phase starts and the RdCd is pulled to ground. Pin to program the EOL comparator. connecting a resistor (REOLP) to ground. Input for the window comparator. capacitor to ground” configurations. This function is blanked during the ignition phase. voltage divider and provides the sinusoidal reference to the PFC current loop. fed to the pin through a voltage divider.
11 ZCD
operation. A negative-going edge triggers PFC MOSFET turn-on. comparator, the PFC driver is triggered by means of an internal starter.
12 PFCCS
multiplier, to determine the PFC MOSFET’ s turnoff. saturation, for example) and, on this occurrence, shuts down the PFC gate. An internal LEB prevents undesired function triggering. Table 1. Pin functions (continued)
MOSFETs with a peak current of 300 mA source and 600 mA sink (typ. values).
14 HBCS
3-level half-bridge current monitor for current control. resulting voltage is applied to this pin. choke saturation), the IC latches to avoid damage to the MOSFETs.
16 LSD Low side driver output: the output stage can deliver 290 mA source and 480 mA
17 VCC Supply voltage of both the signal part of the IC and the gate driver. Clamped with a Zener inside. source of the high side power MOSFET.
19 HSD High-side driver output: the output stage can deliver 290 mA source and 480 mA
20 BOOT
a high voltage DMOS, synchronously driven with the low side power MOSFET.
2 Electrical data
2.1 Maximum ratings
2.2 Thermal data
Table 2. Absolute maximum ratings
- The device has an internal clamping Zener between G ND and the VCC pin. It must not be supplied by a
low impedance voltage source. Table 3. Thermal data
3 Electrical characteristics
Table 4. Electrical characteristics
Table 4. Electrical characteristics (continued)
- Specification over the -40 °C to 125 °C junction temperature range are ensured by design, characterization and statistical
- A pulse train has been sent to the HBCS pin with f = 6 kHz; the pulse duration is the one indicated in the notes as "TON"
L6585DE Device description
4 Device description
The L6585DE embeds a high performance PFC controller, a ballast controller and all the relevant drivers necessary to build an electronic ballast. The PFC section achieves current mode control operating in transition mode, offering a highly linear multiplier including a THD optimizer that allows for an extremely low THD, even over a large range of input voltages and loading conditions. The PFC output voltage is controlled by means of a voltage-mode error amplifier and a precise internal voltage reference. The ballast controller offers the designer a very precise oscillator, a logic that manages all the operating steps and a full set of protection features:
- Programmable end-of-life detection, compliant with both lamp-to-ground and capacitor- to-ground configurations
- Over-current protection with either current limiting or choke saturation protection
- Hard switching events detection High current capability drivers for both the PFC (300 mA source and 600 mA sink) and the half-bridge (290 mA source and 480 mA sink) also allow ballast designs for very high output power (up to 160 W).
5 Application information
Figure 3. Typical application
5.1 VCC section
guarantee the correct behavior of the internal structures. VCC to input voltage through a resistor.
5.2 PFC section
5.2.1 TM PFC operation
Figure 4. PFC section network or, more often, with a simple capacitor connected between INV and COMP pin. In Figure 5 the characteristic curves of the multiplier are reported. Figure 5. Multiplier
and high current capability that makes it compliant with a very wide range of input voltage. PFC gate driver with a repetition rate of approximately 15 kHz. waveform, a power factor correction and THD reduction is achieved.
5.2.2 Leading edge blanking
Figure 6. PFCCS waveforms
5.2.3 THD optimizer feature
zero; this reduces crossover distortion and avoids offset introduction.
5.2.4 Over-voltage protection
Two different over-voltage protections can be detected: dynamic over-voltage, usually due to fast load transition and static over-voltage, due to an excessive input voltage.
- Dynamic OVP The CTR pin is connected to high voltage rail through a voltage divider. If the voltage at this pin is above 3.4 V, the PFC gate driver is stopped until the voltage returns below the threshold. This limits the risk of choke saturation and MOSFET's damage.
- Static OVP A steady over-voltage may cause abnormal behavior in both the PFC (e.g. because input voltage is higher than PFC output voltage) and the ballast (e.g. overheating, lamp over-current, capacitive mode operating point). A steady over-voltage causes a slow transition of the COMP pin towards the low saturation (around 2.25 V). This fact is considered by the L6585DE as a static over-voltage event and a Tch cycle is started. After this cycle, if the COMP pin is saturated low the IC is latched in low consumption mode.
5.2.5 Disabling the L6585DE
the CTR pin can be used to shut down the IC without mains disconnection. When CTR is pulled below 0.75 V, the IC is stopped and the internal logic is reset. When CTR is released, the IC starts with a new preheating sequence. This function is available only if the IC is not latched due to a fault protection intervention.
5.2.6 Feedback disconnection protection
Very fast output voltage surges may damage the upper resistors of the voltage divider feeding the INV pin, causing a feedback disconnection. In this case, the E/A saturates high and the PFC gate drive turns on the MOSFET for a long time (the current sense threshold assumes its maximum value equal to 1 V) and the choke may saturate, destroying the MOSFET. The output voltage increases very fast and may reach very high value even if OVP is triggered. Feedback disconnection protection is then activated if V INV < 1.2 V and dynamic over- voltage protection is triggered.
5.2.7 PFC over-current protection
The PFC MOSFET over-current can occur in cases of PFC choke saturation or in cases of surge from the input, due to the breakdown of the MOSFET body diode. The latter case is observed together with an over-voltage of the PFC output. In both cases, the PFC stage is stopped, whereas the HB stage continues switching. The protection is not latched: once the PFCCS falls below 1.7 V, the PFC driver restarts.
6 Ballast section
6.1 Half-bridge drivers and integrated bootstrap diode
driven by means of a bootstrapped structure reducing the number of external components.
6.2 Normal start-up description
Figure 7. Normal start-up procedure
- Startup : As soon as Vcc reaches the startup threshold voltage references are built up,
RPRE and RRUN (see typical application diagram).
- Preheating: the TCH pin continues to source 31 µA until its voltage reaches 4.63 V,
value of the COSC capacitor and are depicted in Figure 10. values please refer to AN2870. Figure 10. Oscillator characteristics
6.3 Startup sequence with old or damaged lamps
regulation and a lamp voltage limiting. is pulled down and HBCS voltage is checked. If it is above 1.05 V the IC is stopped. reaches 1.9 V, the IC enters run mode and TCH pin is immediately pulled down. Figure 11. Startup procedures with old or damaged lamps
6.4 Old lamp management during run mode
- Rectifying effect
- Over-current
- Hard switching event
6.5 Rectifying effect
that can be triggered by a voltage variation due to rectifying effect.
- VUP = VREF + VZ2 + VF1 + W/2
- VDOWN = VREF – (VZ1 + VF2) – W/2
- VUP = - VDOWN
- 2 VREF = VZ1 − VZ2 Where VUP and VDOWN are the maximum allowed values of VK The tracking configuration (see Figure 13) is useful when the lamp is connected between choke and blocking capacitor in the block capacitor-to-ground configuration. In this configuration the voltage across the blocking capacitor is affected by the voltage ripple superimposed on the PFC output. Using a reference affected by the same ripple helps to reject it and avoid premature triggering of the comparator. As soon as the comparator is triggered, a Tch cycle starts in order to improve the noise immunity.
Table 5. EOL window comparator configuration table
Figure 12. End-of-life protection in lamp-to-ground configuration
Figure 13. End-of-life protection in bl ocking capacitor-to-ground configuration
6.6 Over-current protection
Figure 14. Resonance curve modification due to lamp ageing respectively 1.05 V and 0.82 V.
6.7 Hard switching protection
risk of working below the resonance frequency (capacitive mode). counter that shuts down the IC if 350 (typ.) subsequent spikes are detected. This protection is blanked both during preheating and ignition.
6.8 Choke saturation protection
Figure 15. Example of capacitive mode operation due to ballast choke saturation switching events (typical duration between 40 ns and 100 ns) cannot trigger the comparator. switching protection will be activated after around 420 events. will certainly be activated at the first event.
Figure 16. Half-bridge current sense pulse detection areas
Table 6. Table of faults
2.25 V IC is latched
7 Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark.
Figure 17. Package dimensions Table 7. SO-20 mechanical data
8 Ordering information
Table 8. Order codes
9 Revision history
Table 9. Document revision history