L6566A STMICROELECTRONICS | Alldatasheet
Document overview
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- PDF pages: 51
Technical content
Datasheet sections
- 1 Description
- 2 Pin settings
- 2.1 Connections
- 2.2 Pin description
- 3 Electrical data
- 3.1 Maximum rating
- 3.2 Thermal data
- 4 Electrical characteristi cs
- 5 Application information
- 5.1 High-voltage start-up generator
- 5.2 Zero current detection and triggering block; oscillator block
- 5.3 Burst-mode operation at no load or very light load
- 5.4 Adaptive UVLO
- 5.5 PWM control block
- 5.6 PWM comparator, PWM latch and voltage feedforward blocks
- 5.7 Hiccup-mode OCP
- 5.8 PFC interface
- 5.9 Latched disable function
- 5.10 Soft-start and delayed latched shutdown upon overcurrent
- 5.11 OVP block
- 5.12 Brownout protection
- 5.13 Slope compensation
- 5.14 Summary of L6566A power management functions
Features
■ Selectable multi-mode operation: fixed frequency or quasi-resonant ■ On-board 700 V high-voltage start-up ■ Advanced light load management ■ Low quiescent current (< 3 mA) ■ Adaptive UVLO ■ Line feedforward for constant power capability vs. mains voltage ■ Pulse-by-pulse OCP, shutdown on overload (latched or autorestart) ■ Transformer saturation detection ■ Switched supply rail for PFC controller ■ Latched or autorestart OVP ■ Brownout protection ■ -600/+800 mA totem pole gate driver with active pull-down during UVLO ■ SO16N package
Applications
■ Notebook, TV &LCD monitors adapters ■ High power chargers ■ PDP/LCD TV ■ Consumer appliances, like DVD, VCR, set-top box ■ IT equipment, games, aux. power supplies ■ Power supplies in excess of 150 W SO16N Figure 1. Block diagram
1 Description
The L6566A is an extremely versatile current-mode primary controller IC specifically designed for high-performance offline flyback converters operated from front-end Power Factor Correction (PFC) stages in applications supposed to comply with EN61000-3-2 or JEITA-MITI regulations. Both Fixed-frequency (FF) and Quasi-resonant (QR) operation are supported. The user can pick either of the two depending on application needs. The device features an externally programmable oscillator: it defines converter's switching frequency in FF mode and the maximum allowed switching frequency in QR mode. When FF operation is selected, the IC works like a standard current-mode controller with a maximum duty cycle limited at 70% min. QR operation, when selected, occurs and is achieved through a transformer demagnetization sensing input that triggers MOSFET's turn-on. Under some conditions, ZVS (Zero-voltage Switching) can be achieved. Converter's power capability rise with the input voltage is compensated by line voltage feedforward. At medium and light load, as the QR operating frequency equals the oscillator frequency, a function (valley skipping) is activated to prevent further frequency rise and keep the operation as close to ZVS as possible. With either FF or QR operation, at very light load the IC enters a controlled burst-mode operation that, along with the built-in non-dissipative high-voltage start-up circuit and a reduced quiescent current, helps keep low the consumption from the mains and meet energy saving recommendations. To allow meeting them in two-stage power-factor-corrected systems as well, the L6566A provides an interface with the PFC controller that enables to turn off the pre-regulator at light load. An innovative adaptive UVLO helps minimize the issues related to the fluctuations of the self-supply voltage due to transformer's parasitics. The protection functions included in this device are: not-latched input undervoltage (brownout), output OVP (auto-restart or latch-mode selectable), a first-level OCP with delayed shutdown to protect the system during overload or short circuit conditions (auto- restart or latch-mode selectable) and a second-level OCP that is invoked when the transformer saturates or the secondary diode fails short. A latched disable input allows easy implementation of OTP with an external NTC, while an internal thermal shutdown prevents IC overheating. Programmable soft-start, leading-edge blanking on the current sense input for greater noise immunity, slope compensation (in FF mode only), and a shutdown function for externally controlled burst-mode operation or remote ON/OFF control complete the equipment of this device.
Figure 2. Typical system block diagram energy saving specifications.
2 Pin settings
2.1 Connections
Figure 3. Pin connection (through top view)
2.2 Pin description
Table 2. Pin functions the UVLO threshold to allow a faster restart. this pin and kept separate from any pulsed current return. and IGBT’s with a peak current capability of 800 mA source/sink.
voltage for the signal part of the IC. used, the pin will be left floating. improves sensitivity to temporary disturbances. description).Bypass the pin with a capacitor to GND (pin 3) to reduce noise pick-up. Ground the pin if the function is not used. is pulled below 1.4V the IC will shut down.
10 VREF
Table 2. Pin functions (continued)
11 ZCD
strobed and digitally filtered to increase noise immunity.
12 MODE/SC
maximum allowed operating frequency.
13 OSC
detecting an overload condition (OLP).
15 VFF
pulse-by-pulse current limitation (the higher the voltage, the lower the setpoint).
16 AC_OK
3 Electrical data
3.1 Maximum rating
3.2 Thermal data
Table 3. Absolute maximum ratings Table 4. Thermal data
4 Electrical characteristics
unless otherwise specified). Table 5. Electrical characteristics
Table 5. Electrical characteristics (continued)
- Parameters tracking one another.
- See Table 6 on page 41 and Table 7 on page 42
- The Voltage Feedforward block output is given by:
5 Application information
operation, selectable with the pin MODE/SC (12): forcing the voltage on the pin over 3V (e.g. operation, otherwise the device will be FF-operated.
- QR mode at heavy load. Quasi-resonant ope ration lies in synchronizing MOSFET's
main benefits of this kind of operation.
- Valley-skipping mode at medium/ light load. The externally programmable oscillator of
- Burst-mode with no or very light load. When the load is extremely light or disconnected,
the converter will enter a controlled on/off operation with constant peak current. very low, no issue of audible noise arises. Figure 4. Multi-mode operation with QR option active
- FF mode from heavy to light load. The system operates exactly like a standard current
continuous to discontinuous operation mode of the transformer.
- Burst-mode with no or very light load. This kind of operation is activated in the same
way and results in the same behavior as previously described for QR operation. JEITA-MITI regulations. Pin 6 (Vcc_PFC) provides the supply voltage to the PFC control IC.
5.1 High-voltage start-up generator
Figure 5 shows the internal schematic of the high-voltage start-up generator (HV generator). with a temperature-compensated current generator connected to its source. Figure 5. High-voltage start-up generator: internal schematic
ground and makes its voltage rise almost linearly. Figure 6. Timing diagram: normal power-up and power-down sequences compared to a standard start-up circuit made with external dropping resistors. protection (see the relevant section) is not used. page 20, and that the converter will work safely with extremely low power throughput.
5.2 Zero current detection and tr iggering block; oscillator block
triggering block must be previously armed by a positive-going edge exceeding 100 mV. demagnetization from triggering the ZCD circuit erroneously. frequency will be prevented from exceeding fosc. Figure 9. Drain ringing cy cle skipping as the load is gradually reduced
Application information L6566A Note: When the system operates in valley skipping-mode, uneven switching cycles may be observed under some line/load conditions, due to the fact that the OFF-time of the MOSFET is allowed to change with discrete steps of one ringing cycle, while the OFF-time needed for cycle-by-cycle energy balance may fall in between. Thus one or more longer switching cycles will be compensated by one or more shorter cycles and vice versa. However, this mechanism is absolutely normal and there is no appreciable effect on the performance of the converter or on its output voltage. If the MOSFET is enabled to turn on but the amplitude of the signal on the ZCD pin is smaller than the arming threshold for some reason (e.g. a heavy damping of drain oscillations, like in some single-stage PFC topologies, or when a turn-off snubber is used), MOSFET’s turn-on cannot be triggered. This case is identical to what happens at start-up: at the end of the next oscillator cycle the MOSFET will be turned on, and a new switching cycle will take place after skipping no more than one oscillator cycle. The operation described so far does not consider the blanking time T BLANK after MOSFET’s turn off, and actually TBLANK does not come into play as long as the following condition is met: Equation 3 where D is the MOSFET duty cycle. If this condition is not met, things do not change substantially: the time during which MOSFET’s turn-on is inhibited is extended beyond Tosc by a fraction of TBLANK. As a consequence, the maximum switching frequency will be a little lower than the programmed value fosc and valley-skipping mode may take place slightly earlier than expected. However this is quite unusual: setting fosc = 150 kHz, the phenomenon can be observed at duty cycles higher than 60%. See Section 5.11: OVP block on page 35 for further implications of TBLANK. If the voltage on the COMP pin (9) saturates high, which reveals an open control loop, an internal pull-up keeps the ZCD pin close to 2V during MOSFET's OFF-time to prevent noise from false triggering the detection block. When this pull-up is active, the ZCD pin might not be able to go below the triggering threshold, which would stop the converter. To allow auto- restart operation, however ensuring minimum operating frequency in these conditions, the oscillator frequency that retriggers MOSFET's turn-on is that of the external oscillator divided by 128. Additionally, to prevent malfunction at converter's start-up, the pull-up is disabled during the initial soft-start (see the relevant section). However, to ensure a correct start-up, at the end of the soft-start phase the output voltage of the converter must meet the condition: Equation 4 where Ns is the turn number of the secondary winding, Naux the turn number of the auxiliary winding and I ZCD the maximum pull-up current (130 µA). osc BLANK T T1D −≤ ZCD1Z IRNaux NsVout >
illustrated in the timing diagrams of Figure 10. Section 5.11: OVP block on page 35). Figure 10. Operation of ZCD, triggering and Oscillator blocks (QR option active)
5.3 Burst-mode operation at no load or very light load
others previously described, is noise-free since the peak current is low. sense resistor must be determined taking this offset into account. Figure 11. Load-dependent operating modes: timing diagrams
Figure 12. Addition of an offset to the current sense lowers the burst-mode operation
5.4 Adaptive UVLO
generating a voltage not exceeding the maximum allowed by the control IC at full load. ensures that at full load the MOSFET will be driven with a proper gate-to-source voltage. Figure 13. Adaptive UVLO block
5.5 PWM control block
Figure 14, left-hand side circuit). Figure 14. Possible feedback configurations that can be used with the L6566A
5 Vcc
Figure 15. Externally controlled burst-mode operation by driving pin COMP: timing
5.6 PWM comparator, PWM latch and voltage feedforward blocks
might result from the noise generated ("double-pulse suppression"). of Vcsx, thereby, determines the overcurrent setpoint along with the sense resistor Rs. voltage at maximum mains voltage can be even twice the value at minimum mains voltage. The L6566A has the Line Feedforward function available to solve this issue.
no more than a couple of iterations. the pin can be also biased at a fixed voltage using a divider from VREF (pin 10). Figure 17. Left: Overcurrent setpoint vs. VFF volt age; right: Line Feedforward function block
Application information L6566A where Lp is the inductance of the primary winding. In case a constant maximum power capability vs. the input voltage is not required, the VFF pin can be grounded, directly or through a resistor (see Section 5.11: OVP block on page 35 ), hence fixing the overcurrent setpoint at 1V, or biased at a fixed voltage through a divider from VREF to get a lower setpoint. It is possible to bypass the pin to ground with a small film capacitor (e.g. 1-10 nF) to ensure a clean operation of the IC even in a noisy environment. The pin is internally forced to ground during UVLO, after activating any latched protection and when pin COMP is pulled below its low clamp voltage (see Section 5.5: PWM control block on page 26 ).
5.7 Hiccup-mode OCP
A third comparator senses the voltage on the current sense input and shuts down the device if the voltage on the pin exceeds 1.5 V, a level well above that of the maximum overcurrent setpoint (1V). Such an anomalous condition is typically generated by either a short circuit of the secondary rectifier or a shorted secondary winding or a hard-saturated flyback transformer. To distinguish an actual malfunction from a disturbance (e.g. induced during ESD tests), the first time the comparator is tripped the protection circuit enters a “warning state”. If in the next switching cycle the comparator is not tripped, a temporary disturbance is assumed and the protection logic will be reset in its idle state; if the comparator will be tripped again a real malfunction is assumed and the L6566A will be stopped. Depending on the time relationship between the detected event and the oscillator, occasionally the device could stop after the third detection. This condition is latched as long as the device is supplied. While it is disabled, however, no energy is coming from the self-supply circuit; hence the voltage on the Vcc capacitor will decay and cross the UVLO threshold after some time, which clears the latch. The internal start-up generator is still off, then the Vcc voltage still needs to go below its restart voltage before the Vcc capacitor is charged again and the device restarted. Ultimately, this will result in a low-frequency intermittent operation (Hiccup-mode operation), with very low stress on the power circuit. This special condition is illustrated in the timing diagram of Figure 18.
Figure 18. Hiccup-mode OCP: timing diagram
5.8 PFC interface
precedes the isolated DC-DC converter.
Figure 19. Possible interfaces between the L6566A and a PFC controller occurs at light load (see Section 5.4: Adaptive UVLO on page 25).
5.9 Latched disable function
consumption reduced to a low value. operation is shown in the timing diagram of Figure 20. (e.g. 1-10 nF) to prevent any malfunctioning of this kind.
Figure 20. Operation after latched disable activation: timing diagram
5.10 Soft-start and delayed latc hed shutdown upon overcurrent
charged by an internal current generator, ISS1, from zero up to about 2V where it is clamped.
5.11 OVP block
Table 8 on page 45) for additional hints. Figure 22. OVP Function: internal block diagram
Figure 23. OVP function: timing diagram page 21 for additional details.
5.12 Brownout protection
mains voltage falls below the minimum specification of normal operation. the output voltage not to decay to zero monotonically. device shuts down, with the soft-start capacitor discharged and the gate-drive output low. Figure 25. Brownout protection: internal block diagram and timing diagram
the pin has to be connected to Vcc through a resistor (220 to 680 kΩ).
5.13 Slope compensation
continuous conduction mode with a duty cycle close to or exceeding 50%. Figure 27. Slope compensation waveforms programming resistor is needed to ensure a clean operation at light loads. If slope compensation is not required with FF operation, the pin shall be left floating.
5.14 Summary of L6566A power management functions
used as a sort of quick troubleshooting guide. Table 6. L6566A light load management features
Table 7. L6566A protections
- Use One external diode from V FF (#15) to AC_OK (#16), cathode to AC_OK
- Use one external diode from SS (#14) to V REF (#10), cathode to VREF
- If C ss and the Vcc capacitor are such that Vcc falls below UVLO before latch tripping (Figure 21 on page 34)
- If C ss and the Vcc capacitor are such that the latch is tripped before Vcc falls below UVLO (Figure 21 on page 34)
- Discharged to zero by V cc going below UVLO
6 Application examples and ideas
Figure 28. Typical low-cost application schematic Figure 29. Typical full-feature app lication schematic (QR operation)
Figure 30. Typical full-feature a pplication schematic (FF operation) Table 8. External circuits that determine IC behavior upon OVP and OCP
Figure 31. Frequency foldback at light load (FF operation) Figure 32. Latched shutdown upon mains overvoltage
15 L6566A8 VFF
7 Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
Figure 33. Package dimensions Table 9. SO16N mechanical data
8 Order codes
Table 10. Order codes
9 Revision history
Table 11. Document revision history