L6565 STMICROELECTRONICS | Alldatasheet
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Technical content
■ QUASI-RESONANT (QR) ZERO-VOLTAGE- SWITCHING (ZVS) TOPOLOGY ■ LINE FEED FORWARD TO DELIVER CONSTANT POWER vs. MAINS CHANGE ■ FREQUENCY FOLDBACK FOR OPTIMUM STANDBY EFFICIENCY ■ PULSE-BY-PULSE & HICCUP-MODE OCP ■ ULTRA-LOW START-UP (< 70µA) AND QUIESCENT CURRENT (< 3.5mA) ■ DISABLE FUNCTION (ON/OFF CONTROL) ■ 1% PRECISION (@ T j = 25°C) INTERNAL REFERENCE VOLTAGE ■ ±400mA TOTEM POLE GATE DRIVER WITH UVLO PULL-DOWN ■ BLUE ANGEL, ENERGY STAR, ENERGY
2000 COMPLIANT
APPLICATIONS
■ TV/MONITOR SMPS ■ AC-DC ADAPTERS/CHARGERS ■ DIGITAL CONSUMER ■ PRINTERS, FAX MACHINES, PHOTOCOPIERS AND SCANNERS
DESCRIPTION
The L6565 is a current-mode primary controller IC, specifically designed to build offline Quasi-resonant ZVS (Zero Voltage Switching at switch turn-on) fly- back converters. Quasi-resonant operation is achieved by means of a transformer demagnetization sensing input that trig- gers MOSFET's turn-on. DIP8(Minidip) SO-8 ORDERING NUMBERS: L6565N L6565D QUASI-RESONANT SMPS CONTROLLER BLOCK DIAGRAM VREF2 VOLTAGE REGULATOR INTERNAL SUPPLY 2.5V DRIVER ZERO CURRENT DETECTOR 2.1V 1.6V VCC8 ZCD VCC INV COMP VFF CS GD GND 20V 40K 5pF BLANKING LINE VOLTAGE FEEDFORWARD Hiccup-mode OCP DISABLE R S Q STARTER 2 V Hiccup-mode OCP Starter STOP Q UVLO Blanking START
DESCRIPTION (continued) Converter's power capability variations with the mains voltage are compensated by line voltage feedforward. At light load the device features a special function that automatically lowers the operating frequency still main- taining the operation as close to ZVS as possible. In addition to very low start-up and quiescent currents, this feature helps keep low the consumption from the mains at light load and be Blue Angel and Energy Star com- pliant. The IC includes also a disable function, an on-chip filter on current sense, an error amplifier with a precise ref- erence voltage for primary regulation and an effective two-level overcurrent protection. PIN CONNECTION (Top view, Minidip and SO8) PIN DESCRIPTION N° Name Function 1 INV Inverting input of the error amplifier. The information on the output voltage is fed into the pin through either a resistor divider (primary regulation) or an optocoupler (secondary feedback). This pin can be grounded in some secondary feedback schemes (see pin 2). 2 COMP Output of the error amplifier. Typically, a compensation network is placed between this pin and the INV pin to achieve stability and good dynamic performance of the voltage control loop. With secondary feedback, the pin can be also driven directly by an optocoupler to control PWM by modulating the current sunk from the pin (with the INV pin grounded). 3 VFF Line voltage feedforward. The information on the converter’s input voltage is fed into the pin through a resistor divider and is used to change the setpoint of the pulse-by-pulse current limitation (the higher the voltage, the lower the setpoint). If this function is not desired the pin will be grounded and the current limitation setpoint will be maximum. 4 CS Input to the PWM comparator. The primary current is sensed through a resistor, the resulting voltage is applied to this pin and compared with an internal reference to determine MOSFET’s turn-off. The internal reference is clamped at a value, which defines the pulse-by-pulse current limitation setpoint, depending on the voltage at pin VFF . If the signal at the pin CS exceeds 2 V, the gate driver will be disabled (Hiccup-mode OCP). 5 ZCD Transformer’s demagnetization sensing input for Quasi-Resonant operation. Alternately, synchronization input for an external signal. A negative-going edge triggers MOSFET’s turn-on. The trigger circuit is blanked for a minimum of 3.5 µs after MOSFET turn-off, for safe operation under short circuit conditions and frequency foldback. If the pin is grounded the IC will be disabled. 6 GND Ground. Current return for both the signal part of the IC and the gate driver. 7 GD Gate driver output. The totem pole output stage is able to drive power MOSFET’s and IGBT’s with a peak current of 400 mA (source and sink). 8 Vcc Supply Voltage of both the signal part of the IC and the gate driver. An electrolytic capacitor is connected between this pin and ground. A resistor connected from this pin to the converter’s input bulk capacitor will be typically used to start up the device. ZCD INV COMP VFF CS Vcc GD GND
Symbol Parameter SO8 Minidip Unit R th j-amb Max. Thermal Resistance, Junction-to-ambient 150 100 °C/W Symbol Pin Parameter Value Unit IVcc 8I CC + IZ 30 mA IGD 7 Output Totem Pole Peak Current (2 µs) ±700 mA INV, COMP , VFF , CS 1, 2, 3 4 Analog Inputs & Outputs -0.3 to 7 V IZCD 5 Zero Current Detector 50 (source) -10 (sink) mA Ptot Power Dissipation @Tamb = 50°C (Minidip) (SO8) 0.65 W Tj Junction Temperature Operating range -40 to 150 °C Tstg Storage Temperature -55 to 150 °C ELECTRICAL CHARACTERISTCS (Tj = -25 to 125°C, VCC = 12V, Co = 1nF; unless otherwise specified) Symbol Parameter Test Condition Min. Typ. Max. Unit SUPPLY VOLTAGE Vcc Operating range After turn-on 10.3 18 VCCOn Turn-on threshold 12.5 13.5 14.5 V VCCOff Turn-off threshold 8.7 9.5 10.3 V Hys Hysteresis 3.65 4 4.3 V VZ Zener Voltage I cc = 25 mA 18 20 22 V SUPPLY CURRENT Istart-up Start-up Current Before turn-on, VCC = 12V 45 70 µA Iq Quiescent Current After turn-on 2.3 3.5 mA ICC Operating Supply Current @ 70 kHz 3.5 5 mA Iq Quiescent Current During Hiccup-mode OCP 1.6 3.5 mA Iq Quiescent Current V ZCD < VDIS, VCC >VCCOff 1.4 2.1 mA LINE FEEDFORWARD IVFF Input Bias Current V VFF = 0 to 3 V -1 µA VVFF Operating Range 0 to 3 V K Gain VVFF = 1.5V , VCOMP = 4V 0.16 ERROR AMPLIFIER VINV Voltage Feedback Input Threshold Tamb = 25°C 2.465 2.5 2.535 V 12V < VCC < 18V 2.44 2.56 Line Regulation Vcc = 12 to 18V 2 5 mV IINV Input Bias Current -0.1 -1 µA
G V Voltage Gain Open loop 60 80 dB GB Gain-Bandwidth Product 1 MHz ICOMP Source Current V COMP = 4V, VINV = 2.4 V -2 -3.5 -5 mA Sink Current V COMP = 4V, VINV = 2.6 V 2.5 4.5 mA VCOMP Upper Clamp Voltage I SOURCE = 0.5 mA 5 5.5 V Lower Clamp Voltage I SINK = 0.5 mA 2.25 2.55 V CURRENT SENSE COMPARATOR ICS Input Bias Current V CS = 0 -0.05 -1 µA td(H-L) Delay to Output 200 450 ns VCSx Current Sense Reference ClampVCOMP = Upper clamp, VVFF = 0V 1.28 1.4 1.5 V VCOMP = Upper clamp, VVFF = 1.5V 0.62 0.7 0.78 VCOMP = Upper clamp, VVFF = 3V 00 . 2 VCSdis Hiccup-mode OCP level 1.85 2.0 2.2 V ZERO CURRENT DETECTOR/ SYNCHRONIZATION VZCDH Upper Clamp Voltage I ZCD = 3mA 4.7 5.2 6.1 V VZCDL Lower Clamp Voltage I ZCD = - 3mA 0.3 0.65 1 V VZCDA Arming Voltage (positive-going edge) (1) 2.1 V VZCDT Triggering Voltage (negative-going edge) 1.6 V IZCDb Input Bias Current V ZCD = 1 to 4.5 V 2 µA IZCDsrc Source Current Capability -3 -10 mA IZCDsnk Sink Current Capability 3 10 mA VDIS Disable Threshold 150 200 250 mV IZCDr Restart Current After Disable VZCD < VDIS, Vcc > Vccoff -70 -150 -230 µA TBLANK Blanking time after pin 7 high-to- low transition VCOMP ≥ 3.2 V 3.5 µs VCOMP = 2.5 V 18 START TIMER tSTART Start Timer period 250 400 550 µs GATE DRIVER VOL Dropout Voltage I GDsource = 200mA 1.2 2 V IGDsource = 20mA 0.7 1 VOH IGDsink = 200mA 2 V IGDsink = 20mA 0.3 tf Current Fall Time 40 100 ns tr Current Rise Time 40 100 ns IGDoff IGD sink current Vcc = 4 V, V GD = 1 V 5 10 mA (1) Parameters guaranteed by design, not tested in production. ELECTRICAL CHARACTERISTCS (continued) (Tj = -25 to 125°C, VCC = 12V, Co = 1nF; unless otherwise specified) Symbol Parameter Test Condition Min. Typ. Max. Unit
APPLICATION INFORMATION
Quasi-resonant operation in offline flyback converters lies in synchronizing MOSFET's turn-on to the transform- er's demagnetization. Detecting the resulting negative-going edge of the voltage across any winding of the transformer can do this. The L6565 is provided with a dedicated pin that allows doing the job with a very simple interface, just one resistor. Variable frequency operation - as a result of different operating conditions in terms of input voltage and output current - is inherent in such functionality. The system always works close to the boundary between DCM (Dis- continuous Conduction Mode) and CCM (Continuous Conduction Mode) operation of the transformer. The op- eration is then identical to that of the so-called self-oscillating or Ringing Choke Converter (RCC). Detailed Device Description Internal Supply Block (see fig. 12) A linear voltage regulator supplied by Vcc (pin 8) generates an internal 7V rail used for supplying the entire IC, except for the gate driver that is supplied directly from Vcc. In addition, a bandgap circuit generates a precise internal reference (2.5V±1% @ 25°C) used by the control loop to ensure a good regulation with primary feed- back technique. In figure 12 it is also shown the undervoltage lockout (UVLO) comparator with hysteresis used to enable the chip as long as the Vcc voltage is high enough to ensure a reliable operation. Figure 12. L6565 internal supply block
device is not required to work in QR mode but as a standard PWM controller in a synchronized system (e.g. ZCD circuit erroneously; second, to realize the Frequency Foldback function (see the relevant description). Figure 13. Zero Current Detection and Triggering Block; Disable and Frequency Foldback Blocks A circuit is needed that turns on the external MOSFET at start-up since no signal is coming from the ZCD pin. This is realized with an internal starter, which forces the driver to deliver a pulse to the gate of the MOSFET. by and sunk from the pin within the rated capability of the internal clamps. the pull-down on the pin must be released.
csx (with the error amplifier saturated high in the attempt of keeping output voltage regulation). in the diagram of figure 16. value of about 1.4V (1.5V max.). ripple rejection ability and limits the variation of the power stage's small-signal gain versus the line voltage. Figure 17. a) Overcurrent setpoint vs. VFF voltage; b) Line Feedforward function block
1 DRIVER
noise generated ("double-pulse suppression"). the Vcc voltage must fall below the UVLO threshold. from the self-supply circuit, the Vcc capacitor will be discharged below the UVLO threshold after some time. will be a low-frequency intermittent operation (Hiccup-mode operation), with very low stress on the power circuit. prevent the voltage at the gate drive output (pin 7, GD) from being pulled too negative. ternal MOSFET cannot be turned on accidentally (e.g. at power-on). Figure 18. Gate driver with UVLO pull-down
Figure 19. 50W Wide Range Mains SMPS for 14" TV Figure 20. 40W Wide Range Mains SMPS for inkjet printer
264 Vac
DIM. mm inch A 3.32 0.131 a1 0.51 0.020 B 1.15 1.65 0.045 0.065 b 0.356 0.55 0.014 0.022 b1 0.204 0.304 0.008 0.012 D 10.92 0.430 E 7.95 9.75 0.313 0.384 e2 . 5 4 0 . 1 0 0 e3 7.62 0.300 e4 7.62 0.300 F 6.6 0.260 I 5.08 0.200 L 3.18 3.81 0.125 0.150 Z 1.52 0.060 Minidip
DIM. mm inch A 1.75 0.069 a1 0.1 0.25 0.004 0.010 a2 1.65 0.065 a3 0.65 0.85 0.026 0.033 b 0.35 0.48 0.014 0.019 b1 0.19 0.25 0.007 0.010 C 0.25 0.5 0.010 0.020 c1 45 ° (typ.) D (1) 4.8 5.0 0.189 0.197 E 5.8 6.2 0.228 0.244 e 1.27 0.050 e3 3.81 0.150 F (1) 3.8 4.0 0.15 0.157 L 0.4 1.27 0.016 0.050 M 0.6 0.024 S8 ° (max.) (1) D and F do not include mold flash or protrusions. Mold flash or potrusions shall not exceed 0.15mm (.006inch). SO8 OUTLINE AND MECHANICAL DATA
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