L6563 STMICROELECTRONICS | Alldatasheet
Document overview
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- PDF pages: 37
Technical content
Datasheet sections
- 1 Description
- 1.1 Pin connection
- 1.2 Pin description
- 2 Absolute maximum ratings
- 3 Thermal data
- 4 Electrical characteristics
- 5 Typical electrical performance
- 6 Application information
- 6.1 Overvoltage protection
- 6.2 Feedback Failure Protection (FFP)
- 6.3 Voltage Feedforward
- 6.4 THD optimizer circuit
- 6.5 Tracking Boost function
- 6.6 Inductor saturation detection (L6563 only)
- 6.7 Power management/housekeeping functions
- 6.8 Summary of L6563/A idle states
- 7 Application examples and ideas
- 8 Package mechanical data
- 9 Revision history
Advanced transition-mode PFC controller General features ■ Transition-mode control of PFC pre-regulators ■ Very precise adjustable output overvoltage protection ■ Tracking boost function ■ Protection against feedback loop failure (Latched shutdown) ■ Interface for cascaded converter's PWM controller ■ Input voltage feedforward (1/V2) ■ Remote ON/OFF control ■ Low (≤90µA) start-up current ■ 5mA max. quiescent current ■ 1.5% (@ TJ = 25°C) internal reference voltage ■ -600/+800 mA totem pole gate driver with active pull-down during UVLO ■ SO14 package
Applications
PFC pre-regulators for: ■ HI-END AC-DC adapter/charger ■ Desktop PC, server, WEB server ■ IEC61000-3-2 OR JEIDA-MITI compliant SMPS, in excess of 250W Order code Part number Package Packaging L6563 SO-14 Tube L6563TR SO-14 Tape & Reel L6563A SO-14 Tube L6563ATR SO-14 Tape & Reel SO-14 Block diagram VREF2 Vbias (INTERNAL SUPPLY BUS) 2.5V ZERO CURRENT DETECTOR VCC 12 3 ZCD VCC INV COMP MULT CS GD GND 12 MULTIPLIER R S Q STARTER 1.7V 6TBO 2.5V PFC_OK 1:1 CURRENT MIRROR RUN 0.52V 0.62V PWM _LATCH VFF LEADING-EDGE BLANKING 1:1 BUFFER from VFF 1.4V 0.7V PWM _STOP Vbias UVLO COMPARATOR 0.2V 0.3V 15 V SATDISABLE LATCH UVLO SAT Ideal diode 1 / V 2 Starter OFF Driver Q TRACKING BOOST ON/OFF CONTROL (BROWNOUT DETECTION) LINE VOLTAGE FEEDFORWARD INDUCTOR SATURATION DETECTION ( not in L6563A ) FEEDBACK FAILURE DETECTION VOLTAGE REGULATOR Voltage references
1 Description
THD even over a large load range. consumption (≤ 90 µA before start-up and ≤ 5 mA running). Figure 1. Typical system block diagram
1.1 Pin connection
Figure 2. Pin connection (top view)
1.2 Pin description
Table 1. Pin description regulator is fed into the pin through a resistor divider. pin to change the output voltage so that it tracks the mains voltage. this pin is used also to derive the information on the RMS mains voltage. to determine MOSFET’s turn-off. the mains voltage. Never connect the pin directly to GND.
function is not used leave this pin open. almost to the start-up level and this condition is latched. PWM_LATCH pin is asserted high. protection in case the feedback loop fails. functions are not needed, tie the pin to a voltage between 0.26 and 2.5 V. its PWM controller. If not used, the pin will be left floating. the pin will be left floating.
10 RUN
undervoltage) protection, tie to INV (pin 1) if the function is not used. going edge triggers MOSFET’s turn-on. 12 GND Ground. Current return for both the signal part of the IC and the gate driver. this pin is clamped at about 12V to avoid excessive gate voltages. 14 VCC Supply Voltage of both the signal part of the IC and the gate driver. Table 1. Pin description (continued) regulator is fed into the pin through a resistor divider. pin to change the output voltage so that it tracks the mains voltage.
2 Absolute maximum ratings
3 Thermal data
Table 2. Absolute maximum ratings Table 3. Thermal data
4 Electrical characteristics
Table 4. Electrical characteristics
Table 4. Electrical characteristics (continued)
(4) Parameters guaranteed by design, functionality tested in production.
5 Typical electrical performance
Figure 3. Supply current vs supply voltage Figure 4. V CC Zener voltage vs TJ Figure 5. IC consumption vs T J Figure 6. Feedback reference vs T J Figure 7. Start-up & UVLO vs T J Figure 8. E/A output clamp levels vs T J
Application information L6563 - L6563A
6 Application information
6.1 Overvoltage protection
Normally, the voltage control loop keeps the output voltage VO of the PFC pre-regulator close to its nominal value, set by the ratio of the resistors R1 and R2 of the output divider. Neglecting the ripple components, under steady state conditions the current through R1 equals that through R2. Considering that the non-inverting input of the error amplifier is internally biased at 2.5V, the voltage at pin INV will be 2.5V as well, then: Equation 1 If the output voltage experiences an abrupt change ∆Vo the voltage at pin INV is kept at 2.5V by the local feedback of the error amplifier, a network connected between pins INV and COMP that introduces a long time constant. Then the current through R2 remains equal to 2.5/R2 but that through R1 becomes: Equation 2 The difference current ∆I R1 = I’R1 - I’R1 = ∆VO/R1 will flow through the compensation network and enter the error amplifier (pin COMP). This current is monitored inside the IC and when it reaches about 18 µA the output voltage of the multiplier is forced to decrease, thus reducing the energy drawn from the mains. If the current exceeds 20 µA, the OVP is triggered (Dynamic OVP), and the external power transistor is switched off until the current falls approximately below 5 µA. However, if the overvoltage persists (e.g. in case the load is completely disconnected), the error amplifier will eventually saturate low hence triggering an internal comparator (Static OVP) that will keep the external power switch turned off until the output voltage comes back close to the regulated value. The output overvoltage that is able to trigger the OVP function is then: Equation 3 ∆VO = R1 · 20 · 10-6 IR2 IR1 2.5 I'R1 VO 2.5– VO∆+
much smaller than Vo, the tolerance on the absolute value will be proportionally reduced. The tolerance on the OVP level due to the L6563/A will be 40·0.15 = 6 V, that is ± 1.36%. discharge of the Vcc capacitor. Figure 33. Output voltage setting, OVP and FFP functions: internal block diagram
Application information L6563 - L6563A
6.2 Feedback Failure Protection (FFP)
The OVP function above described is able to handle "normal" overvoltage conditions, i.e. those resulting from an abrupt load/line change or occurring at start-up. It cannot handle the overvoltage generated, for instance, when the upper resistor of the output divider (R1) fails open: the voltage loop can no longer read the information on the output voltage and will force the PFC pre-regulator to work at maximum ON-time, causing the output voltage to rise with no control. A pin of the device (PFC_OK) has been dedicated to provide an additional monitoring of the output voltage with a separate resistor divider (R3 high, R4 low, see Figure 33). This divider is selected so that the voltage at the pin reaches 2.5V if the output voltage exceeds a preset value, usually larger than the maximum Vo that can be expected, also including worst-case load/line transients. Example: V O = 400 V, Vox = 475V. Select: R3 = 3MΩ; When this function is triggered, the gate drive activity is immediately stopped, the device is shut down, its quiescent consumption is reduced below 250 µA and the condition is latched as long as the supply voltage of the IC is above the UVLO threshold. At the same time the pin PWM_LATCH is asserted high. PWM_LATCH is an open source output able to deliver 3.7V min. with 0.5 mA load, intended for tripping a latched shutdown function of the PWM controller IC in the cascaded DC-DC converter, so that the entire unit is latched off. To restart the system it is necessary to recycle the input power, so that the Vcc voltages of both the L6563/A and the PWM controller go below their respective UVLO thresholds. The PFC_OK pin doubles its function as a not-latched IC disable: a voltage below 0.2V will shut down the IC, reducing its consumption below 1 mA. In this case both PWM_STOP and PWM_LATCH keep their high impedance status. To restart the IC simply let the voltage at the pin go above 0.26 V. Note that this function offers a complete protection against not only feedback loop failures or erroneous settings, but also against a failure of the protection itself. Either resistor of the PFC_OK divider failing short or open or a PFC_OK pin floating will result in shutting down the IC and stopping the pre-regulator.
6.3 Voltage Feedforward
The power stage gain of PFC pre-regulators varies with the square of the RMS input voltage. So does the crossover frequency f c of the overall open-loop gain because the gain has a single pole characteristic. This leads to large trade-offs in the design. For example, setting the gain of the error amplifier to get fc = 20 Hz @ 264 Vac means having fc ≅ 4 Hz @ 88 Vac, resulting in a sluggish control dynamics. Additionally, the slow control loop causes large transient current flow during rapid line or load changes that are limited by the dynamics of the multiplier output. This limit is considered when selecting the sense resistor to let the full load power pass under minimum line voltage conditions, with some margin. But a fixed current limit allows excessive power input at high line, whereas a fixed power limit requires the current limit to vary inversely with the line voltage. Voltage Feedforward can compensate for the gain variation with the line voltage and allow overcoming all of the above-mentioned issues. It consists of deriving a voltage proportional to the input RMS voltage, feeding this voltage into a squarer/divider circuit (1/V 2 corrector) and providing the resulting signal to the multiplier that generates the current reference for the inner current control loop (see Figure 34).
Figure 34. Voltage feedforward: squarer-divider (1/V 2) block diagram and transfer range, which improves significantly dynamic behavior at low line and simplifies loop design. voltage changes. Clearly a trade-off is required. in systems with no feedforward compensation.
6.4 THD optimizer circuit
current flow to temporarily stop. near the line voltage zero-crossings as compared to that commanded by the control loop. discharging the high-frequency filter capacitor after the bridge. Figure 36. THD optimization: standard TM PFC controller (left side) and L6563/A
Application information L6563 - L6563A Essentially, the circuit artificially increases the ON-time of the power switch with a positive offset added to the output of the multiplier in the proximity of the line voltage zero-crossings. This offset is reduced as the instantaneous line voltage increases, so that it becomes negligible as the line voltage moves toward the top of the sinusoid. Furthermore the offset is modulated by the voltage on the V FF pin (see Section 6.3 on page 18 section) so as to have little offset at low line, where energy transfer at zero crossings is typically quite good, and a larger offset at high line where the energy transfer gets worse. The effect of the circuit is shown in Figure 36, where the key waveforms of a standard TM PFC controller are compared to those of this chip. To take maximum benefit from the THD optimizer circuit, the high-frequency filter capacitor after the bridge rectifier should be minimized, compatibly with EMI filtering needs. A large capacitance, in fact, introduces a conduction dead-angle of the AC input current in itself - even with an ideal energy transfer by the PFC pre-regulator - thus reducing the effectiveness of the optimizer circuit.
6.5 Tracking Boost function
In some applications it may be advantageous to regulate the output voltage of the PFC pre- regulator so that it tracks the RMS input voltage rather than at a fixed value like in conventional boost pre-regulators. This is commonly referred to as "tracking boost" or "follower boost" approach. With this IC the function can be realized by connecting a resistor (R T) between the TBO pin and ground. The TBO pin presents a DC level equal to the peak of the MULT pin voltage and is then representative of the mains RMS voltage. The resistor defines a current, equal to V(TBO)/R T, that is internally 1:1 mirrored and sunk from pin INV (pin 1) input of the error amplifier. In this way, when the mains voltage increases the voltage at TBO pin will increase as well and so will do the current flowing through the resistor connected between TBO and GND. Then a larger current will be sunk by INV pin and the output voltage of the PFC pre- regulator will be forced to get higher. Obviously, the output voltage will move in the opposite direction if the input voltage decreases. To avoid undesired output voltage rise should the mains voltage exceed the maximum specified value, the voltage at the TBO pin is clamped at 3V. By properly selecting the multiplier bias it is possible to set the maximum input voltage above which input-to-output tracking ends and the output voltage becomes constant. If this function is not used, leave the pin open: the device will regulate a fixed output voltage. Starting from the following data:
- Vin1 = minimum specified input RMS voltage;
- Vin2 = maximum specified input RMS voltage;
- Vo1 = regulated output voltage @ Vin = Vin1;
- Vo2 = regulated output voltage @ Vin = Vin2;
- Vox = absolute maximum limit for the regulated output voltage;
- ∆Vo = OVP threshold,
to set the output voltage at the desired values use the following design procedure: 1. Determine the input RMS voltage Vin clamp that produces Vo = Vox: Equation 6 and choose a value Vinx such that Vin2 = Vinx < Vinclamp. This will result in a limitation of the output voltage range below Vox (it will equal Vox if one chooses Vinx = Vinclamp) 2. Determine the divider ratio of the MULT pin (pin 3) bias: Equation 7 and check that at minimum mains voltage Vin1 the peak voltage on pin 3 is greater than 0.65V. 3. Determine R1, the upper resistor of the output divider: Equation 8 4. Calculate the lower resistor R 2 of the output divider and the adjustment resistor RT: Equation 9 Vin clamp Vox Vo 1– Vox Vo 2– k 3 2V i n x⋅ R1 Vo∆ R2 2.5 R1 Vin 2 Vin 1– RT 2kR 1 Vin 2 Vin 1–
Application information L6563 - L6563A 5. Check that the maximum current sourced by the TBO pin (pin 6) does not exceed the maximum specified (0.25mA): Equation 10 In the following Mathcad® sheet, as an example, the calculation is shown for the circuit illustrated in Figure 39 shows the internal block diagram of the tracking boost function. Design data Vin1 := 88V Vo 1:= 200V Vin2 := 264V Vo 2:= 385V Vox ;= 400V ∆Vo ;= 40V Step 1 choose: Vinx: = 270V Step 2 Step 3 ITBOmax RT Vin clamp : Vox Vo 1– Vox Vo 2– k: 3 2V i n x⋅ R1: Vo∆
Figure 37. Processing result
6.6 Inductor saturation detection (L6563 only)
which leads to a catastrophic failure after few switching cycles. current and, furthermore, there is little or no voltage available for demagnetization. Figure 38. 80W, wide-range-mains PFC pre-regul ator with tracking boost function active Figure 39. Tracking boost and voltage feedforward blocks
to be tolerated, the L6563A does not support this protection function.
6.7 Power management/housekeeping functions
enables/disables the operation of the PFC stage. Figure 40. Effect of boost inductor saturation on the MOSFET current and detection method
higher than those of the L6563/A. Figure 41. Interface circuits that let DC-DC converter’s controller IC disable the L6563/A at light
specified holdup time respectively. cause the device to stop operating. Figure 44. Brownout protection (master PFC)
6.8 Summary of L6563/A idle states
Table 5. Summary of L6563/A idle states
7 Application examples and ideas
Figure 45. Demo board (EVAL6563-80W) 80W, Wide-range, Tracking Boost: Electrical schematic Figure 46. EVAL6563-80W: PCB and component layout (Top view, real size: 64 x 94 mm)
Figure 47. EVAL6563-80W: PCB layout, soldering side (Top view) Note: Measurements done with the line filter shown in Figure 49. Note: Measurements done with the line filter shown in Figure 49. Table 6. EVAL6563-80W: Evaluation results at full load Table 7. EVAL6563-80W: Evaluation results at half load
8 Package mechanical data
conditions are also marked on the inner box label. ECOPACK is an ST trademark. Table 8. SO-14 Mechanical data Figure 54. Package dimensions
9 Revision history
Table 9. Revision history