L6460

L6460 STMICROELECTRONICS | Alldatasheet

Document overview

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Technical content

Datasheet sections

• 1 General description
• 1.1 Overview
• 1.2 Pin connection
• 1.3 Pin list
• 2 L6460’s main features
• 3 Electrical specifications
• 3.1 Absolute maximum rating
• 3.2 Operating ratings specifications
• 3.3 Electrical characteristics
• 4 Internal supplies
• 4.1 V SupplyInt regulator
• 4.2 Charge pump regulator
• 4.3 V3v3 regulator
• 5 Supervisory system
• 5.1 Power on reset (POR) circuit
• 5.3 Thermal shut down generation circuit
• 6 Watchdog circuit
• 7 Internal clock oscillator
• 8 Start-up configurations
• 8.1 Operation modes
• 8.2 Basic device mode
• 8.3 Slave device mode
• 8.4 Master device mode
• 8.5 Single device mode
• 8.6 Sub-configurations for slave, master or single device modes

Datasheet sections

• 15.1 Voltage divider specifications
• 16 Current DAC circuit
• 17 Operational amplifiers
• 18 Low voltage power switches
• 19 General purpose PWM
• 19.2 Programmable PWM generator (GpPwm)
• 20 Interrupt controller
• 21 Digital comparator
• 22 GPIO pins
• 22.1 GPIO[0]
• 22.2 GPIO[1]
• 22.3 GPIO[2]
• 22.4 GPIO[3]
• 22.5 GPIO[4]
• 22.6 GPIO[5]
• 22.7 GPIO[6]
• 22.8 GPIO[7]
• 22.9 GPIO[8]
• 22.10 GPIO[9]
• 22.11 GPIO[10]
• 22.12 GPIO[11]
• 22.13 GPIO[12]
• 22.14 GPIO[13]
• 22.15 GPIO[14]
• 23 Serial interface
• 23.1 Read transaction
• 23.2 Write transaction

Features

■ Operating supply voltage from 13 V to 38 V ■ 4 full bridge driver configurable in multi-motor application to drive: – 2 DC and 1 stepper motor –4 D C m o t o r ■ Bridge 1 and 2 (RDSon = 0.60 Ω) can be configured to work as: – Dual full bridge driver – Super DC driver – 2 half bridge driver – 1 super half bridge –2 p o w e r s w i t c h e s – 1 super power switch ■ Bridge 3 and 4 (RDSon = 0.85 Ω) can be configured to work as: – Same as bridges 1 and 2, listed above – Stepper motor driver: up to 1/16 microstepping – 2 buck regulators (bridge 3) – 1 super buck regulator – Battery charger (bridge 4) ■ Power supply management – One switching buck regulator – One switching regulator controller – One linear regulator – One battery charger ■ Fully protected through – Thermal warning and shutdown – Overcurrent protection – Undervoltage lock-out ■ SPI interface ■ Programmable watchdog function ■ Integrated power sequencing and supervisory functions with fault signaling through serial interface and external reset pin ■ Very low power dissipation in shut-down mode (~35 mW) ■ Auxiliary features – Multi-channels 9 bit ADC – 2 operational amplifiers – Digital comparator – 2 low voltage power switches – 3 general purpose PWM generators –1 4 G P I O s

Description

The L6460 is optimized to control and drive multi- motor system providing a unique level of integration in term of control, power and auxiliary features. Thanks to the high configurability L6460 can be customized to drive different motor architectures and to optimize the number of embedded features, such as the voltage regulators, the high precision A/D converter, the operational amplifier and the voltage comparators. The possibility to drive simultaneously stepper and DC motor makes L6460 the ideal solution for all the application featuring multi motors. Table 1. Device summary

8.6.5 Bridge + V

1 General description

1.1 Overview

A/D converter, 2 operational amplifiers and 14 configurable GPIOs. power stage featuring additional voltage buck regulators. Figure 1. Block diagram Note: See following Chapter 2 for a detailed description of possible configurations.

1.2 Pin connection

Figure 2. Pin connection

1.3 Pin list

Table 2. Pins configuration

1 DC1_PLUS Bridge 1 phase “plus” output Output

4 GPIO4 General purpose I/O A nalog In/Out - CMOS bi-dir

5 GPIO3 General purpose I/O A nalog In/Out - CMOS bi-dir

6 DC1_MINUS Bridge 1 phase “minus” output Output

7 DC1_MINUS Bridge 1 phase “minus” output Output

8 GND1 Ground pin for bridge1

9 GND2 Ground pin for bridge2 (1)(2)(3) Power/digital

10 DC2_MINUS Bridge 2 phase “minus” output Output

11 DC2_MINUS Bridge 2 phase “minus” output Output

12 GPIO2 General purpose I/O A nalog In/Out - CMOS bi-dir

13 GPIO1 General purpose I/O A nalog In/Out - CMOS bi-dir

14 GPIO0 General purpose I/O Analog Input - CMOS input

16 DC2_PLUS Bridge 2 phase “plus” output Output

17 DC2_PLUS Bridge 2 phase “plus” output Output

19 MISO SPI serial data output CMOS output

20 MOSI SPI serial data input CMOS input

21 V LINmain_FB Linear main regulator feedback Analog input

22 V LINmain_OUT Linear main regulator output Power output

23 GPIO 8 General purpose I/ O Analog In/Out - CMOS bi-dir

24 V SWmain_SW Main switching regulator switching output Power output

25 V Supply Main voltage supply Power Input

26 V SWmain_FB Main switching regulator feedback pin Analog input

27 V REF_FB Regulator voltage feedback Analog input

28 I REF_FB Regulator current feedback Analog input

29 SCLK SPI input clock pin CMOS input

30 V Supply Main voltage supply Power input

31 DC4_PLUS Bridge 4 phase “plus” output Output

33 DC4_SENSE Bridge 4 sense output (4) Output

35 GPIO12 General purpose I/O A nalog In/Out - CMOS bi-dir

36 GPIO13 General purpose I/O A nalog In/Out - CMOS bi-dir

37 GPIO14 General purpose I/O A nalog In/Out - CMOS bi-dir

39 DC4_MINUS Bridge 4 phase “minus” output Output

40 DC4_SENSE Bridge 4 sense output (4) Output

41 DC3_SENSE Bridge 3 sense output (4) Output

42 DC3_MINUS Bridge 3 phase “minus” output Output

44 GPIO11 General purpose I/O A nalog In/Out - CMOS bi-dir

45 GPIO10 General purpose I/O A nalog In/Out - CMOS bi-dir

46 GPIO9 General purpose I/O A nalog In/Out - CMOS bi-dir

47 GPIO5 General purpose I/O A nalog In/Out - CMOS bi-dir

48 DC3_SENSE Bridge 3 sense output

50 DC3_PLUS Bridge 3 phase “plus” output Output

51 V Supply Main voltage supply Power input

54 V SupplyInt Internal voltage supply Power Input

55 GPIO7 General purpose I/O A nalog In/Out - CMOS bi-dir

56 V GPIO_SPI Low voltage pins power supply Power input

57 GPIO6 General purpose I/O A nalog In/Out - CMOS bi-dir

58 V SWDRV_SW Switching regulator controller source input Power input

59 V SWDRV_GATE Switching driver gate drive pin Analog output

60 V Pump Charge pump voltage Power Input/output

61 CPH Charge pump high switch pin Power Input/output

62 CPL Charge pump low switch pin Power Input/output

63 V Supply Main voltage supply Power input

64 DC1_plus Bridge 1 phase “plus” output Output

1. These pins must be connected all together to a unique PCB ground.
2. Bridges1 and 2 have 2 ground pads: one is bonded to the relative ground pin (GND1 or GND2) and the

the resistance of E-Pad bonding. (N.B: grounds of two bridges are internally connected together).

1. The analog ground is connected to exposed pad E-Pad.
2. The pin must be tied to ground if bridge is not used as a stepper motor.

Table 2. Pins configuration (continued)

L6460’s main features L6460 14/139 Doc ID 17713 Rev 1

2 L6460’s main features

L6460 includes the following circuits:

• Four widely configurable full bridges: – Bridges 1 and 2: – Diagonal R DSon: 0.6 Ω typ. – Max operative current = 2.5 A. – Bridges 3 and 4: – Diagonal R DSon: 0.85 Ω typ. – Max operative current = 1.5 A.
• Possible configurations for each bridge are the following: – Bridge 1: – DC motor driver. – Super DC (bridge 1 and 2 paralleled form superbridge1). – 2 independent half bridges. – 1 super half bridge (bridge 1 side A and bridge 1 side B paralleled form superhalfbridge1). – 2 independent switches (high or low side). – 1 super switch (high or low side). – Bridge 2 has the same configurations of bridge 1. – Bridge 3 has the same configurations of bridge 1 (bridge 3 and 4 paralleled form superbridge2) plus the following: – ½ stepper motor driver. – 2 buck regulators (V AUX1_SW, VAUX2_SW). – 1 Super buck regulator (V AUX1//2_SW). – Bridge 4 has the same configurations of bridge 1 plus the following: – ½ stepper motor driver. – 1 super buck regulator (V AUX3_SW). – Battery charger.
• One buck type switching regulator (VSWmain) with: – Output regulated voltage range: 1-5 Volts. – Output load current: 3.0 A. – Internal output power DMOS. – Internal soft start sequence. – Internal PWM generation. – Switching frequency: ~250 kHz. – Pulse skipping strategy control.
• One switching regulator controller (VSWDRV) with: – Output regulated voltage range: 1-30 Volts. – Selectable current limitation. – Internal PWM generation. – Pulse skipping strategy control.
• One linear regulator (VLINmain) that can be used to generate low current/low ripple

L6460 L6460’s main features Doc ID 17713 Rev 1 15/139 voltages. This regulator can be used to drive an external bipolar pass transistor to generate high current/low ripple output voltages.

• One bidirectional serial interface with address detection so that different ICs can share the same data bus.
• Integrated power sequencing and supervisory functions with fault signaling through serial interface and external reset pin.
• Fourteen general purpose I/Os that can be used to drive/read internal/external analog/logic signals.
• One 8-bit/9-bit A/D converter (100 kS/s @ 9-bit, 200 kS/s @8-bit). It can be used to measure most of the internal signals, of the input pins and a voltage proportional to IC temperature. – Current sink DAC: – Three output current ranges: up to 0.64/6.4/64 mA. – 64 (6-bit programmable) availabl e current levels for each range. – 5 V output tolerant.
• Two operational amplifiers: – 3.3 V supply, rail to rail input co mpatibility, internally compensated. – They can have all pins externally accessible or can be internally configured as a buffer o make internal reference voltages available outside of the chip. – Unity gain bandwidth > 1 MHz. – They can also be set as comparators with 3.3 V input compatibility and low offset.
• Two 3.3 V pass switches with 1 Ω RDSon and short circuit protected.
• Programmable watchdog function.
• Thermal shutdown protection with thermal warning capability.
• Very low power dissipation in “low power mode” (~35 mW) L6460 is intended to maximize the use of its components, so when an internal circuit is not used it could be employed for other applications. Bridge 3, for example, can be used as a full bridge or to implement two switching regulators with synchronous rectification: to obtain this flexibility L6460 includes 2 separate regulation loops for these regulators; when the bridge is used as a motor driver, the 2 regulation loops can be redirected on general purpose I/Os to leave the possibility to assembly a switching regulator by only adding an external FET.

3 Electrical specifications

3.1 Absolute maximum rating

The following specifications define the maximum range of voltages or currents for L6460.

3.2 Operating ratings specifications

Table 3. Absolute maximum ratings

1. This value is useful to define the voltage rati ng for external capacitor to be connected from VPump to

to provide voltage to external loads.

1. TSD is the thermal shut do wn temperature of the device.

Table 4. IC operating ratings

3.3 Electrical characteristics

1. For V supply lower than 21 V an external resistor between Vsupply and Vsupply Int pins are required.

For Vsupply lower than 15 V external diodes for charge pump are required.

1. Operating supply current is measured with system regulators operating but not loaded.
2. Operating V GPIO_SPI current is measured with all circuits supplied by VGPIO_SPI (GPIO’s, operational

amplifiers and pass switches) enabled but not loaded.

1. The external components connected to the pin must be chosen to avoid that the voltage exceeds this

Table 5. Electrical characteristics

Table 5. Electrical characteristics (continued)

1. This value is useful to define the voltage rating for external capacitor to be connected from VSupply to VSupplyInt.
2. This typical value is only intended to give an estimation of the current consumption when L6460 is configured in simple

recommendations on Chapter 4.1).

1. Measured between 10% and 90% of output voltage transition.
2. Measured from a fault detection to 50% of output voltage transition.
3. Current is defined to be positive when flowing into the pin.
4. Load regulation is calculated at a fixed junction temperature using short load pulses covering all the load current range. This

is to avoid change on output voltage due to heating effect.

1. Undervoltage rising and falling thresholds are intended as a percentage of feedback pin voltage (V
2. The regulated voltage can be calculated using the formula: V

SWmain_OUT = VFBREF *(Ra+Rb)/Rb.

1. Undervoltage rising and falling thresholds are intended as a percentage of feedback pin voltage (VSW_main_FB). 11. This condition is intended to simulate an extra current on output. 12. This condition is intended to simulate a short circuit on output. 13. Rise and fall time are measured between 10% and 90% V SWmain output voltage. 14. Undervoltage rising and falling thresholds are intended as a percentage of feedback pin voltage (VSWDRV_FB). 15. The current protection values must be intended as a protection for the chip and not as a continuous current limitation. The protection is performed by switching off the output bridge when current reaches values higher than the IOC max. No protection could be guaranteed for values in the middle range between IMAX and IOC 16. In this cell X stands for 1 or 2, Y stands for A or B 17. In this cell X stands for 3 or 4, Y stands for A or B 18. The current protection thresholds for Bridge 3 a nd 4 are not selectable so only the max current value (MtrXSideYILimSel[1:0]= 11) is available. 19. Overcurrent Off time can be configured using SPI. 20. Rise and fall time are measured between 10% and 90% of DC out put voltage. With device in full bridge configuration (resistive load between outputs). 21. Default state for Aux1 22. Default state for Aux2 23. The regulated voltage can be calculated using the formula: V AUX_SW = VFBREF *(Ra+Rb)/Rb. 24. Undervoltage rising and falling thres holds are intended as a percentage of feedback pin voltage (GPIO1 and/or GPIO2) 25. Rise and fall time is measured between 10% and 90% of output voltage. 26. The external components connected to the pin must be chos en to avoid that the voltage exceeds this operative range. 27. The regulated voltage can be calculated using the formula: V AUX3_SW = VFBREF *(Ra+Rb)/Rb. 28. Undervoltage rising and falling thresholds are intended as a percentage of feedback pin voltage (VREF_FB). 29. The definition of LSB for this table is LSB=IMRmax/(2 7.5-1). 30. Integral Non Linearity error (INL) is defined as the maximu m distance between any point of the ADC characteristic and the “best straight line” approximating the ADC transfer curve. 31. The ADC ensures monotonic characteristic and no missing codes. 32. Differential nonlinearity error (DNL) is defined as the difference between an actual step width and the ideal width value of 1 LSB. adjusting for offset error. 35. Please note that the result of the conversion will always be a 9-bit word: to speed up the conversion, the resolution is reduced when the ADC is used in the 8- bit resolution mode. 36. Actual input capacitance depends on t he pin that must be converted. 37. The definition of LSB for this table is LSB=IMRmax/(2 9-1). 38. All parameters are guaranteed in the range between V OL and VR Max. 39. Measured from DacValue[5:0] change in SPI interface. 40. V GPIO_SPI = 3.3 V unless otherwise specified 41. In this section reports the operational amplif ier parameters that change when used as comparator. 42. ΔVi is the differential voltage applied to input pins across the common voltage VCM. 43. Measured between 50% of input and output signal. 44. Time measured from change in SPI interf ace to 50% of external pin transition. 45. Measured between nSS rising edge and 50% of V out. 46. Specification applies to nSS, SCLK and MOSI pins. 47. Current is considered to be positive when flowing towards the IC 48. These times are measured at the pin output between specified V OH and VOL.

4 Internal supplies

4.1 V SupplyInt regulator

Supply pin), recommended value is in the range 80 ÷ 120 nF . Figure 3. V SupplyInt pin REXT could be chosen by applying this formula: REXT = (VSupply min - VS_Int max)/(IS_Int max). by the circuits connected to this pin. For example, with VSupply = 32 V and IS_Int = 12 mA a typical resistor value is 1 kΩ.

4.2 Charge pump regulator

below its under voltage falling threshold, all the regulators will be switched off. The charge pump circuit is disabled when L6460 is in “low power mode”. Figure 4. Charge pump block diagram

4.3 V3v3 regulator

V3v3 is the output of an internal regulator used to supply some low voltage internal circuits. recommended value is in the range 80 ÷ 120 nF .

5 Supervisory system

The supervisory circuitry monitors the state of several functions inside L6460 and resets the device (and other ICs if connected to nRESET pin) when the monitored functions are outside their normal range. Supervisory circuitr y can be divided into three main blocks: – Power on reset (POR) generation circuitry. – nRESET (nRST_int) generation circuitry. – Thermal shut down (TSD) generation circuitry. POR circuitry monitors the voltages that L6460 needs to guarantee its own functionality; nRESET circuitry controls if L6460’s main voltages are inside the normal range; TSD is the thermal shut down of the chip in case of overheating.

5.1 Power on reset (POR) circuit

Power on reset circuit monitors VSupply, and V3V3 voltages. The purpose of this circuit is to set the device is in a stable and controlled status until the minimum supply voltages that guarantee the device functionality are reached. The output signal of this circuit (in the following indicated as “POR”) becomes active when V Supply or V3V3 go under their falling threshold. When POR output signal is active, all functions and all flags inside L6460 are set in their reset state; once POR signal comes back from off state (meaning monitored voltages are above their rising threshold), the power up sequence is re-initialized. 5.2 nRESET generation circuit The nRESET circuit monitors VSupply, VSupplyInt, VPump, VGPIO_SPI and all system regulators (VSystem) voltages. The purpose of this circuit is to prevent the device functionality until the monitored voltages reach their operative value (please note that V3v3 is monitored by POR, so it must be above its minimum value, otherwise nRESET circuit is not active). This circuit generates an internal reset signal (in the following indicated as “nRST_int”) that will also be signaled to external circuits by pulling low the nRESET pin. The signal nRST_int becomes active in the following cases: 1. When one of the following voltages is lower than its own under voltage threshold: –V Supply and VSupplyInt. –V Pump. –V System (all switching or linear system regulators voltages). –V GPIO_SPI. 2. When watchdog timer counter (see Chapter 6) elapse the watchdog timeout time (only if watchdog function is enabled). 3. When L6460 is in “Low Power mode”. 4. When EnExtSoftRst bit in SoftResReg register is at logic level = “1” and a “SoftRes” command is applied (see SoftResReg register description in Chapter 25). When an nRST_int event is caused by above cases, the nRESET pin will stay low for a “stretch” time that starts from the moment that nRST_int signal returns in the operative

according to following table. – Serial interface will be reset and will not accept any other command. direction signals will be reset. – AD converter will be powered off. – GPIOs will be powered off. – Current DAC will be powered off. – Operational amplifie rs will be powered off. – Watchdog count will be reset (while Watchdog flags won’t be reset). – Interrupt controller will be powered off. – Digital comparator will be powered off. nRST_int in power up sequence will be powered off. Table 6. Stretch time selection

Figure 5. nReset generation circuit considered as nRESET circuit voltages.

5.3 Thermal shut down generation circuit

The third component of the supervisory circuit is the thermal shut down generation circuit. This circuit generates two different flags depending on the IC temperature: – the “TSD” flag indicates that the IC temperature is greater than the maximum allowable temperature. – the “Warm” flag, that can be read using serial interface, becomes active at a lower temperature respect to TSD signal, therefore it can be used to prevent the IC from reaching over temperature. When a TSD event occurs, L6460 will enter in the reset state placing the bridges in high impedance and turning off all regulators and other circuits until the internal temperature decreases below the Warm temperature. At this point, L6460 will restart the power up sequence and TSD bit will be set and will be readable as soon as L6460 will come out from the reset state. This TSD bit can be reset in three ways: – by writing a logic level ‘1’ in the Clea rTSD bit in the ICTemp register (see Chapter 24); – by a POR event; – by entering in “Low Power Mode”. The Warm bit, set by L6460 when IC is working over the warming temperature, can be read using the SPI interface. Once this bit is set it can be reset in three ways: – by writing a logic level ‘1’ in the ClearWarm bit; – by a POR event; – by entering in “Low Power Mode”. The thermal sensor voltage can be converted using the internal A/D: this way the microcontroller can directly measure the IC temperature. To avoid unwanted commutation especially when temperature is near the thresholds, the output signal is filtered for both TSD and Warm.

6 Watchdog circuit

periodically write at logic level “1’ the ClrWDog bit in the WatchDogStatus register. WDEnable bit in the WatchDogCfg register. – by writing a ‘1’ in the WDClear bi t in the WatchDogStatus register. – by writing a ‘1’ in the SoftReset bit in the WatchDogStatus register. signal to cause an “nRst_int” event by setting to logic ‘1’ the WDEnnRst bit. Figure 6. Watchdog circuit block diagram the WD delay value is loaded. WDdelay[3:0] bits in the WatchDogCfg register according to following table.

Table 7. Watchdog timeout specifications

Internal clock oscillator L6460 38/139 Doc ID 17713 Rev 1

7 Internal clock oscillator

L6460 includes a free running oscillator that does not require any external components. This circuit is used to generate the time base needed to generate the internal timings; the typical frequency is 16 MHz. The oscillator circuit starts as soon as the IC exits from the power on reset condition and it is stopped only when in “low power mode”.

8 Start-up configurations

8.1 Operation modes

select its start-up configuration. Table 8. Possible start-up pins state symbol

8.2 Basic device mode

doesn’t use GPIO[3] and GPIO[4] as configuration pins, leaving them free for other uses.

1. Auxiliary switching regulator1 (V AUX1_SW).
2. Auxiliary switching regulator2 (V AUX2_SW).
3. Main linear regulator (V SWmain).
4. Main switch ing regulator (VSWmain) (Not system regulator).

Table 9. Start-up correspondence

1. The description of these modes is in the following Chapter 8.6

001 R e g u l a t o r s

0 Z 0 Simple regulator

0 Z Z Bridge + VEXT

1. VEXT is the regulator output voltage obtained using the switching regulator controller with external FET.

0 Z 1 Secondary regulators

011 R e g u l a t o r s

1 Z Z Primary regulator

1 Z 1 Regulators

L6460 Start-up configurations Doc ID 17713 Rev 1 41/139

8.3 Slave device mode

In slave device mode, L6460 consider the nAWAKE pin as an input enable. Since this is now a digital pin, the current pull up source inside the nAWAKE circuit is disabled. At the startup, if the nAWAKE pin is found to be low for a period higher than tAWAKEFILT, L6460 enters directly in the “Low Power mode”; when nAWAKE pin is pulled high for a period higher than t AWAKEFILT, L6460 begins its start up procedure.

8.4 Master device mode

In master device mode, L6460 begins its start up procedure without waiting for any external enable signal and it uses GPIO[5] pin to drive the nAWAKE pin of Slave devices. During the whole start up time, it forces its GPIO[5] pin at logic level “0” in order to maintain all slave devices in “Low Power mode” as previously described. When start up operations are completed, L6460 forces the GPIO[5] output to logic level “1” to enable the slave devices and keeps GPIO[5] output at high level until it senses an under-voltage on any of its System regulators. If firmware writes in the PwrCtrl register to set Master L6460 in “Low Power mode” it immediately forces GPIO[5] output to logic level “0” to force the slave devices to enter in “Low Power mode”, then it waits for T MASTWAIT time and it starts its “Low Power mode” sequence.

8.5 Single device mode

In single device mode, the device behaves similarly to master device mode but: 1. It doesn’t use the GPIO[5] pin to drive slave devices. 2. It doesn’t wait for T MASTWAIT before entering in “Low Power mode”.

8.6 Sub-configurations for slave, master or single device modes

Each slave, master or single device modes can be divided in other minor modes depending on the start-up sequence needed for L6460 internal regulators. Unless otherwise specified, in all the following modes the regulators included in the start up sequence are considered system regulators and they start in the sequence indicated.

8.6.1 Bridge mode

In this configuration bridges 3 and 4 are not used as regulators and therefore can be configured by the firmware in any of their possible bridge modes. When in this mode the power-up sequence is: 1. Main switching regulator (V SWmain). 2. Main linear regulator (V LINmain).

Start-up configurations L6460 42/139 Doc ID 17713 Rev 1

8.6.2 Primary regulator mode (KP)

In this configuration bridge 4 can be configured by firmware while bridge 3 is configured as two separate synchronous switching regulators. The last regulator in the sequence AUX2_SW) is not considered a system regulator. When in this mode the power-up sequence is: 1. Auxiliary switching regulator1 (V AUX1_SW). 2. Main switch ing regulator (VSWmain) together with main linear regulator (VLINmain). 3. Auxiliary switching regulator2 (V AUX2_SW) (Not system regulator).

8.6.3 Regulators mode

In this configuration bridge 4 can be configured by firmware while bridge 3 is configured as two separate synchronous switching regulators, but the start up sequence is different previous one. When in this mode the power-up sequence is: 1. Main switching regulator (V SWmain). 2. Auxiliary switching regulator1 (V AUX1_SW) 3. Auxiliary switching regulator2 (V AUX2_SW)

8.6.4 Simple r egulator mode (KT)

Also in this configuration bridge 4 can be configured by firmware while bridge 3 is configured as two separate synchronous switching regulators. The last regulator in the sequence SWmain) is not considered a system regulator. When in this mode the power-up sequence is: 1. Auxiliary switching regulator1 (V AUX1_SW). 2. Auxiliary switching regulator2 (V AUX2_SW) 3. Main linear regulator (V LINmain) 4. Main switch ing regulator (VSWmain) (not system regulator).

8.6.5 Bridge + V EXT mode

In this configuration bridges 3 and 4 are not used as regulators and the regulator obtained using the switching regulator controller (VSWDRV) is included in start-up. When in this mode the power-up sequence is: 1. Main switching regulator (V SWmain). 2. Switching regulator controller regulator (VSWDRV). 3. Main linear regulator (V LINmain).

L6460 Start-up configurations Doc ID 17713 Rev 1 43/139

8.6.6 Secondary regulators mode

In this configuration, bridge 3 is configured as a single synchronous switching regulator using its two half bridges in parallel (VAUX_(1//2)SW). When in this mode the power-up sequence is: 1. Main switching regulator (V SWmain). 2. Auxiliary switching regulator (V AUX(1//2)_SW). 3. Main linear regulator (V LINmain).

9 Power sequencing

As soon as VSupply and VSupplyInt are above their power on reset level, L6460 will start the charge pump circuit; once VPump voltage reaches its under voltage rising threshold, L6460 begins a sequence that starts the regulators considered system regulators. A regulator is considered a System regulator if: – It has to start in on state without any user action. – It is included in the power-up sequence. – Its under-voltage event is considered by L6460 as an error condition to be signaled through nRESET pin. Once V Supply and VSupplyInt, VPump and all the system regulators are over their under voltage rising threshold, L6460 enters in the normal operating state, that will release nRESET pin and will wait for SPI commands. L6460 will reduce the noise introduced in the system by switching out of phase all its power circuits (switching regulators, bridges and charge pump). The L6460's startup sequence of operation is the following: – start V 3v3 internal linear regulator – sample startup configuration – wait enable if slave device – start charge pump – start system regulators (see order in Section 8.6) – if master send enable to slave device – wait until V GPIO_SPI becomes ok

10 Power saving modes

10.1 Standby mode

Low voltage power = VSupply* IV3v3. because VSupplyInt is feeded by VSupply, directly or with a resistor in series. VGPIO_SPI voltage can be provided to low voltage circuitry inside L6460. Figure 7. Standby mode function description reset event happens or “Low Power mode” is selected. voltage rail, when the standby mode is used, VGPIO_SPI is requested to be at 3.3V.

10.2 Hibernate mode

L6460’s hibernate mode allows the firmware to switch off some (or all) selected System Regulators leaving in on state only those necessary to resume L6460 to operative condition when waked-up by an external signal. Hibernate mode is selected when the firmware writes the command word in the HibernateCmd register. When in hibernate mode L6460 will force regulators in the state (on/off) selected by the firmware by writing in the HibernateCmd register and will force nRESET pin low. The exiting from hibernate mode is achieved by forcing at low level nAWAKE pin (or GPIO5 pin if L6460 is in Slave mode); L6460 will also exit from hibernate mode if an undervoltage event happens on V Supply, VSupplyInt, VPump or V3v3. When the exit from hibernate mode is due to an external command, L6460 sets to ‘1’ the bit HibModeLth in the HibernateStatus register.

10.3 Low power mode

When in normal operating mode, the microcontroller can place L6460 in “Low Power mode”. In this condition L6460 sets all bridges outputs in high impedance, powers down all regulators (including system regulators and charge pump) and disables almost all its circuits including internal clock reducing as much as possible power consumption. The only circuits that remain active are: 3V3 internal regulator. – nAWAKE pin current pull-up. – nRESET pin that will be pulled low. – POR circuit. The entering in low power mode is obtained in different ways depending if L6460 is configured as slave device or not. When L6460 is configured as slave device the low power mode is directly controlled by nAWAKE pin that acts as an enable: if this pin is low for a time longer then t AWAKEFILT, Low Power mode is entered; if this pin is high L6460 exits from Low Power mode. In all other start-up configurations, Low Power mode is entered by writing a Low Power mode command in the PowerModeControl register; once L6460 is in Low Power mode it starts checking the nAWAKE pin status: if it is found low for a time longer than t AWAKEFILT, L6460 exits from Low Power mode and restarts its startup sequence. When the nAWAKE pin is externally pulled low, the “AWAKE” event is stored and it is readable through SPI. L6460 will also exit from Low Power mode if a POR event is found. Note: When in “Low power mode” V Supply is monitored only for its power on reset level. 10.4 nAWAKE pin At the start up, before L6460 has identified the required operation mode (see Chapter 8), a current sink IINP is always active to pull down nAWAKE pin. As soon as the operation mode (basic, slave, master or single device) is detected, the functionality of nAWAKE pin will be different.

Here below is reported the nAWAKE pin simplified schematic. Figure 8. nAWAKE function block diagram

11 Linear main regulator

disabling most of its internal blocks. – Regulated output voltage from 0.8V to V Supply-2V with a maximum load of 10mA. – Band gap generated internal reference voltage. – Short circuit protected (output current is clamped to 22mA typ). – Low power dissipation mode. Figure 9. Linear main regulator voltage VLINmain_OUT with an output current IOUT is about: Pd= (VSupply-VLINmain_OUT)*IOUT.

Figure 10. Linear main regulator with external bipolar for high current

• VLINmain_OUT = 0.8 V --> 1 µF
• 0.8V< VLINmain_OUT < 2.5 V --> 0.68 µF
• 2.5V= VLINmain_OUT 5 V --> 0.33 µF
• VLINmain_OUT > 5 V --> 0.1 F When this regulator is disabled, the whole circuit is switched off and the current consumption is reduced to a very low level both from V3v3 and from VSupply. When in this condition, the output pin is pulled low by an internal switch. Driver VLINmain_Ref Body Diode Cload Ra Rb VLINmain_ FB Vsupply VLINmain_ OUT

Main switching regulator L6460 50/139 Doc ID 17713 Rev 1

12 Main switching regulator

Main switching regulator is an asynchronous switching regulator intended to be the source of the main voltage in the system. It implements a soft start strategy and could be a system regulator so even if its output voltage VSWmain is not used to power any internal circuit, L6460 will check that it is in the good value range before enabling all its internal functions. When L6460 detects a system regulator under-voltage event with a duration longer than the period defined by the deglitch filter (t prim_uv), it will enter in reset state signaling this event to the microcontroller by pulling low the nRESET pin and disabling most of its internal block (e.g. bridges, GPIOs, …). The output voltage will be externally set by a divider network connected to feedback pin. To reduce as much as possible the regulation voltage error L6460 has the possibility to choose between four feedback voltage references (and, as a consequence, four under-voltage thresholds) using the serial interface. The feedback reference voltage selection is made by writing the SelFBRef bits in the MainSwCfg register. Here after are summarized the primary features of this regulator: – Internal power switch. – Soft start circuitry to limit inrush current flow from primary supply. – Internally generated PWM (250 kHz switching frequency). – Nonlinear pulse skipping control. – Protected against load short circuit. – Cycle by cycle current limiting using internal current sensor. – Under voltage signal (both continuous and latched) accessible through SPI. When L6460 is in “low power mode”, this regulator will be disabled. In order to save external components and power when using two or more L6460 IC’s on the same board, the primary switching regulator can be disabled by serial interface. Care must be paid using this function because an under-voltage on this regulator, as previously seen, will be read as a fault condition by L6460.

12.1 Pulse skipping operation

Pulse skipping is a well known, non linear, control strategy used in switching regulators. In this technique (see Figure 11) the feedback comparator output is sampled at the beginning of each switching cycle. At this time, if the sampled value shows that output voltage is lower than requested one, the complete PWM duty cycle is applied to power switch; otherwise no PWM is applied and the switching cycle is skipped. Once PWM is applied to power element only a current limit event can disable the power switch before the whole duty cycle is finished.

Figure 11. Main switching regulator functional blocks according to following Table 10. MainSwCfg register according to following Table 11. Table 10. Main switching regulator PWM specification Table 11. Main switching regulator current limit

Switching regulator controller L6460 52/139 Doc ID 17713 Rev 1

13 Switching regulator controller

This circuit controls an external FET to implement a switching buck regulator using a non linear pulse skipping control with internally generated PWM signal. The output voltage will be externally set by a divider network connected on feedback pin. To reduce as much as possible the regulation voltage error L6460 has the possibility to switch between four regulator feedback voltage references (and, as a consequence, four under- voltage thresholds) using serial interface. The feedback reference voltage is selected by writing the SelFBRef bits in the SwCtrCfg. This regulator is switched off when L6460 is powered up for the first time and can be enabled using L6460’s SPI interface. Here after are summarized the main features of the regulator: – Soft start circuitry to limit inrush current flow from primary supply. – Changeable feedback reference voltage – Internally generated PWM (250 kHz switching frequency). – Nonlinear pulse skipping control. – Protected against load short circuit. – Cycle by cycle current limiting using internal current sensor. – Under voltage signal (both continuous and latched) accessible through SPI.

Figure 12. Switching regulator controller functional blocks

13.1 Pulse skipping operation

Pulse skipping strategy has already been explained on main switching regulator section. SelSwCtrPWM bits in the SwCtrCfg register using SPI. Table 12. Switching regulator controller PWM specification

13.2 Output equivalent circuit

Figure 13. Switching regulator controller output driving: equivalent circuit and source until the sink command is present.

13.3 Switching regulator contro ller application considerations

reference voltage as indicated in the Table 13. Table 13. Switching regulator controller application: feedback reference

L6460 Switching regulator controller Doc ID 17713 Rev 1 55/139 An example of application can be considered the following, supposing the external mosfet type STD12NF06L: – Max DC current load = 3 A – Typ Over current threshold = 3 A * 1.5 = 4.5 A – L = 150 µH – C = 220-330 µF In this conditions the step-down regulator will result over-load protected, short-circuit protected over all the regulated voltage range and the V Supply range. Other application configurations could be evaluated before being implemented.

14 Power bridges

bridges) that are configurable in several different configurations. that can be read through SPI. limited by integrated freewheeling diodes (see Figure 14). Figure 14. H Bridge block diagram be used to drive the resulting H bridge.

Table 14. PWM selection truth table for bridge 1 or 2

1. In this table X stands for 1 or 2, Y stands for A or B.

00 MotorXPWM (Configurable by means of MtrXCfg

01 AuxXPWM (Configurable by means of

Table 15. PWM selection truth table for bridge 3 or 4

1. In this table X stands for 3 or 4, Y stands for A or B.

00 MotorXPWM (Configurable by means of

Figure 15. Bridge 1 and 2 PWM selection

00 Motor2 PWM

01 Aux2Pwm

10 ExtPwm1

11 ExtPwm2

00 Motor1 PWM

01 Aux1PWM

14.1 Possible configurations

MtrXTable[1:0] bits and the bridge configuration. paralleled form SuperHalfBridgeX or SuperSwitchX. The possible configurations for the bridges are described in the following. Table 16. Bridge selection

00 F u l l b r i d g e

Table 17. Bridge 3 and 4 configuration

14.1.1 Full bridge

reduce its biasing thus contributing to the power saving. high impedance state for the off time. Table 18. Full bridge truth table

00 XX XX XX Z Z

14.1.2 Parallel configur ation (super bridge)

bridge while the two phases - will become phase –. Figure 16. Super bridge configuration Mtr1SideAPwmSel[1:0] (Mtr3SideAPwmSel[1:0]) bits in SPI. the motor and this is the PWM chosen for side A. anti-crossover dead times are slightly increased when the bridges are paralleled.

14.1.3 Half bridge configuration

them as a single super half bridge.

Figure 17. Half bridge configuration In this case each half bridge will behave according to the following truth table. high impedance state for the off time. Table 19. Half bridge truth table

14.1.4 Switch configuration

All resulting switches will behave according to the following truth table. impedance state for the toff time.

14.1.5 Bipolar stepper configuration

– Internal PWM current control. – Fast, mixed and slow current decay modes. internal DAC and an the external RSENSE value. Table 20. Switch truth table

side power MOS for the whole off time. In fast decay mode the current is recirculated through the high and low side power MOS opposite respect to those forcing current to increase. Mixed decay mode is a selectable mix of the previous two modes (fast decay followed by slow decay) and allows the user to find the best trade off between load current ripple and fast current levels transition. Additionally, by setting the SeqMixedOnlyInDecreasingPh bit in the StpCfg1 register, the user can choose to apply the fast decay percentage in mixed mode always or only when the current is decreasing (i.e from 90° to 180° and from 270° to 360° of the sinusoidal wave). By using SPI interface the user can choose:

• Control type (external firmware control, half step, normal drive, wave drive, micro-step).
• Up to 16 current levels (quasi-sinusoidal increments) for each bridge.
• Current direction.
• Decay mode.
• Blanking time.
• Off time (32 values from 2µs to 64µs).
• Percentage of fast decay respect to toff (when in mixed decay mode).

Figure 18. Bipolar stepper configuration GPIO12 (StepReq signal), according to Table 21.

1. Stepping sequence left to external microcontroller: in this mode the current level in

each motor winding is set by the microcontroller via the serial interface.

1. Full step: in this mode the electrical angle will change by 90° steps at each StepReq
2. Half step: in this mode, one motor winding is energized and then two windings
3. Microstepping: in this mode the current in each motor winding has a quasi sinusoidal

StepDir bit according to the Table 23. Table 21. Sequencer driver 0 StepCmd bit in StepCmd register. Table 22. Stepper driving mode

001 Half Step Half step

010 Normal Step Full step (two phases on)

011 Wave Drive Full step (one phase on)

representing the current module and phase. Table 23. Stepper sequencer direction

0 Counter clockwise (CCW)

1 Clockwise (CW)

allows the commutation of the Rsense comparator. depending on the control mode chosen, the selectable steps are Table 25. Table 24. DAC

Table 25. Internal sequencer

Table 25. Internal sequencer (continued)

StepBlkTime[1:0] bits in the StpCfg1 register. Table 26. Stepper off time

Table 26. Stepper off time (continued)

14.1.6 Synchronous buck regulat or configuration (Bridge 3)

strategy similar to that used by primary switching regulator. Table 27. Stepper fast decay

Figure 19. Regulator block diagram must be fast recovery and low series resistance type.

writing the SelFBRef[1:0] bits in the Aux1SwCfg or Aux2SwCfg registers.

14.1.7 Regulation loop

comparators and filters similar to that used in main switching regulator. relative regulation loop is not used they can be accessed as shown in the Figure 20. Figure 20. Internal comparator functional block diagram Table 28. PWM specification

14.1.8 Battery charger or sw itching regulator (Bridge 4)

The control loop block diagram is shown in the Figure 21. Figure 21. Battery charger control loop block diagram to be used as a constant voltage/constant current programmable source. profile in Figure 22) will not be considered during start up sequence.

using the serial interface, writing the SelCurrRef[1:0] bits in the Aux3SwCfg1 register. the internal current limitation will work (typical Ilimit current 4A). In the Figure 22 is shown a typical Li-Ion battery charge profile. Figure 22. Li-ion battery charge profile The battery charge loop control can be used to implement a buck type switching regulator. internally in the Bridge4 section.

Figure 23. Simple buck regulator Aux3BatteryCharge bit must be written in the Aux3SwCfg1 register. The regulator will also implement a soft start strategy. When L6460 “low power mode” is enabled this regulator will be disabled. – Nonlinear pulse skipping control. – Internally generated PWM (250 KHz switching frequency). sense differential amplifier. – Protected against load short circuit. – Soft start circuitry to limit inrush current flow from primary supply. – Under voltage signal (both continuous and latched) accessible through SPI. – Over temperature protection. supply voltage and regulated voltage.

Table 29. Battery charger regulator controller PWM specification

15 AD converter

L6460 integrates and makes accessible via SPI a general purpose multi-input channel 3.3V analog to digital converter (ADC). The ADC can be configured to be used as:

• 8-bit resolution ADC.
• 9-bit resolution ADC. The result of the conversion will always be a 9-bit word; the difference between the two configurations is that, to speed up the conversion, the resolution is reduced when the ADC is used in the 8-bit resolution mode. The ADC is seen at software level as a 2 channel ADC with different programmable sample times; a finite state machine will sample the requests done through the SPI interface on both the channel and will execute them in sequence. When used as 8-bit resolution the ADC can achieve a higher throughput and, if the minimum sample time is used, one conversion is completed in t = 5.5 µs. When used as 9-bit resolution ADC the circuit is slower and the minimum sample times are disabled. In that case the conversion will be completed in a time t= 10 µs. The use of ADC type must be decided at the start-up by writing in the one time programmable ADC configuration register; no A/D conversion will be enabled if this register is not set from last power-up sequence. This ADC can be used to measure some external pins as well as some L6460’s internal voltages. The converter is based on a cyclic architecture with an internal sample-and-hold circuit. Sample time can be changed using serial interface to enable good measure of higher impedance sources.

Figure 24. A2D block diagram The A2D system is enabled by setting the A2DEnable bit to ‘1’ in the A2DControl register. resolution or 9-bit) according to the Table 30. Table 30. ADC truth table

0 X Disabled

are reported in Table 32 and Table 33. Table 31. Channel addresses 00000 V Supply scaled See voltage divider specification. 00001 V SupplyInt scaled See voltage divider specification.

00010 V ref_2_5V

00011 Temp Sensor1 Temperature sensor1

00100 Temp Sensor2 Temperature sensor2

3v3 scaled See voltage divider specification.

01000 Not used

01001 GPIO[0]

01010 GPIO[1]

01011 GPIO[2]

01100 GPIO[3]

01101 GPIO[4]

01110 GPIO[5]

01111 GPIO[6]

10000 GPIO[7]

10001 GPIO[8] clamp See current DAC circuit

10010 GPIO[9]

10011 GPIO[10]

10100 GPIO[11]

10101 GPIO[12]

10110 GPIO[13]

10111 GPIO[14]

11000 MuxRefOpAmp1

11001 MuxRefOpAmp2

11010 OutStripStepperPhA

11011 OutStripStepperPhB

11100 Not used

11101 ST reserved References AUX1 switching reg.

registers and L6460 will not accept other conversion request on that channel. channel address cannot be changed. the A2Dcontinuous1 and A2Dcontinuous2 bits; the conversions are made in sequence. Table 32. ADC sample times when working as a 8-bit ADC Table 33. ADC sample time when working as a 9-bit ADC

15.1 Voltage divider specifications

working range, they are scaled with a resistor divider before the conversion. Table 34. Voltage divider specification

16 Current DAC circuit

selected using the DacRange[1:0] bits in the CurrDacCtrl register. current of half microampere from the pin during the sampling time. Figure 25. Current DAC block diagram

where N is the value of DacValue[5:0] bits. Table 35. Current DAC truth table

17 Operational amplifiers

in Figure 26 are reported the block diagrams of the two operational amplifiers. Figure 26. Configurable 3.3 V operational amplifiers sure not to enable the path between one of these voltage references and the external pin.

Operational amplifiers L6460 88/139 Doc ID 17713 Rev 1 The operational amplifiers are capable to drive a capacitive load in buffer configuration up to a maximum of 100 pF; for higher capacitance it is necessary to add resistive loads to increase the OP output current, and/or to add a low resistor (10 Ω) in series to the load capacitance. To use the operational amplifiers as comparators the user must disable internal compensation writing a logic one in the OpXDisComp bit in the OpAmpXCtrl register.

18 Low voltage power switches

therefore the user will find a limit flag that must be cleared. GPIO_SPI, they never inject current on this pin. Figure 27. Low power switch block diagram

19 General purpose PWM

L6460 includes three general purpose PWM generators that can be redirected on GPIO pins (see Chapter 22). Two of these generators (Aux_PWM_1 and Aux_PWM_2) work with a fixed period FOSC/512 and have a programmable duty cycle; the other one (GP_PWM) has a programmable base time clock and a programmable time for both high and low levels.

19.1 General purpose PWM generators 1 and 2 (AuxPwm1 and

AuxPwm2) The Duty cycle of these PWM generators can be changed by writing the AuxPwmXCtrl bits (where X can be 1 or 2) in the AuxPwm1Ctrl and AuxPwm2Ctrl registers. Their positive duty cycle will change according to the equation: According to this equation a programmed “0” value will cause a 0% duty cycle (output always at logic level 0).

19.2 Programmable PWM generator (GpPwm)

GpPWM has a programmable base clock that can be changed by programming the GpPwmBase[6:0] bits in the GpPwmBase register. The clock will change according to the equation: The high and low level duration (expressed in base clock periods), can be programmed writing the GpPwmHigh[7:0] and GpPwmLow[7:0] bits in the GpPwmCtrl register so they will change according to following equations: The resulting period of the PWM will be: and the positive duty cycle will result: A programmed value of 0 in GpPwmHigh[7:0] and GpPwmLow[7:0] bits will force the PWM generator output to be always at logic level “0”. PWM_X_DUTY AuxPwmXCtrl 9:0 [] /512= PWM_BASE_PERIOD GpPwmBase 6:0 [] 1+() Tosc×= High_level_Time GpPwmHigh 7:0[] PWM_BASE_PERIOD×= Low_level_Time GpPwmLow 7:0[] PWM_BASE_PERIOD×= Period GpPwmHigh 7:0[] GpPwmLow 7:0[]+() PWM_BASE_PERIOD+= DutyCycle High_level_Time

20 Interrupt controller

be signaled directly to the external circuits. Figure 28. Interrupt controller diagram The Table 36 contains the events that can be monitored by the interrupt controller. Table 36. Interrupt controller event SwRegCtrl Ilimit Switching regul ator controller Ilimit event. VMainSW Ilimit Main switching regulator Ilimit event. LowPowSw 1 Low voltage power switch 1 Ilimit event.

enable bit in the interrupt controller configuration register (IntCrtlCfg). The GPIO output of this circuit can be programmed to be active high or active low. Vloop1Ilim AUX1 Ilimit event.

1. This event is disabled if the related ADC channel is configured in continuous mode.

Table 36. Interrupt controller event (continued)

21 Digital comparator

L6460 includes one digital comparator that can be used to signal, through serial interface, that a channel converted by the ADC is greater, greater-equal, lesser, lesser equal, or equal than a fixed value set by serial interface or than the value converted by the other ADC channel. This circuit can be used to monitor the temperature of the IC advising the firmware when it reaches a certain value decided by the firmware by setting one ADC channel to do continuous conversions of the temperature sensor. The circuit operation can be enabled or disabled changing the EnDigCmp bit in the configuration register DigCmpCfg. By setting the DigCmpUpdate[1:0] bits in the configuration register, the comparator can be programmed to update its output in one of the following ways:

• DigCmpUpdate[1:0]=00 – Continuously (each clock).
• DigCmpUpdate[1:0]=01 – Each time a conversion is performed on ADC channel 0.
• DigCmpUpdate[1:0]=10 – Each time a conversion is performed on ADC channel 1.
• DigCmpUpdate[1:0]=11 – ADC state machine driven. When the last option is selected, the digital comparator will update its output in two different ways depending on the configuration of the ADC converter. If ADC converter is configured to do continuous conversions on both channels, the output of the comparator will be updated when the double conversion is completed. If ADC converter is not configured to do continuous conversions on both channels, the output of the comparator will be updated each time a conversion is completed. The comparator output can be digitally filtered so that the programmed condition has to be found for three consecutive checks before to be signaled. The Figure 29 shows the block diagram of digital comparator.

Figure 29. Digital comparator block diagram In Table 37 is reported the comparison type truth table. In Table 38 is reported the Data0/Data1 selection truth table. Table 37. Comparison type truth table

0 X X Disabled

Table 38. DataX selection truth table

0 X DigCmpValue[9:0]

22 GPIO pins

body diode between output and supply. All digital output signals can be inverted before being provided on the relative GPIO pins. Here below is reported the table with GPIO functions. Table 39. GPIO functions description

1. In this table are used the abbr eviations of the following In Table 40.
2. GPIO[8] input Schmitt trigger is disabled by default (after a reset) to be able to read the digital value from this pin it needs

to be enabled writing a logic ‘1’ in the EnGpio8DigIn in CurrDacCtrl register. Table 39. GPIO functions description (continued)

Table 40. Abbreviations ADC input Input to the ADC system. SPI IN Digital state of this pin is readable through SPI. SPI OUT Digital state of this pin can be set through SPI. BB Back to back high side driver. Comp1 IN - This pin can be used as minus input for comparator 1. Comp2 IN - This pin can be used as minus input for comparator 2. regulator obtained by using bridge 4. STEP_REQ This pin can be used to reques t a stepper sequencer evolution step. Interrupt Ctrl This pin can be used to carry out the interrupt controller circuit output. IN PWM This pin can be used to provide an external PWM to bridges. Comp1 OUT This pin can be used as output of the comparator 1. AuxPwm1 This pin can be used to carry out the PWM generated by AuxPwm1 circuit. Low Volt. Pow. Sw. 1 This pin can be used as output of low voltage power switch 1. Comp2 OUT This pin can be used as output of the comparator 2. AuxPwm2 This pin can be used to carry out the PWM generated by AuxPwm2 circuit. Low Volt. Pow. Sw. 2 This pin can be used as output of low voltage power switch 2. AuxPwm3 This pin can be used to carry out the PWM generated by AuxPwm3 circuit. CurrDAC This pin can be used to carry out the output of the current DAC circuit. AuxPwm4 This pin can be used to carry out the PWM generated by AuxPwm4 circuit. OpAmp1 in+ This pin can be used as operational amplifier 1 non-inverting input. OpAmp1 in- This pin can be used as operational amplifier 1 inverting input. OpAmp1 Out This pin can be used as operational amplifier 1 output. OpAmp2 in+ This pin can be used as operational amplifier 2 non-inverting input. OpAmp2 in- This pin can be used as operational amplifier 2 inverting input.

Hereafter are reported the detailed specifications for each GPIO. must be enabled in GpioOutEnable register. OpAmp2 Out This pin can be used as operational amplifier 2 output. ID 1 This pin is used to determine the SPI ID1 bit value. ID 2 This pin is used to determine the SPI ID2 bit value. Slave Control This pin is used as slave co ntrol when the IC is configured as master. Table 40. Abbreviations (continued)

22.1 GPIO[0]

The GPIO[0] truth table is (for the abbreviation list please refer to Table 40). Table 41. GPIO[0] truth table

1 X X X X Detection of StartUp config See

1. In all configurations in whic h GPIO[0] is enabled as output:

c) the GPIO[0] pin is an open drain output.

Figure 30. GPIO[0] block diagram

22.2 GPIO[1]

The GPIO[1] truth table is (for the abbreviation list please refer to Table 40). Table 42. GPIO[1] truth table

1 XXX X A U X 1 F B (1)

1. AUX1Enable or AUX1System bit =1 represent the case in which AUX1 is used as a system or not system
2. In all configurations in whic h GPIO[1] is enabled as output:

c) the GPIO[1] pin is an open drain output.

Figure 31. GPIO[1] block diagram

22.3 GPIO[2]

The GPIO[2] truth table is (for the abbreviation list please refer to Table 40). Table 43. GPIO[2] truth table

1 XXX X A U X 2 F B (1)

1. AUX2Enable or AUX2System bit =1 represent the case in which AUX1 is used as a System or Not System
2. In all configurations in whic h GPIO[2] is enabled as output:

d) the GPIO[2] pin is an open drain output.

Figure 32. GPIO[2] block diagram

22.4 GPIO[3]

The GPIO[3] truth table is (for the abbreviation list please refer to Table 40). Table 44. GPIO[3] truth table

1. In all configurations in whic h GPIO[3] is enabled as output:

c) the GPIO[3] pin is an open drain output.

Figure 33. GPIO[3] block diagram

22.5 GPIO[4]

The GPIO[4] truth table is (for the abbreviation list please refer to Table 40). Table 45. GPIO[4] truth table

1. In all configurations in whic h GPIO[4] is enabled as output:

c) the GPIO[4] pin is an open drain output.

Figure 34. GPIO[4] block diagram

22.6 GPIO[5]

The GPIO[5] truth table is (for the abbreviation list please refer to Table 40). Table 46. GPIO[5] truth table

1. Master bit is at logic level “1” when L6460 is used as a master device (seeChapter 8)
2. This bit is at logic level “1” if AUX1 regulator is a system regulator but its power stage is externally realized

1 X X X X X Slave control

1. In all configurations in whic h GPIO[5] is enabled as output:

c) the GPIO[5] pin is a rail to ra il, back to back output supplied by V3v3.

Figure 35. GPIO[5] block diagram

22.7 GPIO[6]

Table 47. GPIO[6] truth table

1. When EnLowVSw[1]= ‘1’ the GpioOutEnable[6] bit is forced to 0.
2. In all configurations in whic h GPIO[6] is enabled as output:

c) the GPIO[6] pin is a rail to rail output supplied by VGPIO_SPI.

Figure 36. GPIO[6] block diagram

22.8 GPIO[7]

The GPIO[7] truth table is (for the abbreviation list please refer to Table 40). Table 48. GPIO[7] truth table

1. When EnLowVSw[2] = ‘1’ the GpioOutEnable[7] bit is forced to 0.
2. In all configurations in whic h GPIO[7] is enabled as output:

c) the GPIO[7] pin is a rail to rail output supplied by VGPIO_SPI.

Figure 37. GPIO[7] block diagram

22.9 GPIO[8]

The GPIO[8] truth table is (for the abbreviation list please refer to Table 40). Table 49. GPIO[8] truth table

1. The EnDAC bit in the CurrDacCtrl register enables the Current DAC (see Chapter 17)
2. This pin is 5 volt input tolerant.

1 X X X X CurrDAC (3)

1. When EnDAC = ‘1’ the GpioOutEnable[8] bit is forced to 0. The current DAC circuit is directly connected to

GPIO[8] pin so as soon as it is enabled it will sink current from pin.

1. The GPIO[8] pin can be always us ed as a digital input so its value can be always read through SPI

Figure 38. GPIO[8] block diagram

22.10 GPIO[9]

The GPIO[9] truth table is (for the abbreviation list please refer to Table 40). Table 50. GPIO[9] truth table

1. The Op1EnPlusPin bit in the OpAmp1Ctrl register enabl es the connection of the positive input of Op1 to
2. The GPIO[9] pin is used by the system w hen firmware requires the ID read action (Chapter 25)
3. When Op1EnPlusPin = ‘1’ the GpioOutEnable[9] bit is forced to 0.
4. In all configurations in whic h GPIO[9] is enabled as output:

d)the GPIO[9] pin is a rail to rail output supplied by VGPIO_SPI.

Figure 39. GPIO[9] block diagram

22.11 GPIO[10]

The GPIO[10] truth table is (for the abbreviation list please refer to Table 40). Table 51. GPIO[10] truth table

1. The Op1EnMinusPin bit in the OpAm p1Ctrl register enables the connection of the positive input of Op1 to
2. The GPIO[10] pin is used by the system w hen firmware requires the ID read action (Chapter 25)

1 X XXX O p A m p 1 i n - (3)

1. When Op1EnPlusPin = ‘1’ the Gpio OutEnable[10] bit is forced to 0.
2. In all configurations in which GPIO[10] is enabled as output:

d) the GPIO[10] pin is a rail to rail output supplied by VGPIO_SPI.

Figure 40. GPIO[10] block diagram

22.12 GPIO[11]

The GPIO[11] truth table is (for the abbreviation list please refer to Table 40). Table 52. GPIO[11] truth table

1. The EnOp1 bit in the OpAmp1Ctrl regi ster enables the operational amplifier 1.

1 X X X X OpAmp1 Out (2)

1. When EnOp1 = ‘1’ the GpioOutEnable[11] bit is forced to 0.
2. In all configurations in which GPIO[11] is enabled as output:

d) the GPIO[11] pin is a rail to rail output supplied by VGPIO_SPI.

Figure 41. GPIO[11] block diagram

22.13 GPIO[12]

The GPIO[12] truth table is (for the abbreviation list please refer to Table 40. Table 53. GPIO[12] truth table

1. AUX2Enable or AUX2System bit =1 represent the case in which AUX2 is used as a regulator (system or

1 X X X X X RegLoop2

01 X X X X O p A m p 2 i n + (2)

1. When Op2EnPlusPin = ‘1’ the Gpio OutEnable[11] bit is forced to 0.
2. In all configurations in which GPIO[12] is enabled as output:

d) the GPIO[12] pin is a rail to ra il, back to back output supplied by VGPIO_SPI.

Figure 42. GPIO[12] block diagram

22.14 GPIO[13]

The GPIO[13] truth table is (for the abbreviation list please refer to Table 40). Table 54. GPIO[13] truth table

1. The Op2EnMinusPin bit in the OpAm p2Ctrl register enables the connection of the positive input of Op1 to
2. When Op2EnMinusPin = ‘1’ the Gpio OutEnable[13] bit is forced to 0.
3. In all configurations in whic h GPIO[9] is enabled as output:

c) the GPIO[13] pin is a rail to rail output supplied by VGPIO_SPI.

Figure 43. GPIO[13] block diagram

22.15 GPIO[14]

The GPIO[14] truth table is (for the abbreviation list please refer to Table 40). Table 55. GPIO[14] truth table

1. The EnOp2 bit in the OpAmp2Ctrl regi ster enables the operational amplifier 2.

1 X XXX O p A m p 2 O u t (2)

1. When EnOp2 = ‘1’ the GpioOutEnable[14] bit is forced to 0.
2. In all configurations in which GPIO[14] is enabled as output:

c) the GPIO[14] pin is a rail to rail output supplied by VGPIO_SPI.

Figure 44. GPIO[14] block diagram

Doc ID 17713 Rev 1 129/139

23 Serial interface

L6460 can communicate with an external microprocessor by using an integrated slave SPI (serial protocol interface). Through this interface almost all L6460 functionalities can be controlled and all the ICs can be seen as a register map made by 128 register of 16-bit each. The SPI is a simple industry standard communications interface commonly used in embedded systems and it has the following four I/O pins: – MISO (master input slave output) – MOSI (master output slave input) – SCLK (serial clock [controlled by the master]) – nSS (slave select active low [controlled by the master]) The “MISO” (master in, slave out) signal carries synchronous data from the slave to the master device. The MOSI (master out, slave in) signal carries synchronous data from the master to the slave device. The SCLK signal is driven by the master, synchronizing all data transfers. Each SPI slave device has one nSS signal that is an active-low slave input/master output pin. Slave devices do not respond to transactions unless their nSS input signal is driven low. Master device interfacing with multiple SPI slave devices has an nSS signal for each slave device. L6460 will maintain its MISO pin in high impedance until it does not recognize its address in serial frame.

23.1 Read transaction

A read transaction (see Figure 45) is always started by the master device that lowers the nSS pin. The other bits are then sent on the MOSI pin with this order: 1. 7-bit representing the address of the register that must be read (MSB first [A 6…A 0]); 2. 2-bit that must be “10” for a read transaction; 3. 2-bit representing L6460 IC address; 4. 1-bit reserved for future use that must be set at “0”. At this point the data stored in the register at the selected address will be shifted out on the MISO pin. The read operation is terminated by raising the signal on nSS pin.

Figure 45. SPI read transaction

23.2 Write transaction

1. 7-bit representing the address of the register that must be written (MSB first [A6…A0]);
2. 2-bit that must be “01” for a read transaction;
3. 2-bit representing L6460 IC address;
4. 1-bit reserved for future use that must be set at “0”.

on rising edge of the nSS line. Figure 46. SPI write transaction

24 Registers list

Table 56. Register address map

Table 56. Register address map (continued)

25 Schematic examples

Figure 49. Application with 2 DC motors, 1 stepper motor and 3 power supplies

Figure 50. Application with 2 DC motors, a battery charger and 5 power supplies

specifications, grade definitions and product status are available at: www.st.com. Figure 51. TQFP64 mechanical data an package dimensions

Table 57. Document revision history 02-Jul-2010 1 Initial release.