L6392 STMICROELECTRONICS | Alldatasheet
Document overview
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- PDF pages: 19
Technical content
Datasheet sections
- 1 Block diagram
- 2 Pin connection
- 3 Truth table
- 4 Electrical data
- 4.1 Absolute maximum ratings
- 4.2 Thermal data
- 4.3 Recommended operating conditions
- 5 Electrical characteristics
- 5.1 AC operation
- 5.2 DC operation
- 6 Waveforms definitions
- 7 Typical application diagram
- 8 Bootstrap driver
- 8.1 CBOOT selection and charging
- 9 Package mechanical data
- 10 Revision history
Features
■ High voltage rail up to 600 V ■ dV/dt immunity ± 50 V/nsec in full temperature range ■ Driver current capability: – 270 mA source – 430 mA sink ■ Switching times 75/35 nsec rise/fall with 1 nF load ■ 3.3 V, 5 V TTL/CMOS inputs with hysteresis ■ Integrated bootstrap diode ■ Operational amplifier for advanced current sensing ■ Adjustable dead-time ■ Interlocking function ■ Compact and simplified layout ■ Bill of material reduction ■ Flexible, easy and fast design Application
Description
The L6392 is a high-voltage device, manufactured with the BCD “OFF-LINE" technology. It has a monolitich half-bridge gate driver for N-channel Power MOSFET or IGBT. The high side (floating) section is designed to stand a voltage rail up to 600 V. The logic inputs are CMOS/TTL compatible down to 3.3 V for easy of interfacing microcont roller/DSP The IC embeds an op amp suitable for advanced current sensing in applications such as field oriented motor control. DIP-14 SO-14 Table 1. Device summary
1 Block diagram
Figure 1. Block diagram
2 Pin connection
Figure 2. Pins connection (top view) Table 2. Pin description
3 HIN I High side driver logic input (active high)
4 VCC P Lower section supply voltage
5 DT I Dead time setting
6 OPOUT O Opamp output
7 GND P Ground
8 OP+ I Opamp non inverting input
9 OP- I Opamp inverting input
10 LVG
- The circuit guarantees less than 1 V on the LV G and HVG pins (@ Isink = 10 mA), with VCC > 3 V. This
MOSFET normally used to hold the pin low; the gate driver assures low impedance also in SD condition.
11 NC Not connected
12 OUT P High side (floating) common voltage
13 HVG (1) O High side driver output
14 BOOT P Bootstrapped supply voltage
8 OP+
3 Truth table
Table 3. Truth table
4 Electrical data
4.1 Absolute maximum ratings
4.2 Thermal data
4.3 Recommended operating conditions
Table 4. Absolute maximum rating Table 5. Thermal data Table 6. Recommended operating conditions
- If the condition TBDV< V boot - Vout < TBD V and Vboot < TBD V are guaranteed, Vout can range from TBD V
14 Floating supply voltage (1) TBD TBD V
5 Electrical characteristics
5.1 AC operation
Figure 3. Timing characteristics Table 7. AC operation electrical characteristics (V CC = 15V; TJ =+25 °C)
5.2 DC operation
Table 8. DC operation electrical characteristics (V CC = 15 V;TJ = +25 °C)
- R DSon is tested in the following way:
Table 9. OPAMP characteristics (V CC = 15 V, TJ = +25 °C)
- The direction of input current is out of the IC.
6 Waveforms definitions
Figure 4. Dead time - timing waveforms
7 Typical application diagram
Figure 5. Application diagram
8 Bootstrap driver
A bootstrap circuitry is needed to supply the high voltage section. This function is normally accomplished by a high voltage fast recovery diode (Figure 6 a). In the L6392 a patented integrated structure replaces the external diode. It is realized by a high voltage DMOS, driven synchronously with the low side driver (LVG), with diode in series, as shown in Figure 6 b. An internal charge pump (Figure 6 b) provides the DMOS driving voltage.
8.1 C BOOT selection and charging
To choose the proper CBOOT value the external MOS can be seen as an equivalent capacitor. This capacitor CEXT is related to the MOS total gate charge: The ratio between the capacitors CEXT and CBOOT is proportional to the cyclical voltage loss. It has to be: CBOOT >>> CEXT e.g.: if Qgate is 30 nC and Vgate is 10 V, CEXT is 3 nF . With CBOOT = 100 nF the drop would be 300 mV. If HVG has to be supplied for a long time, the CBOOT selection has to take into account also the leakage and quiescent losses. e.g.: HVG steady state consumption is lower than 200 µA, so if HVG TON is 5 ms, CBOOT has to supply 1 µC to CEXT. This charge on a 1µF capacitor means a voltage drop of 1 V. The internal bootstrap driver gives agreat advantage: the external fast recovery diode can be avoided (it usually has great leakage current). This structure can work only if VOUT is close to GND (or lower) and in the meanwhile the LVG is on. The charging time (Tcharge ) of the CBOOT is the time in which both conditions are fulfilled and it has to be long enough to charge the capacitor. The bootstrap driver introduces a voltage drop due to the DMOS RDSON (typical value: 120 Ω). At low frequency this drop can be neglected. Anyway increasing the frequency it must be taken in to account. The following equation is useful to compute the drop on the bootstrap DMOS: where Qgate is the gate charge of the external power MOS, Rdson is the on resistance of the bootstrap DMOS, and Tcharge is the charging time of the bootstrap capacitor. CEXT Qgate Vgate Vdrop Ich earg Rdson Vdrop→ Qgate Tch earg
Figure 6. Bootstrap driver
9 Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com
Figure 7. DIP-14 mechanical data and package dimensions
Figure 8. SO-14 mechanical data and package dimensions
Table 10. Document revision history