L6385ED STMICROELECTRONICS | Alldatasheet

Document overview

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  • PDF pages: 16

Technical content

Datasheet sections

  • 1 Electrical data
  • 1.1 Absolute maximum ratings
  • 1.2 Thermal data
  • 1.3 Recommended operating conditions
  • 2 Pin connection
  • 3 Electrical characteristics
  • 3.1 AC operation
  • 3.2 DC operation
  • 3.3 Timing diagram
  • 4 Bootstrap driver
  • 4.1 CBOOT selection and charging
  • 5 Typical characteristic
  • 6 Package mechanical data
  • 7 Order codes
  • 8 Revision history

Features

■ High voltage rail up to 600V ■ dV/dt immunity ±50V/nsec in full temperature range ■ Driver current capability: – 400mA source, – 650mA sink ■ Switching times 50/30 nsec rise/fall with 1nF load ■ CMOS/TTL Schmitt trigger inputs with hysteresis and pull down ■ Under voltage lock out on lower and upper driving section ■ Internal bootstrap diode ■ Outputs in phase with inputs

Description

The L6385E is an high-voltage device, manufactured with the BCD"OFF-LINE" technology. It has an Half - Bridge Driver structure that enables to drive independent referenced N Channel Power MOS or IGBT. The High Side (Floating) Section is enabled to work with voltage Rail up to 600V. The Logic Inputs are CMOS/TTL compatible for ease of interfacing with controlling devices. DIP-8 SO-8 Figure 1. Block diagram

1 Electrical data

1.1 Absolute maximum ratings

1.2 Thermal data

1.3 Recommended operating conditions

Table 1. Absolute maximum ratings Table 2. Thermal data Table 3. Recommended operating conditions

  1. If the condition Vboot - Vout < 18V is guaranteed, Vout can range from -3 to 580V

8 Floating supply voltage (1) 17 V

2 Pin connection

Figure 2. Pin connection (Top view) Table 4. Pin description

1 LIN I Low side driver logic input

2 HIN I High side driver logic input

3 V cc Low voltage power supply

4 GND Ground

5 LVG (1)

  1. The circuit guarantees 0.3V maximum on the pin (@ Isink = 10mA). This allows to omit the "bleeder"

6 VOUT O High side driver floating reference

7 HVG (1) O High side driver output

8 V boot Bootstrap supply voltage

4 LVG

3 Electrical characteristics

3.1 AC operation

3.2 DC operation

Table 5. AC operation electrical characteristcs (VCC = 15V; TJ = 25°C) Table 6. DC operation electrical characteristcs (VCC = 15V; TJ = 25°C)

3.3 Timing diagram

Figure 3. Input/output timing diagram

  1. R DS(on) is tested in the following way:

Table 6. DC operation electrical characteristcs (continued)(VCC = 15V; TJ = 25°C)

4 Bootstrap driver

A bootstrap circuitry is needed to supply the high voltage section. This function is normally accomplished by a high voltage fast recovery diode (Figure 4 a). In the L6385E a patented integrated structure replaces the external diode. It is realized by a high voltage DMOS, driven synchronously with the low side driver (LVG), with in series a diode, as shown in Figure 4 b. An internal charge pump (Figure 4 b) provides the DMOS driving voltage. The diode connected in series to the DMOS has been added to avoid undesirable turn on of it.

4.1 C BOOT selection and charging

To choose the proper CBOOT value the external MOS can be seen as an equivalent capacitor. This capacitor CEXT is related to the MOS total gate charge: The ratio between the capacitors CEXT and CBOOT is proportional to the cyclical voltage loss. It has to be: CBOOT>>>CEXT e.g.: if Qgate is 30nC and Vgate is 10V, CEXT is 3nF . With CBOOT = 100nF the drop would be 300mV. If HVG has to be supplied for a long time, the CBOOT selection has to take into account also the leakage losses. e.g.: HVG steady state consumption is lower than 200µA, so if HVG TON is 5ms, CBOOT has to supply 1µC to CEXT. This charge on a 1µF capacitor means a voltage drop of 1V. The internal bootstrap driver gives great advantages: the external fast recovery diode can be avoided (it usually has great leakage current). This structure can work only if VOUT is close to GND (or lower) and in the meanwhile the LVG is on. The charging time (Tcharge ) of the CBOOT is the time in which both conditions are fulfilled and it has to be long enough to charge the capacitor. The bootstrap driver introduces a voltage drop due to the DMOS RDSON (typical value: 125 Ω). At low frequency this drop can be neglected. Anyway increasing the frequency it must be taken in to account. The following equation is useful to compute the drop on the bootstrap DMOS: where Qgate is the gate charge of the external power MOS, Rdson is the on resistance of the bootstrap DMOS, and Tcharge is the charging time of the bootstrap capacitor. CEXT Qgate Vgate Vdrop Ich earg Rdson Vdrop→ Qgate Tch earg

Figure 4. Bootstrap driver

5 Typical characteristic

Figure 5. Typical rise and fall times vs Figure 6. Quiescent current vs supply Figure 7. Turn on time vs temperature Figure 8. Turn Off time vs temperature Figure 9. VBOOT UV turn On threshold Figure 10. Vcc UV turn Off threshold vs

6 Package mechanical data

In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com

Figure 15. DIP-8 mechanical data and package dimensions

Figure 16. SO-8 mechanical data and package dimensions exceed 0.15mm in total (both side).

  1. Dimension “E1” does not include interlead flash

7 Order codes

Table 7. Order codes

8 Revision history

Table 8. Document revision history