L6374FP013TR

L6374_08 STMICROELECTRONICS | Alldatasheet

Document overview

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Technical content

Datasheet sections

• 1 Maximum ratings
• 2 Pin connections
• 3 Electrical characteristics
• 4 Thermal characteristics
• 4.1 RthJP
• 4.2 RthJA1
• 4.3 RthJA2
• 5 Overtemperature protection (OVT)
• 6 Undervoltage protection (UV)
• 7 Diagnostic logic
• 8 Programmable delay
• 9 Analog inputs (I1,I2,I3,I4)
• 10 State / push-pull input
• 11 The switching of the output stag e
• 12 Application note
• 13 Package mechanical data
• 14 Revision history

Features

■ Four independent line drivers with 100 mA up to 35 V outputs ■ Input signals between - 7 V and + 35 V, with pre-setting threshold ■ Push-pull outputs with three state control and true zero current between Vs and ground ■ Current limiting on each output effective in the full "ground to Vs" output voltage range ■ Output voltage clamp to Vs and to ground ■ Overtemperature and undervoltage protections ■ Diagnostic for overtemperature, undervoltage and overcurrent ■ Pre-setting delay for overcurrent diagnostic ■ High speed operation: up to 300 kHz with 35 V swing

Description

The L6374 is especially designed to be used as a line driver in industrial control systems based on the 24 V signal levels (IEC 61131, 24VDC). Table 1. Device summary Figure 1. Block diagram

1 Maximum ratings

2 Pin connections

Figure 2. Pins connection (top view) Table 2. Absolute maximum ratings

3 Electrical characteristics

Table 3. Electrical characteristics

Table 3. Electrical characteristics (continued)

4 Thermal characteristics

4.1 R thJP

and the soldering joint with the PCB footprint can be made.

4.2 R thJA1

considered on the bottom side of an horizontal PCB (worst case).

4.3 R thJA2

takes place through still air and through the PCB itself. Table 4. Thermal data

Figure 3. Printed heatsink

Overtemperature protection (OVT) L6374

5 Overtemperature protection (OVT)

If the chip temperature exceeds Th (measured in a central position in the chip) the chip deactivates itself. The following actions are taken:

• all the output stages are forced in the "three state" condition, i.e. are disconnected from the output pins; only the clamping diodes at the outputs remain active;
• the signal Diag is activated (active low). Normal operation is resumed as soon as (typically after some seconds) the chip temperature monitored goes back below Th -HT. The different upper and lower thresholds with hysteretic behavior, assure that no intermittent conditions can be generated.

6 Undervoltage protection (UV)

The supply voltage is expected to range from 11 V to 35 V, even if its reference value is considered to be 24 V. In this range the L6374 operates correctly. Below 10.8 V the overall system has to be considered not reliable. Consequently the supply voltage is monitored continuously and a signal, called UV, is internally generated and used. The signal is "on" as long as the supply voltage does not reach the upper internal threshold of the V s comparator (called Vsh). The UV signal disappears above Vsh. Once the UV signal has been removed, the supply voltage must decrease below the lower threshold (i.e. below Vsh -Hys1) before it is turned on again. The hysteresis Hys1 is provided to prevent intermittent operation of the device at low supply voltages that may have a superimposed ripple around the average value. The UV signal inhibits the outputs, putting them in three-state, but has no effect on the creation of the reference voltages for the internal comparators, nor on the continuous operation of the charge-pump circuits.

7 Diagnostic logic

The situations that are monitored and signalled with the Diag output pin are:

• current limit (OVC) in action; there are 8 individual current limiting circuits, two per each output, i.e. one per every output transistor; they limit the current that can be either sour- ced or sunk from each output, to a typical value of 150 mA, equal for all of them;
• undervoltage protection (UV);
• overtemperature protection (OVP); The diagnostic signal is transmitted via an open drain output (for ease of wired-or connection of several such signals) and a low level represents the presence of at least one of the monitored conditions, mentioned above.

8 Programmable delay

The current limiting circuits can be requested to perform even in absence of a real fault condition, for a short period, if the load is of capacitive nature or if it is a filament lamp (that exhibits a very low resistance during the initial heating phase). To avoid the forwarding of misleading, short diagnostic pulses in coincidence with the intervention of the current limiting circuits when operating on capacitive loads, a delay of about 5 µs is inserted on the signal path, between the "OR" of the current limit signals and its use as external diagnostic. It takes about 1µs to charge (or discharge) by 24 V a capacitor of 5 nF with a current of 120 mA . To implement longer delays (from the intervention of one of the current limiting circuits to the activation of the diagnostic) an external capacitor can be connected between pin C3 and ground (pin C3 is otherwise left open). The delay shall then be determined by the ratio of about 10 pF/µs, using the value of the capacitance connected to the pin.

9 Analog inputs (I1,I2,I3,I4)

The input stage of each channel is a high im-pedence comparator with built-in hysteresis (200 mV) for high noise immunity. Each comparator has one input connected to all the others and tied to a common pin Ref (Pin 11). If this pin is left floating an internal precise band gap voltage reference (1.25 V) is applied, otherwise these inputs can be externally programmed by connecting an external voltage source (from 0 to 5 V) and the current on this pin is internally limited to ±20 mA. The other input pin of each comparator can swing from -7 to 35 V. For this reason it has been implemented the structure shown in Figure 4 on page 10 and the device can also be used as line receiver. When the input voltage is negative, the current is internally limited by a 15 kΩ resistor as shown in Figure 4 on page 10. High and low input thresholds can be obtained by adding and subtracting half of the hysteresis to the voltage of pin Ref (see Figure 5 on page 10).

10 State / push-pull input

Figure 4. Equivalent input circuit Figure 5. Input comparator threshold

11 The switching of the output stage

interval of around 200 ns, the other transistor is turned on.

• delay from the input pin to the output reaction;
• OFF transition in the output stage;
• dead time
• on transition in the output stage.

Figure 6. V S = 35 V, 350 Ω connected to VS/2. easy to in terpret if the load has not the perfect symmetry of that case, as showed below. Figure 8 – show to hide some of the switching phases described. linger close to the supply voltage as long as possible.

It is recommended not to leave the Ref pin (pin 11) floating: if not used with an external voltage reference, it is better to connect an external capacitor (of at least 10 nF) between this pin and ground. This capacitor filters the voltage reference against voltage spikes that can be generated by the commutation of the output stages. This is very common using capacitive loads: in fact, the initial transient of such loads behaves like a short circuit, so the current flowing through the outputs presents very high spikes. Moreover, if the device is used as a line receiver. (i.e. the input signals can go below ground) it is required not to leave the Ref pin (pin 11) floating: in this case, the pin can be connected to ground or to a fixed external voltage reference.

Package mechanical data L6374 In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com

Table 5. SO-20 mechanical data Figure 12. Package dimensions

Table 6. Document revision history June 2004 2 Technical migration from ST -PRESS to EDOCS.