L6364

L6364 STMICROELECTRONICS | Alldatasheet

Document overview

• Manufacturer or author: STMICROELECTRONICS
• PDF pages: 60

Technical content

Datasheet sections

• 1 Description
• 2 Block Diagram
• 3 Package and pin-out
• 4 Technical Data
• 4.1 Absolute Maximum Ratings
• 4.2 Thermal Characteristics
• 4.3 Recommended operating conditioning
• 4.4 Electrical Characteristics
• 5 Startup
• 6 SPI Communication
• 6.1 Multiple byte exchange
• 7 DIO pin
• 7.1 DIO mode output control
• 7.2 SIO mode control
• 8 IO-Link UART peripheral
• 8.1 Multi-octet UART mode
• 8.1.1 SIO Mode
• 8.1.2 IO-Link mode
• 8.1.3 Transmit mode
• 8.1.4 IO-Link UART peripheral (Multi-octet mode) state machine
• 8.1.5 Interrupt handling
• 8.1.6 Data interrupt handling
• 8.1.7 Short-circuit, overtemperature and undervoltage interrupt handling
• 8.1.8 Interrupt handler structure
• 8.1.9 Changing to and from SIO mode
• 8.1.10 SPI register writes outside interrupt service routines
• 8.2 Single octet UART mode
• 8.2.1 Buffering
• 8.2.2 Receive mode
• 8.2.3 Transmit mode

Features

• Supply voltage from 5 V to 35 V
• 2.5 V to 5 V compatible I/Os
• 3.3 V and 5 V, 50 mA linear regulators
• 50 mA DC-DC regulator with configurable frequency (0.5 MHz to 2 MHz) & voltage (5 V to 10.5 V)
• Low dissipative (5 Ω) CQ and DIO output stages configurable in high side, low side, push/pull
• Configurable reporting threshold (0.11 A to 0.25 A) of current limitation for CQ and DIO lines
• Configurable reporting threshold (0.22 A to 0.5 A) of current limitation for CQ//DIO line (Join Mode)
• Fully protected: – Embedded reverse polarisation diode (D OUT pin) – Full zero current reverse polarity between V PLUS, CQ, DIO and PGND pins – Configurable (up to 216°C) thermal shutdown threshold – 7-bit, calibrated, temperature measurement – Configurable (6.0 V to 15 V) V PLUS undervoltage detection – CQ and DIO short-circuit current limit and reporting
• -40 to +150°C operating temperature
• Suitable to drive L, C and R loads
• Quartz-free IO-Link clock extraction and timing generation at COM2 (38.4k Baud) and COM3 (230.4k Baud)
• Integrated UART peripheral with M-sequence handling (inc. checksum) for all IO-Link sequences according to specification v1.1
• Multi octet UART mode for M-sequence size up to 15 octets
• Single octet UART mode for unlimited M-sequence size and continuous data transfer
• Transparent UART mode for special applications
• CQ and DIO switching time = 100 ns (2 kΩ//2.2 nF load)
• 8 V Zener limits for fast demagnetization of inductive loads
• Two LED drivers with configurable (up to 8 mA) current
• Design to meet application requirements: – ESD IEC 61000-4-2 protection to 4 kV – EMC protection against surge (500 Ω coupling) above ±2A/50 μs
• Smart format QFN-20L 4x4 mm and CSP-19 2.5x2.5 mm packages Application
• Industrial sensors
• Factory automation
• Process control Product status link L6364 Product summary Order code L6364Q L6364W Package QFN 20L CSP 19 Packing Tape & Reel Tape & Reel Dual channel transceiver IC for SIO and IO-Link sensor applications L6364 Datasheet DS13363 - Rev 4 - October 2021 For further information contact your local STMicroelectronics sales office.

1 Description

The L6364 is a dual channel transceiver for industrial sensor applications. It has been designed to support even the IO-Link standard and acts as a bridge between a microcontroller with a sensor or actuator function and a 24 V supply and signaling cable. In normal operation the L6364 is configured at start up by the microcontroller via the SPI interface. Typically, the L6364 then operates as a Single Input Output device driving the output lines as configured by the microcontroller. If the device is connected to an IO-Link master, then the master can initiate communication and exchange data with the microcontroller while the L6364 acts as a physical layer for the communication. The L6364 integrates a surge pulse suppressor circuit featuring the protection of the process side pins (VPLUS, CQ, DIO, PGND) against up to ±1.5 kV/50 us withstand pulses applied with 500 Ω coupling. Also, the same pins are protected against reverse polarity (Section 20 Surge pulse and reverse polarity protections). The two symmetrical input/output stages (CQ and DIO) can be used either for the communication through the 24 V data bus or to drive industrial loads. Each output stage can be configured (Hi-Z, High Side, Low Side, Push-Pull) and protected against overload by the ISET programmable threshold (110 mA to 250 mA). Also, the JOIN mode configuration allows to reduce power dissipation and to double overload threshold by shorting CQ and DIO on the application. The IC embeds two linear regulators (V3V3 and V5V) than can work either directly supplied by the external supply rail (VPLUS) or by the high efficiency and configurable (VSET, fSET) embedded DC-DC converter. The output voltage of the DC-DC can be used as additional supply rail for the application. The total current capability (IOUT) of the internal regulators and DC-DC is 50 mA. The logic core of the IC is internally supplied by the V3V3 rail and communicates with the external microcontroller by an SPI (slave) interface, an interrupt signal (INT) and direct driving of DIO line (CTLD). The VDIG pin defines the voltage rail of these digital signals: it enables the IC to work even with microcontroller supplied by different rails than V3V3. The internal logic embeds an IO-Link UART peripheral that can be configured by the microcontroller in one of the three possible options: Transparent, Single-octet or Multi-octet (Section 8 IO-Link UART peripheral). In Transparent mode the IC works purely as a physical layer between the microcontroller and the 24 V data bus: the workload for the management of the input/output data is fully demanded to the firmware running on the microcontroller. In Single-octet and Multi-octet modes the IC itself does a set of IO-Link required checks on the input/output data with consequent drastic reduction of the workload for the microcontroller. The Multi-octet is usually preferred when the data transfer with the IO-Link master can be managed by the available 8-bits registers buffer: the IC generates an interrupt to microcontroller when all data in the buffer are ready. If IO-Link data transfer exceeds the IC buffer capability, then Single-octet can be used instead: in this case the IC generates an interrupt at every octet ready. The L6364 offers two programmable pins (LED1 and LED2) acting as LED drivers with configurable current capability (up to 8 mA, each). L6364

Description

2 Block Diagram

Figure 1. Block Diagram

3 Package and pin-out

Figure 2. Package and pin-out - QFN Figure 3. Package and pin-out - CSP

Table 1. Pin Description

11 D1 VPLUS Line supply voltage PWR

14 B1 CQ Line data signal SIO/SDCI ANA IO

13 C1 DIO Line data signal DI/DO ANA IO

15 A1 PGND Switch ground return PWR

17 A3 MOSI SPI data, microcontroller to

19 A4 SS SPI synchronization, slave

20 B4 SCK SPI interface clock signal CI

18 B3 MISO SPI data, L6364 to

16 A2 INT Interrupt CO

1 A5 VDIG

10 B2 CTLD Direct control of DIO output

6 C3 LED1 LED1 source current ANA O

7 D5 LED2 LED2 source current ANA O

3 C4 V5V Sensor and microcontroller

2 B5 V3V3 PWR

9 D2 DOUT

8 D3 LOUT Inductor power feed ANA IO

5 D4 VDCDC

1. PWR: power, CI: CMOS input, CO: CMOS output, COZ: output with tristate function, ANA IO: Analogue input output, ANA
2. although the internal core of the IC is supplied by the V3V3, the full operation is guaranteed even when VDIG is connected

4 Technical Data

4.1 Absolute Maximum Ratings

under these conditions is not implied. All voltages are referenced to GND unless otherwise specified. Table 2. Absolute maximum ratings between the operating ratings and the absolute maximum ratings leads to a reduced operating lifetime.

4.2 Thermal Characteristics

Table 3. Thermal data

1. 2s, FR4, Cu thickness = 35 μm
2. 2s2p, FR4 under still air conditions

4.3 Recommended operating conditioning

Table 4. Recommended operating conditions

Symbol Parameter Min. Typ. Max. Unit VSUP VPLUS supply voltage, IV5V0= 50 mA, (DC-DC disabled) 6 24 35 V Minimum VPLUS (DC-DC enabled) (see Figure 15) 10.5 V VDCDC_5V_MIN Minimum VDCDC output voltage (VSET) for use of V5V 6.1 V CBLK Blocking capacitor on VPLUS 100 nF CEMC EMC blocking capacitor 470 pF CV3V3 Capacitor CV3V3 1 10 μF CV5V Capacitor CV5V (V5V in use) 1 10 μF CDOUT Capacitor CDOUT 0.01 1 μF CDCDC Capacitor CDCDC 2.2 uF LDCDC Inductor LDCDC 220 uH CQLOAD_MAX Maximum load capacitor CQ (see Figure 21)(1) 250 nF CDIOLOAD_MAX Maximum load capacitor DIO (see Figure 21) (1) 250 nF CJOINLOAD_MAX Maximum load capacitor JOIN mode (see Figure 22) (1) 500 nF LCQLOAD_MAX Maximum load inductance CQ (see Figure 21) (2) mH LDIOLOAD_MAX Maximum load inductance DIO (see Figure 21) (2) mH LJOINLOAD_MAX Maximum load inductance JOIN mode (see Figure 22) (2) mH 1. values measured with pure capacitive load. 2. unlimited, see Section 19 for further details.

4.4 Electrical Characteristics

Electrical parameters are valid over the operating temperature and voltage range, unless otherwise stated. Table 5. Receiver CQ/DIO Table 32. Register

Electrical Characteristics

Symbol Parameter Test Conditions Min. Typ. Max. Unit fCK Internal clock base -10% 10 +10% MHz Table 6. Short-circuit and Wake-up detection Figure 4. Example of Wake-up sequence timing (VCQ = green plot; ICQ = red plot; VINT = Yellow) Table 7. POR (Power On Reset) Table 8. Output switches individual channels CQ/DIO

Table 9. Line surge protection, parameters with respect to any pair PGND, CQ, DIO, VPLUS Table 10. Thermal shutdown Table 11. Digital pins Table 12. LED Driver

1. The current supplied by each LED pin can be configured between 0 to 8 mA by LED1[3:0] and LED2[3:0] of LED register

(address 0x07). One bit increment of LEDx[3:0] corresponds to +0.5 mA(typ). Table 13. Linear regulators

Symbol Parameter Test Condition Min. Typ. Max. Unit VV3V3 Regulator output voltage 0 mA < IV3V3 <50 mA 3.0 3.3 3.6 V VV5V Regulator output voltage 0 mA < IV5V < 50 mA 4.5 5.0 5.5 V IPD5V Pull-down current of V5V pin 50 100 200 μA VUV Undervoltage detect see Table 29, VUV < 10 V UVSET-1 UVSET UVSET+1 V VUV ≥ 10 V UVSET-10% UVSET UVSET+10% V Table 14. DC-DC supply DS13363 - Rev 4 page 10/60

5 Startup

L6364, including the control for the 5 V regulator, is supplied by the V3V3 supply. The SPI communication logic is reset whenever SS='1' and is independent of the L6364 power on reset itself. STATUS:RST bit is read as part of the STATUS byte on every SPI access. used as set out in Table 15 to determine the L6364 reset state, and also to react to unexpected reset conditions. Table 15. L6364 Reset conditions may wait for a high level on INT before proceeding. STATUS:RST='1' to allow normal operation of the L6364. The microcontroller should initialize the state of the internal registers to the desired values after reset.

6 SPI Communication

Internal registers (see Table 32. Register map) are provided to observe and control the L6364 state. internal core works at the V3V3 rail. only driven when the slave specific select line is SS='0', which allows other SPI slaves to share the same SPI bus. The MSB of the address byte is a WR/RDn bit, where a '1' indicates that each byte is written to the registers. Valid data is always made available on the MISO line independent of the WR/RDn bit. read operations, the level of the MOSI line is ignored for the data bytes. SS edge which synchronizes transmission, followed by a target register address byte. sent from the L6364 to the microcontroller. Figure 5. Register programming.

6.1 Multiple byte exchange

bytes are written on the rising SCK clock edge of the eighth bit of each byte. possible to both read and write the values of multiple register bytes in one operation. This is particularly useful with larger M-sequence types where there is limited time available for the SPI exchange.

Figure 6. Single byte and sequential byte accesses

7 DIO pin

• JOIN mode (DCTL:DIO bit = '0'). This is the default configuration for DCTL:DIO bit. The DIO/CQ outputs function together to provide a single, double drive strength, IO-Link conformal output. The outputs, DIO and CQ, must be externally shorted together. When in this mode, the DCTL:HS and DCTL:LS no longer have any effect on the output state.
• DIO mode (DCTL:DIO bit = '1'). The DIO line functions as independent high voltage digital input output pin. Setting bit DCTL:IEN in this mode, enables a signal level change interrupt, informing the microcontroller that a level change has occurred on the DIO line.

7.1 DIO mode output control

Table 16. DIO control via SPI-DCTL:EXT=’0’ to be a PNP, NPN or Push-Pull driver. Table 17. Direct DIO control via pin CTLD – DCTL:EXT=’1’ (low-side switch). This allows rapid switch-off for inductive loads. standard absolute levels are used, and where the bit is '1' the threshold is referred to VVPLUS/1.8.

7.2 SIO mode control

In the SIOActive state, the high-side or low-side switches are switched according to the CCTL:HS and CCTL:LS bits. It is not legal to switch on both simultaneously, and this register setting disables both switches. The high-side and low-side switches are identical, and have an on-state resistance of RSW. Any inactive switch acts as a Zener diode limiting the voltage on the CQ line to VZEN above VPLUS (high-side switch), or VZEN below GND (low-side switch). This allows rapid switch-off for inductive loads. L6364 SIO mode control DS13363 - Rev 4 page 15/60

8 IO-Link UART peripheral

The L6364 contains an IO-Link UART peripheral for bidirectional communication according to the IO-Link Standard. The peripheral is controlled, and data is exchanged, via SPI register accesses. In an application where pins CQ and DIO are coupled together i.e. JOIN mode, then a reference to CQ in the following refers to the shorted pair.

8.1 Multi-octet UART mode

8.1.1 SIO Mode

Figure 7 shows the IO-Link UART peripheral state machine. When the CCTL:SIO bit is set, the L6364 is set to Single Input Output mode. In this mode the L6364 has the following states:

• SIOActive: The CQ line is driven according to the setting of the HS and LS bits of CCTL register. The internal UART does not run in this state and so master messages are only detected if a wake-up request from the master is received, which switches the L6364 to the SIOListen state. If the output is set to high impedance (CCTL:HS=LS='0'), then the L6364 can not receive a wake-up request from the master. It is therefore necessary to switch to IO-Link mode (CCTL:SIO='0') if communication detection is required with a high impedance output.
• SIOListen: The L6364 has experienced a short-circuit via a wake-up request from the master. Both high-side and low-side switches are off, and the restart timer is running. Transitions on the CQ line are read as data, and stored in the data buffer (FR0 to FR14 registers). If a complete, valid, master message is received, then the state changes to Transmit, an interrupt is generated and the restart timer is reset. If the timer expires, then the L6364 returns to the SIOActive state and the CQ line is driven again after the transmission.

8.1.2 IO-Link mode

At startup, and if the SIO bit is cleared, the L6364 enters IO-Link mode. In this mode the L6364 has the following states:

• IOListen: Transitions on the CQ line are read as data, and stored in the data buffers. Once a complete master message has been read, or an error is experienced in reception (e.g. bad parity, checksum or time-out), then the state changes to Transmit.

8.1.3 Transmit mode

Following reception of an IO-Link master message the L6364 enters the following state:

• Transmit: The L6364 is waiting on data from the microcontroller, or is in the process of transmitting data on the CQ channel. The L6364 reverts to IOListen or SIOActive on completion of the transmission, or if an abort is generated by the microcontroller by setting END bit in the LINK register. If the L6364 has entered Transmit from an SIO mode, the microcontroller would normally now set the L6364 to IO-Link mode, such that the L6364 continues to listen for further information from the master. If the L6364 experiences a short-circuit during Transmit, then the STATUS:SSC bit is set, and the L6364 returns to either IOListen or SIOListen. L6364 IO-Link UART peripheral DS13363 - Rev 4 page 16/60

8.1.4 IO-Link UART peripheral (Multi-octet mode) state machine

Figure 7. IO-Link UART peripheral state machine

8.1.5 Interrupt handling

8.1.6 Data interrupt handling

If the STATUS:DAT bit is read as active (high) on an SPI access, then the L6364 is halted in a WAIT condition and is waiting for either a LINK:END or LINK:SND command from the microcontroller. While the L6364 is in the WAIT condition the interrupt pin (INT), the STATUS:INT bit and the STATUS:DAT bit remain active continuously. Data can be read and written to the L6364 registers while in the WAIT condition. Typically the LINK register and FR registers are accessed to read the incoming data, and the FR registers are written to set up the outgoing data. As the L6364 is halted, it doesn't generate further data interrupts in the WAIT condition. When the microcontroller sends either a LINK:END or LINK:SND command, the interrupt pin (INT), the STATUS:INT bit and the data bit, STATUS:DAT, are cleared within 220 ns of the last SCK edge of the SPI write access. If the microcontroller detects an active interrupt after the SPI access, or if the STATUS:DAT bit is read as active (high) on a subsequent SPI access, then new data is available. The LINK register is duplicated as LINK2 at address 0xF to optimize sequential SPI access:

• a sequential SPI read can be used to read the LINK2 register and then the frame registers in one SPI operation.
• a sequential SPI write (including SND bit) can be used to write the LINK2 register and then the frame registers. Transmission starts once the FR0 register is written and the micro-controller must ensure that the subsequent registers have valid values before the start of transmission of the respective octets.

8.1.7 Short-circuit, overtemperature and undervoltage interrupt handling

The INT pin and the STATUS:INT bit are additionally active (high) if the last value of the short-circuit, undervoltage or overtemperature status bits communicated on the SPI is different to the current value. The L6364 handles short-circuit and overtemperature autonomously and does not require a reaction from the microcontroller. It is possible for these status bits to change at any time, and so the interrupt may be removed between entering the interrupt service routine and reading the status on the SPI. The interrupt is removed during the next SPI access to the L6364. If an SPI access is made without checking the value of these bits, as is typical during processing of a data interrupt, it is normal to record the status values from the final access, or to explicitly add an extra SPI access.

8.1.8 Interrupt handler structure

The interrupt handler will typically have the following sequence: read the L6364 status with a read access from the LINK register if (STATUS:DAT is active) analyze the STATUS:CHK bit, read the FR registers send LINK2:SND or LINK2:END as appropriate and write the response into the FR registers update the microcontrollers copy of the short-circuit, undervoltage and overtemperature status based on the status bits received in the previous access. Take action if necessary.

8.1.9 Changing to and from SIO mode

The L6364 should be placed into IO-Link mode as soon as communication with the master is established. Typically a switch from SIO mode (CCTL:SIO='1') to IO-Link mode (CCTL:SIO='0') is made during the WAIT condition when a valid message is detected from the master. A switch from IO-Link mode to SIO mode is typically made shortly after the device response for the FALLBACK command has been sent. The switches themselves are, however, only activated by the microcontroller after the period defined in the IO-Link specification. The L6364 may be switched from SIO mode to IO-Link mode at any time without disturbing data reception or transmission. A switch from IO-Link mode to SIO mode may disturb data reception if a master is in the process of transmitting, and the UART is therefore reset if this occurs. L6364 Multi-octet UART mode DS13363 - Rev 4 page 18/60

8.1.10 SPI register writes outside interrupt service routines

The interrupt service routine typically accesses the SPI, and so it is necessary to avoid a collision between an interrupt service routine SPI access and any other SPI access made from the microcontroller. Accessing the SPI clears a short-circuit or overtemperature interrupt, and so the received value of these bits must be recorded by the microcontroller. If a function makes a number of sequential SPI accesses, then it is reasonable to ignore these status bits on all but the last access, and record the values read on this last access. It is not necessary to check the STATUS:DAT bit outside the interrupt service routine, since the data interrupt remains active until the microcontroller responds.

8.2 Single octet UART mode

The L6364 supports an operating mode called Single octet UART mode, which performs a simplified data transfer function, transferring one octet at a time in either direction. In this mode, M-sequence type recognition (MSEQ:M2CNT), the number of on-demand data octets (MSEQ:OD1, MSEQ:OD2) and checksum verification/generation are disabled and, therefore, must be realized by the microcontroller. Note, that an exchange is always triggered by the master. It is not possible to transmit data without first receiving valid data. Figure 8 shows the single octet UART mode state machine. When the CCTL:SGL bit is set by the microcontroller, the L6364 is set to single octet UART mode.

8.2.1 Buffering

The FR0 register and the L6364 UART internal register together provide double buffering of data in receive and single buffering in transmit. In order to avoid buffer over- or under-runs it is necessary for the microcontroller to:

• read FR0 before the UART writes a new octet in Receive mode (delay ca. 11xT BIT), or
• write FR0 before the UART requires a new octet in Transmit mode (delay ca. 3xT BIT).

8.2.2 Receive mode

In Receive mode the L6364 has the following states:

• Receive wait: The L6364 has received a complete master octet via the CQ channel. A data interrupt is generated (STATUS:DAT='1') and the received octet is placed in the FR0 register. The microcontroller has access to the FR0 register and reads the received octet. The state changes to Receive Interim. The UART continues to run in this state receiving the following frame. A buffer over-run results if the microcontroller does not read FR0 before the frame completes. A UART frame is 11 bits, which at 230.4kBaud gives a period of 47μs for the two SPI accesses, each of 16 bits. At 4 MHz SPI this corresponds to an SPI delay of 4 μs. Error conditions: parity error, stop bit, time-out (more than 4xTBIT waiting for the next UART frame on the CQ line), or buffer under-run are signaled with a data interrupt (STATUS:DAT='1') with additionally STATUS:CHK='1'. The microcontroller should respond by writing LINK:END and discarding any received octets. The master stops sending after the last master octet and so a time-out is generally detected by the L6364 in the delay while the microcontroller is preparing the response. The condition is held internally in the L6364 and discarded by the L6364 when FR0 is written by the microcontroller, initiating transmission. The timeout is therefore not reported to the microcontroller in this case.
• Receive interim: The UART receives data on the CQ line and copies this to the FR0 register, switching to Receive wait on completion. Once the expected number of octets is received, the microcontroller initiates sending by writing the first octet in the response M-sequence to FR0, thereby switching the L6364 to Transmit mode (see Section 8.2.3 ). (In single octet UART mode the equivalent of a LINK:SND command is achieved by writing to FR0). L6364 Single octet UART mode DS13363 - Rev 4 page 19/60

In SIOListen mode a received UART frame is only reported if the parity and stop bits are correct. The microcontroller must switch from SIO mode to IO-Link mode after reception of a valid UART frame before responding with LINK:END, otherwise the L6364 returns to SIO mode conflicting with the further master transmission.

8.2.3 Transmit mode

Transmit mode is entered when the microcontroller writes FR0 while the L6364 is in the Receive wait state. The UART reads this value from the FR0 register, emptying the buffer, and starts transmitting. The L6364 enters the Transmit wait state. The L6364 provides a single octet data buffer and requests further data whenever this buffer is empty, including during the transmission of the previous octet. It is only necessary to ensure that this buffer is refilled before the UART needs to send the next octet. The maximum allowed time between the starts of two subsequent frames on IO-Link is 11 TBIT frame + 3 TBIT pause = 14 TBIT, which at 230.4kBaud gives a period of 60 μs for the 16 bit SPI access. At 4 MHz SPI this corresponds to an SPI delay of 4 μs. In Transmit mode the L6364 has the following states:

• Transmit wait: The L6364 requests a new octet by sending a data interrupt (STATUS:DAT='1'). The L6364 is waiting for a response from the microcontroller, which either writes FR0 with a new octet to continue transmission, or LINK:END to terminate transmission.
• Transmitting (buffer empty): The UART sends the current octet. A further response is requested from the microcontroller, by sending a data interrupt (STATUS:DAT='1'). If the microcontroller provides a further octet, this is placed in the buffer and the state changes to Transmitting (buffer full), if the microcontroller writes LINK:END, then the state changes to Transmitting (terminating). If the microcontroller does not provide an octet before the UART transmission completes, then the state changes to Transmit wait.
• Transmitting (buffer full): The UART sends the current octet. On completion, it sources the next octet from the buffer, and the state changes to Transmitting (buffer empty).
• Transmitting (terminating): The UART sends the current octet. On completion, the PHY returns to idle.

8.2.4 Timing errors in transmit

The microcontroller can cause a timing error in Transmit mode if the delay in response is too long. These errors are not monitored by the L6364. A minimum inter-frame time delay of 1xTBIT is, however, guaranteed by the L6364.

8.2.5 Error condition in transmit

Error conditions are reported to the microcontroller as either short-circuit (STATUS:SSC='1', reported following a delay of tRETRY), or overtemperature (STATUS:SOT='1'). The conditions are handled autonomously by the L6364 and no intervention by the microcontroller is necessary. The normal data flow is preserved and the L6364 requests further octets from the microcontroller as if the error were not present. These octets are silently dropped and no attempt is made to transmit them. Under error conditions, then transmission may be terminated by the microcontroller using LINK:END='1'. L6364 Single octet UART mode DS13363 - Rev 4 page 20/60

8.2.6 Single octet UART mode state machine

Figure 8. Single octet UART mode state diagram either read from or write to FR0.

8.2.7 Synchronization in single octet UART mode

M-sequence, and in particular the checksum, guards against this. mode, eg. for code download. insertion of a synchronization octet every 32 octets.

8.3 Transparent UART mode

The L6364 supports an operating mode for transparent communication of UART frames. function of the DUAL PHY device is reduced to that of a physical level converter. restricted use of microcontroller resources. state machine in the L6364 and the PLL are placed in reset.

8.3.1 Pin functions in transparent mode

path. The SS pin controls the use of the MOSI and MISO pins, according to Table 18. Table 18. Pin dual use in transparent mode SPI access, and assert this value again on the MOSI line before setting SS='1'. Support for this may, however, be automatic depending on the microcontroller. as the MOSI line is permanently driven. Figure 9. Illustration of operation in transparent mode

8.4 Transparent mode output path

place of the MOSI line itself. select operation as a high-side, low-side or push-pull device. Note that the logical path from MOSI to CQ is inverting.

Table 19. Transparent mode operation which is suitable to indicate the presence of a valid IO-Link wake-up pulse. In transparent IO-Link operation (CCTL:TRNS='1', CCTL:SIO='0'), a short is reported immediately after tSHORT. The output switches are disabled while a short is reported, protecting the device from excessive dissipation. data or waiting for at least tRESTART.

8.4.1 Transparent mode input path

filtered with a constant delay filter, (1/16) * TBIT, see Table 5, to remove line glitches.

8.4.2 Leaving transparent mode

Transparent mode is left by clearing the CCTL:TRNS register bit to '0' via the SPI.

9 IO-Link physical layer

9.1 UART frame

Table 20. UART frame definition

1 START 0

2 LSB b0

9 MSB b7

10 PARITY P

11 STOP 1

idle state for the CQ line is low. bits b[7:0] and the parity bit.

9.2 M-sequence interpretation

where a ‘1’ denotes a read operation and a '0' a write. Table 21. M-sequence control (MC) octet structure of the message is of Type 0, Type 1 or Type 2. Table 22. Checksum/M-sequence type (CKT) octet M-sequence type and on the transfer direction (READ or WRITE).

Table 23. Receive M-sequence lengths

• f(OD1), f(OD2): defines the received number of on-demand octets, where support is only provided for data widths of 1, 2 and 8 octets and not 32. The values are determined from MSEQ:OD1[1:0] for type 1 sequences and MSEQ:OD2[1:0] for type 2 sequences according to Table 24.

Table 24. Permissible values of MSEQ:OD1 and MSEQ:OD2

00 Illegal(*) 00 1 octet

• M2CNT: defines the expected octet count on a read operation. Its value corresponds to the value of field MSEQ:M2CNT[3:0] The total data buffer size is 15 octets. If an M-sequence of a length greater than this is required for reception or transmission, then the single octet access mode should be used (see Section 8.2 ). (*)A setting of MSEQ:OD1[1:0]=00 is used for backwards compatibility. In this case M2CNT + f(OD2) defines the length of received type 1 M-sequences. L6364 M-sequence interpretation DS13363 - Rev 4 page 25/60

9.2.1 Example setting

combinations of PREOPERATE and OPERATE M-sequences. Table 25. Example M2CNT, OD1 and OD2 registers setting

1 PREOPERATE:TYPE_1_2

2 PREOPERATE:TYPE_0

3 PREOPERATE:TYPE_1_V

9.3 Checksum calculation and verification

octets of the message, with a starting value of 0x52. Table 26. Checksum compaction The L6364 then inserts this 6-bit checksum into the lower bits of the last octet sent (“Checksum/status octet”). Table 27. Checksum/status (CKS) octet message, with a starting value of 0x52. The calculated and expected checksum are compared and STATUS:CHK is set accordingly.

9.4 Data signal receive

Table 5. The decision threshold for the CQ data level is determined by the CFG:RF bit. exceeded, then both STATUS:DAT and STATUS:CHK bits are set and an interrupt is generated. message, signaling completion by writing a '1' to either the LINK:SND or LINK:END register bits.

9.5 Data output

calculated and stuffed in the message.

The data is sent by using push-pull operation of the output switches. Writing either the LINK:SND or LINK:END bit clears the STATUS:DAT and STATUS:CHK status flags. The data output is synchronized using the internal PLL clock. As defined in the IO-Link specification v1.1, the device has a maximum of 10xTBIT periods to process the incoming message and prepare the response. A delay of up to TBIT/16 can be incurred in the L6364 due to synchronization with the internal PLL clock, leaving the microcontroller slightly less than 10xTBIT to respond.

9.6 Clock recovery

The L6364 has an internal RC clock with a nominal frequency of fCK. The filtered data line is monitored for transitions while in the IOListen and SIOListen states. When a first rising edge is seen, the internal PLL clock phase is aligned to the incoming data. The PLL clock corrects its operational frequency on the detection of further rising edges. See Section 8.2.7 regarding detailed operation in single octet mode. The clock correction has a resolution of 0.4%(TYP) and a stability of 1%(MAX) over the duration of a message. L6364 Clock recovery DS13363 - Rev 4 page 28/60

10 Short-circuit detection

the output transistors of the affected output are switched off. tRESTART in order to allow reception of a valid IO-Link message or to protect the IC against overloading. providing full protection of the IC in case of overload. Table 28. DC short-circuit threshold current, ISET, CQ and DIO Figure 10. Wake-up time diagram

11 Maximum current output

The switches have an independent saturation current of ISAT, and do not draw more current than this. If, however, the CQ and DIO pins are configured to create a single output (JOIN mode), then the saturation current in this case is = 2 x ISAT. The power supply must be able to supply this current for the duration tSHORT to prevent a supply voltage drop on VPLUS. L6364 Maximum current output DS13363 - Rev 4 page 30/60

12 Undervoltage detection

this status is different to the status reported in the last SPI exchange. The undervoltage thresholds are set by CFG:UVT[2:0]. Table 29. Undervoltage threshold

13 Short term power loss

If the supply on the VPLUS fails then reverse current from V3V3 to VPLUS and from V5V to VPLUS is blocked. A residual leakage current of IPLUSREV may still flow in this time. Appropriate dimensioning of the capacitors CV3V3 and CV5V can be used to maintain the power supply during this event. L6364 Short term power loss DS13363 - Rev 4 page 32/60

14 Temperature measurement

temperature is given as shown in Figure 11. Figure 11. L6364 temperature measurement

15 Thermal shutdown

to '0'. The trip threshold is determined by the set-point in register THERM:TH[4:0] as shown in Figure 12. Figure 12. L6364 thermal shutdown configuration the status register (STATUS:SOT) and an interrupt is generated.

15.1 Automatic operation

release threshold, the L6364 returns to a normal operating state and returns the threshold to the original level.

16 LED outputs

defined by the settings of the LED:LED1 and LED:LED2 fields. Figure 13. L6364 LED currents

17 DC-DC converter

17.1 Converter configuration

Table 30. DC-DC converter nominal operating frequency, FSET Table 31. DC-DC output voltage, VSET

1. Default value following reset.

is not required, the pin DOUT is externally shorted to pin VDCDC.

17.2 Converter architecture

VDCDCpin is equal to the duty ratio of the high-side switch multiplied by the input voltage (VVPLUS- VDIODE).

Figure 14. Block diagram of DC-DC converter PID controller. This block monitors the voltages at VDCDC and VPLUS pins.

17.3 Converter operation

17.3.1 Startup

• V V3V3 >VPOR (by means, bandgap is stable)
• V VPLUS >VDCMIN (by means, oscillator toggling)
• V VPLUS>VPLUSDCMIN Operation outside these conditions is prevented to protect the IC and the surrounding circuit. Initially the converter is in a STARTUP state. In this state an internal current source attempts to source a current ISTARTUP from pin DOUT to pin LOUT. Where LOUT is connected to VDCDC by an inductor, voltage at VDCDC pin is pulled up by this current: VDCDC voltage rises until it reaches voltage VSTARTUP, where the source current is then regulated to maintain VDCDC voltage at VSTARTUP. The converter remains in the STARTUP state until the operating conditions are met. Bias is provided either by a HV bias circuit where the IC is in reset VV3V3 < VPOR, or by an LV bias circuit once V3V3 is available. During the overlap period, the bias currents are doubled.

17.3.2 Entry to operation

ARM state for 1 ms before starting operation. The switch controls are powered in this state, but set to OFF.

17.3.3 Leaving operation

diode between LOUT and PGND.

17.3.4 SLEEP state

SLEEP state is left by resetting the DCDC:DIS bit, or during a L6364 reset, that is when VV3V3 < VPOR.

17.3.5 BYPASS state

In this mode, the ISTARTUP current source is permanently enabled and the voltage on VDCDC is held at VSTARTUP. suppression of converter switching noise is required for a temporary period.

17.4 Converter external component consideration

17.4.1 Minimum supply voltage

Figure 15. Minimum supply voltage the entire temperature range.

17.4.2 Coil current limitation protection

every 200 ns and a normal cycle is started once the coil current is below ILIMIT.

operating current and external components should be chosen to avoid this behavior under normal conditions. Figure 16. Overcurrent operation

17.4.3 Capacitive blocking of DOUT

Table 5. Receiver CQ/DIO, is required to correctly supply the transient currents when the DC-DC converter value may, however, be increased to provide additional isolation from input voltage ripple on VPLUS.

18 Linear regulators

the master, and the 5.0 V linear regulator as the slave. A typical load of 10mA, a supply voltage of 24 V with a rise time of 2.4 V/μs on pin VPLUS were used. the current drawn to charge the application capacitors and any external loads. Figure 17. L6364 linear regulators' startup under different conditions of load capacitance (VVPLUS > VSUP in pure mode or VDCDC > VDCDC_5V_MIN for DC-DC operation). power-down state by setting bit CFG:PD5V. This ensures capacitances on the line are discharged cleanly, and that the output is tied to a known state.

19 Power dissipation

pitch etc), the thermal package properties provided in the figure below should only serve as a guideline. Figure 18. Example of thermal power dissipation estimation application hardware (heat-sink capability) should take account of this heating.

20 Surge pulse and reverse polarity protections

between any pair of these pins according to IEC 60255-5, i.e. > 2 APK (up to 3 APK) for a half-time of 50 μs. under test to the current ratings shown in Figure 19. Figure 19. Surge waveform chosen to be in excess of the normal operating voltages of the L6364. automatically ceases to conduct. operating voltages return to their nominal conditions. exceeding the demands of IEC 60255-5 are required.

21 Register Map

Table 32. Register map

LINK 0x04 N/A N/A Data buffer fill count(1).

0 TEMP [6] TEMP [5] TEMP [4] TEMP [3] TEMP [2] TEMP [1] TEMP [0]

Table 30. DC-DC converter nominal Table 31. DC-DC output voltage,

address BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 LINK2(2) 0x0F N/A N/A Data buffer fill count(3). Writing '1' declines sending response Writing '1' sends IO- Link response after FR0 is written FR0 to FR14 0x10 to 0x1E R/W R/W R/W R/W R/W R/W R/W R/W DATA [7] DATA [6] DATA [5] DATA [4] DATA [3] DATA [2] DATA [1] DATA [0] The data buffer registers are only accessible when frame data is available (DAT bit set).The initial value of all register bits following reset is '0', except bits DCDC:VSET[2:0], where the default value is 1. Valid CNT data may only be read when data is available (DAT bit set). If this is true, then reading the field returns the number received octets. Writing the CNT field sets the number of octets to transmit. Note that a read back will continue to read the number of octets in the received frame, and not the value written over SPI. 2. LINK register repeated prior to frame buffer with deferred send function 3. Valid CNT data may only be read when data is available (DAT bit set). If this is true, then reading the field returns the number received octets. Writing the CNT field sets the number of octets to transmit. Note that a read back will continue to read the number of octets in the received frame, and not the value written over SPI. L6364 Register Map DS13363 - Rev 4 page 45/60

22 Detailed block diagram

Figure 20. Detailed block diagram, showing register field connections

23 Typical Applications

Figure 21. Application example: DC-DC disabled, CQ and DIO coupled (Join Mode), VSENSOR = 5 V, VMCU = Figure 22. Application example: DC-DC enabled, CQ and DIO coupled (Join Mode), VSENSOR = VMCU =

soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. Figure 25. QFN20L mechanical drawings Table 33. QFN20L Dimensions [mm]

Table 34. QFN20L, Packing information (additional dimension info [mm])

soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. Figure 28. CSP19 Mechanical drawings Table 35. CSP19 Dimensions [mm]

Revision history

Table 36. Document revision history 11-Aug-2020 1 Initial release. and Figure 22 added Figure 23 and Figure 24. packing information Section 24 . Added the maximum value for CDOUT Section 4.3 . Section 4.4 ; added Figure 3 and rephrased chapter 9 Section 10 . VSURGE(LEAKAGE) and VSURGE(THRESHOLD) parameters. Reworked register map style of Table 32 Section 21 . In front page, added packing information in Product summary table. Extended product description and moved from front page to chapter 1. Deleted VDCDC_3V3_MIN from Table 4. Recommended operating conditions. and pin-out and in Section 6 SPI Communication. Added RTH(JA) in JEDEC conditions in Section 4.2 Thermal Characteristics. Fixed input voltage value in Section 17.2 Converter architecture. thermal power dissipation estimation. information (drawing and dimension [mm])) and CSP19 (Section 24 ).

Contents

DS13363 - Rev 4 page 56/60

DS13363 - Rev 4 page 57/60