L6353

L6353 STMICROELECTRONICS | Alldatasheet

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Technical content

SMART DRIVER FOR POWER MOS & IGBT PEAK HIGH OUTPUT CURRENT CAPABIL- ITY (+8A) WIDE SUPPLY VOLTAGE RANGE (12.5 TO 18V) 0 TO –7.5V NEGATIVE BIAS VOLTAGE SUP- PLY RANGE OVER CURRENT AND DESATURATION PROTECTION OF THE EXTERNAL POWER DEVICE (EXTERNALLY PROGRAMMABLE) LATCH-UP PROTECTION (FOR IGBT) TWO STEPS TURN-ON (PROGRAMMABLE) PROTECTION AGAINST POSITIVE SUPPLY UNDER-VOLTAGE INPUT COMPATIBLE WITH OPTOCOUPLER OR PULSE TRANSFORMER PROGRAMMABLE TURN-ON DELAY THERMAL PROTECTION WITH ON-CHIP OVER-TEMPERATURE ALARM AND TURN- OFF PROCEDURE OPERATING FREQUENCY UP TO 100kHz

DESCRIPTION

The L6353 device is a smart driver, with all the drive and protection know-how ”on board”. Available in both DIP and SO package, it can be triggered with a logic level or with the signal from an optocoupleror a pulse transformer. It filters parasitic inputsignals and drives any MOS or IGBT. February 2000 DIP16 2.5V 300µA 1.25V FILTER 200ns 1.25V 3.75V 3.15V LOGIC ON_SENSE ON_LEV_PROG MON_DELAY V SS OUT2 OUT1 VPOS ALARM INV_OUT INPUT SELECT DELAY COM D94IN106B OUT1 CLAMPING CLAMP_PROG THERMAL SHUTDOWN − 3.15V 7.5V SUPPLY UV SENSE REFERENCES REF VCC BLOCK DIAGRAM SO16 ORDERING NUMBERS: L6353 (DIP) L6353D (SO)

DESCRIPTION (continued) It monitors the on-state voltage drop of the driven power device and protects it against overload and short circuit. The on-state voltage drop level is externally pro- grammable from 5 to 15V. This function is inhib- ited during the turn-on of the external power de- vice for an externally programmable period. An internal inhibition time of 200ns avoids false triggering. Overload or overheating are signalled on an alarm output. If temperature continues to increase the power output is switched off and maintained in the off-state until the temperature decreases below the low threshold. A programmable turn-on delay avoids cross conduction in bridge configu- rations. To preserve the external power device (especially IGBT) from the risk of latch-up, the gate voltage can be risen in two different steps (of which the first is externally programmable from 7 to 11V). ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value Unit VCC Supply Voltage referred to COM pin 20 V VSS Negative Supply Voltage referred to COM pin – 8 to 0 V VPOS -VOUT1 Collector-Emitter Voltage of High Side NPN 25 V VOUT2 -V SS Drain-Source Voltage of Low Side DMOS 25 V VEXT1 Externally Forced Voltage (pin 9) -0.3 to V CC V VEXT2 Externally Forced Voltage (pins 4,7,10, 11, 12) -0.3 to 7 V IDELAY Sink Current pin Delay 3 mA IMON_DELA Y Sink Current Pin Mon_Delay 3 mA VON_SENSE Voltage on ON_SENSE Pin VSS-0.3 to V CC V IOUT1 Positive Output Current (tp ≤1ms) (peak) 8 A IOUT2 Negative Output Current (tp ≤1ms) (peak) 8 A IINV_OUT Output Current in INV_OUT Pin ±20 mA IALARM Output Current in ALARM Pin ±20 mA Ptot Total Power Dissipation internally limited Tamb Operating Temperature Range -25 to +85 °C Tstg Storage Temperature -50 to +150 °C THERMAL DATA Symbol Parameter DIP16 SO16 Unit R thj-ambient Thermal Resistance Junction-ambient Max 80 90 °C/W OUT1 VCC VPOS MON_DELAY ALARM VREF INV_OUT SELECT V SS ON_SENSE COM OUT2 CLAMP_PROG ON_LEV_PROG D94IN113A DELAY

8 INPUT 9

PIN CONNECTION (top view) L6353

N. Name Function 1 OUT1 Output of high side driver (emitter of power NPN transistor). 2V CC Positive Supply Voltage (referred to COM). See under voltage lockout functioning 3V POS Positive Bias Voltage (collector of the NPN power transistor). 4 CLAMP_PROG First Step of the Gate Voltage Programming. The programming is achieved setting an appropriate voltage on this pin (i.e. using a resistence voltage divider). 5 INV-OUT Inverted Output Driver Status. The buffer output is able to drive some auxiliary circuit (i.e. a LED). 6 ALARM Diagnostic Output Signal. A fault condition is signalled by this output buffer.

7 MON_DELAY V

ON Monitor Delay. An R-C network connected between this, the COM and the VREF pins, define tMON_DELAY time interval (see fig 4) 8V REF Output of the 5V/10mA internal voltage reference. 9 INPUT Input signal. The driving signal can be a logic level either active LOW (inverted mode) or HIGH (direct mode) in the Logic Level or a pulse in the Pulse Transformer Mode (see Figure 2) 10 DELAY On Triggering Delay. An R-C network connected between this, the COM and the V REF pins, definethe tDELAY time interval (see fig 4) 11 SELECT Select the direct/inverted mode in the Logic Level Mode. It’s also the reference pin in Pulse transformer mode. 12 ON_LEV_PROG V ON level programming. This pin is used to set the VON monitor level. The programming is achieved setting an appropriate voltage on this pin (i.e. using a resistive divider). 13 ON_SENSE On State Monitor. This pin is used to monitor the turning on of the external power device. 14 V SS Negative supply voltage (referred to the COM). This pin is the source of the low side driver DMOS.

15 COM Ground

16 OUT2 Output of the low side driver (drain of the DMOS). L6353

DC ELECTRICAL CHARACTERISTICS (VPOS =V CC =15V; VSS = -5 to 0V; Tj = -25 to +125°C; unless otherwise specified) Symbol Pin Parameter Test Condition Min. Typ. Max. Unit Vdrop 1V POS -V OUT1 IOUT1 = 2A 2.5 V VCC 2 Operating Supply Voltage (referred to COM pin) 12.5 18 V VCCth1 Under Voltage Upper Threshold 10.5 11.5 12.5 V VCCth2 Under Voltage Lower Threshold 10 11 12 V VCChys Under Voltage Hysteresis 0.3 0.5 0.7 V ICCq Quiescent Supply Current 5 mA Vd 4, 12 Output Voltage pin floating 1.26 V Iso Sourced Current pin grounding 20 µA Isi Sinked Current pin at +5V -20 µA Vdrop_sig 5, 6 High State Output Voltage Drop Iout= 20mA V CC –3 V Low State Output Voltage Drop 3 V Vref 8 Output of Internal Voltage Reference Iref= 0A; Tj=2 5°C 4.9 5 5.1 V Iref< 10mA; Tj=2 5°C 4.8 5.2 mA R in 7, 10 Comparator Input Resistance 100 Ω Vdth Comparator Threshold 3.15 V R ins 13 Input Resistance 75 K Ω Iouts Output Current pin grounded 200 µA VSS 14 Operating Negative Bias Voltage (referred to COM) – 7 0 V R ON 16 On Resistance OUT2 to V SS ); IOUT2 = 2A 0.5 Ω Vil 9 Low Level Voltage (Logic Level Mode) 0 1 V Vih High Level Voltage (Logic Level Mode) 4 V CC V Iin Input Current 0<V in<V CC (Logic Level Mode) –1 0 1 0 µA tinh Inhibited Parasitic Pulse Duration (Logic Level Mode) 200 300 ns Vton Turn-on Threshold Voltage Referred to Vsel (Pulse Transformer Mode) 1.5 V Vtoff Turn-off Threshold Voltage Referred to Vsel (Pulse Transformer Mode) – 1.5 V Vsl 11 Low Level Voltage (Logic Level Mode) 0 1 V Vsh High Level Voltage (Logic Level Mode) 2 V REF V Isl Current Output of SELECT Pin Vsl= 0V (Logic Level Mode) 300 µA Vsel Output Voltage of SELECT Pin (Pulse Transformer Mode) 2.25 2.5 2.75 V L6353

To drive the external power device three different possibilities are allowed: The Logic Level Mode, either direct or inverted, and the Pulse Transformer Mode Using the Logic Level Mode (direct) an high level (referred to COM), at the INPUT pin will start the Turn on Procedure (i.e. firing an N channel exter- nal device). A low level (referred to COM) will in- stead close the OUT2 pin to VSS. The functioning is reversed in the inverted mode. To select the direct mode the SELECT pin must be connected via a capacitor to COM. The in- verted mode is chosen by connecting the SE- LECT pin to COM. In logic Level Mode pulses lasting less than t inh (200ns typ.) are filtered out. In the Pulse Transformer Mode the SELECT pin will be the reference pin for the signal applied to the INPUTpin. The positive pulse will start the TURN ON PROCEDURE, while the negative pulse will close OUT2 to V SS . The duration of this pulses (tw , see fig.2) must be again tw >tinh. TURN-ON PROCEDURE The firing of the external power device is per- formed in three steps in order to avoid the most common problems that can arise. In each of these steps there are a number of pa- rameters that can be easily externally presetted to the requested values. First Step Parameter:t DELAY In order to avoid cross-conduction between the external power device in half bridge arrangement the driver output is activated after an externally programmable delay time (t DELAY , see fig. 3) after the input signal. To set the tDELAY interval an R-C network has to be connected between the DE- LAY, VREF and COM pins (see fig.4) giving: tDELAY (µsec) = REXT (KΩ ).C EXT (nF)+ ton To minimize this interval only a resistor has to be connected between the DELAY and the VREF lim- iting thus the duration to the internal propagation delay ton. Second step Parameters:tMON_DELAY ,VCL To protect the driven device from latch-up at turn- on (IGBT) after the tDELAY time interval a second externally programmable time interval tMON_DE- LAY (presettable using the same technique used to set the tDELAY interval, see fig.4) tMON-DELAY (µsec) = REXT (KΩ ).C EXT (nF) during the tMON_DELAY the voltage on the VOUT1) is limited to the VCL level. To program this value an appropriate voltage drop has to be imposed, by mean of a resistive voltage divider, at the CLAMP_PROG pin according to the following for- mula: 100nF LOGIC VSS (**) OUT2 OUT1 V POS D94IN116B VREF MON DELAYCLAMP_PROG COM VH.V. D FW LOAD 1.2Ω 5.6Ω V G ON_SENSE VCEINPUT Vin VREF 12KΩ 2.2KΩ 100nF (*) VREF 1nF 47KΩ ON_LEV_PROGDELAY V REF 100pF 4.7KΩ VREF 12KΩ 12KΩ 100nF (*) POSITIVE SUPPLY 100µF-35V 100µF-10V NEGATIVE SUPPLY 100nF SELECT VCC NOTES: (*) The capacitor is required if the pin is left floating. (**) If the negative supply is not used, the VSS pin must be connected to the COM pin as close as possible to the IC. Figure 4.Gate driving waveforms test circuit. L6353

VCLAMP_PROG = VCL 6with 7V < VCL <11V Leaving the CLAMP_PROG pin floating the VCL level is set to 9V. If the pin is grounded the func- tion is inhibited (i.e. no intermediate step during the firing). Third step Parameter:V ONth At the end of the tMON_DELAY the gate of the driven device is pulled toward the VPOS level in order to ensure an appropriate drive to minimize the power losses. The external power device is considered in overload whenever the voltage on its output, sensed via the V ON_SENSE pin, is above VONth . The comparison value is programmable setting at a certain level, by means of a resistive divider, the ON_LEV_PROG pin according to the following formula: V ON_LEV_PROG =V ONth . 0.17 with 5V < VONth .< 15V and VONth .<V CC -1V. If the ON_LEV_PROG pin is left floating theVONth . level is set to 7.5V. The overload status is signalled via the ALARM pin, active LOW. To inhibite the VON Monitor func- tion, the VSENSE pins must be grounded. THERMAL PROCEDURE As the junction temperature raises, two different events will take place. When the Over Tempera- ture Threshold (T th1), set at 130°C is reached, the ALARM output is activated (low level). If the tem- perature keeps on raising, up to the Over Tem- peratur Shutdown (Tth2 = 160°C Typ) the output power device is turned off until the temperature decrease. To prevent an oscillating behaviour both the thresholds have a built-in hysteresis of 20°C. UNDERVOLTAGE LOCK OUT To avoid operation with non optimal drive of the external power device, an Undervoltage Lockout function is implemented. The OUT1 pin is forced close to VSS until the VCC supply voltage has reached the Undervoltage Upper Threshold CCth2 ) value. If the supply voltage falls below the lower hysteresis value (i.e. VCCth1 -V CChys ) the OUT1 will be again forced close to VSS . The built-in hysteresis will thus avoid intermittent func- tioning of the device at low supply voltage that may have a superimposed ripple. VsD94IN126BVccth Vcchys Undervoltage Comparator Hysteresis L6353

DIM. mm inch a1 0.51 0.020 B 0.77 1.65 0.030 0.065 b 0.5 0.020 b1 0.25 0.010 D 20 0.787 E 8.5 0.335 e 2.54 0.100 e3 17.78 0.700 F 7.1 0.280 I 5.1 0.201 L 3.3 0.130 Z 1.27 0.050 OUTLINE AND MECHANICAL DATA L6353

DIM. mm inch A 1.75 0.069 a1 0.1 0.25 0.004 0.009 a2 1.6 0.063 b 0.35 0.46 0.014 0.018 b1 0.19 0.25 0.007 0.010 C 0.5 0.020 c1 45 °(typ.) D (1) 9.8 10 0.386 0.394 E 5.8 6.2 0.228 0.244 e 1.27 0.050 e3 8.89 0.350 F (1) 3.8 4 0.150 0.157 G 4.6 5.3 0.181 0.209 L 0.4 1.27 0.016 0.050 M 0.62 0.024 S (1) D and F do not include mold flash or protrus ions. Mold flash or potrusion s shall not excee d 0.15mm (.006inch). OUTLINE AND MECHANICAL DATA 8°(max.) L6353

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