L6280 STMICROELECTRONICS | Alldatasheet
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THREE CHANNELS MULTIPOWER DRIVER SYSTEM ADVANCE DATA PROGRAMMABLE CONFIGURATION (CHANNELS 1 AND 2) OUTPUT CURRENT UP TO 1A (CHANNELS 1A N D2 )
1 SENSE PER CHANNEL
OUTPUT CURRENT CHANNEL 3 UP TO 3A DIRECT INTERFACE TO MICROPROCESSOR C-MOS COMPATIBLE INPUT INTERNAL DC-DC CONVERTER FOR LOGIC SUPPLY (+5V) POWER FAIL WATCHDOG MANAGEMENT THERMAL PROTECTION VERY LOW DISSIPATED POWER (SUIT- ABLE FOR USE IN BATTERY SUPPLIED AP- PLICATIONS)
DESCRIPTION
The L6280 is a multipower driver system for motor and solenoid control applicatios that connects di- rectly to a microprocessor bus. Realized in Mul- tipower BCD technology -- which combines isolated DMOS transistors, CMOS & bipolar circuits on the same chip -- it integrates two 1A motor drivers (channels 1 & 2) a 3A solenoid driver (channel 3) and a 5V switchmode power supply. All of the drivers in the L6280 are controlled by a microprocessor which loads commands and reads diagnostic information, treating the device as a peripheral. Channels 1 and 2 feature a pro- grammable output DMOS transistor configuration that can be set during the initialization phase. Thanks to very low dissipation of its DMOS power stages the L6280 needs no heatsink and is pack- aged in a 44-lead PLCC package. This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice. January 1992 MULTIPOWER BCD TECHNOLOGY BLOCK DIAGRAM PLCC44 ORDERING NUMBER: L6280
Symbol Parameter Value Unit VS Power Supply Voltage (Note A) 35 V VSS Logic Supply Voltage 7 V V13 Pin 13 Input Voltage (Note B) 60 V VDHS High Side Out Transistor Driving Voltage (Note B,C) 18 V VO Output Voltage. CH1; CH2: Unipolar Motor Drive (Note D) CH3 V V VOD Differential Output Voltage CH1; CH2; Full Bridge Configuration (Note E) 60 V Vsense Sensing Voltage -1 to 2 V VI Logic Input Voltage -0.3 to V SS +0.3 V ILSD Low Side Driver Input Current CH1; CH2 DC Operation Peak (Note F) CH3 DC Operation Peak (Note G) 0.7 4.4 A A A A IHSD High Side Driver Onput Current CH1; CH2 DC Operation Peak (Note F) CH3 DC Operation Peak (Note G) 4.4 A A A A ISSOUT SMPS Output Current (Continuous) (Peak; TON < 5ms) A A IRES Reset Output Open Drain Input Current 16 mA Ptot Total Power Dissipation atTamb = 70°C (Note H) 1.6 W Tstg;Tj Storage an Junction Temperature Range -40 to 150 °C Notes: A) D0 = D1 = D2 = D3 =0; B) V13 = VS +V DHS ; C) At 20V > VDHS > 17V the input current at pin 13 must be < 30mA; D) D0 = 1; D1 = D2 = D3 = 0; E) D1 = 1; D0 = X; D2 = D3 = 0; F) The pulse width must be < 5ms and the Duty Cycle must be < 10% G) The pulse width must be <5ms and the Duty Cycle must be < 6%; H) mounted on board with minimized dissipating copper area. THERMAL DATA Symbol Description Value Unit R th j-pins R th j-amb Thermal Resistance Junction-pins Thermal Resistance Junction-ambient (*) Max. Max. °C/W °C/W (*) Mounted on board with minimized dissipating copper area. PIN CONNECTION (top view) L6280
1V S Power Supply Voltage Input
2 HSD 1 High Side CH 3 Power Output
3 SMPS OUT Output of Switchmode Power Supply
4 HSD 1 High Side CH 1 Power Output
5 HSD 2 High Side CH 1 Power Output
6, 7,17,29, 39, 40 GND Common Grounded Terminal
8 LSD 1A Low Side CH 1 Power Output
9 LSD 2A Low Side CH 1 Power Output
10 SENSE 1 A Resistor Rsense, connected to this pin allows load current control for CH 1
11 LSD 1B Low Side CH 1 Power Output
12 LSD 2B Low Side CH 1 Power Output
S +V DHS Input Voltage for the HSD Gates Drive
14 V SS Logic Supply Voltage Input
15 Comp. An RC series network allows the compensation of the SMPS regulation loop
16 RES OUT The reset open drain output can be used to warn the microprocessor about V S
18 R OSC Together with COSC , sets the cycle time of the SMPS t = 1.1 RO C O 19 C OSC Together with COSC , sets the cycle time of the SMPS t = 1.1 RO C O and sets the minimum ON time in the PWM current control loop
20 C D The value of this capacitor sets the reset delay tD =7 x 104 C D
21 V DLS By-pass Capacitor of the LSD Gates Voltage drive
22 t WD The value of this CWD sets the duration of the watchdog monostable tWD =3 x 104 CWD . If no watchdog signal is generated into the TWD time the device is automatically switched off.
23 CS Enable Input (active when low)
24 WR Write Input. When WR is low the data is loaded into the µP interface 25 A0 Operation Selection (see programming sequence). 26 A1 Operation Selection (see programming sequence). 27 A2 Channel Selection (see programming sequence). 28 A3 Channel Selection (see programming sequence). 30 D0 Data (see programming sequence). 31 D1 Data (see programming sequence). 32 D2 Data (see programming sequence). 33 D3 Data (see programming sequence).
34 LSD 2B Low Side CH 2 Power Output
35 LSD 1B Low Side CH 2 Power Output
36 SENSE 2 A Resistor R
sense, connected to this pin allows load current control for CH 2
37 LSD 2A Low Side CH 2 Power Output
38 LSD 1A Low Side CH 2 Power Output
41 HSD 2 High Side CH 2 Power Output
42 HSD 1 High Side CH 2 Power Output
43 SENSE 3 A Resistor R
sense, connected to this pin allows load current control for CH 3
44 LSD 1 Low Side CH 3 Power Output
ELECTRICAL CHARACTERISTICS (VS = 20V; Tj=2 5°C; VSS = 5V; VDHS =15V; RO =165KΩ; CO =680pF; unless otherwise specified) Symbol Parameter Test Condition Min. Typ. Max. Unit IDSS Leakage Current Fig. 1 V DS = 60V 2 mA Vs Power Supply Voltage Note 1,2 >V PF 48 V VINL Low Level Input Voltage -0.3 1.35 V IINL Low Level Input Current -10 µA VINH High Level Input Voltage 3.15 V SS V IINH High Level Input Current 10 µA VROUT Low Level Reset Out I16 = 1.5mA 0.8 V VPF Power Supply Fail Voltage (Fig. 2) 13 V IS Quiescent Supply Current V S = 12V 4.5 6 7.5 mA VSS Logic Supply Voltage 4.75 5 5.25 V ISS(IN) Logic Supply Current 4.5 6 7.5 mA ISS(OUT) SMPS Out Current Range Note 3 800 mA fosc Oscillator Frequency 64 80 96 KHz f1 SMPS and CH3 Frequency f osc KHz f1max Max SMPS Switching Frequency 120 KHz f2 PWM Frequency fosc/2 KHz f3 High Side Driver Switching Frequency fosc/4 KHz TSD Thermal Shutdown 125 150 °C tWD Monostable Watchdog Time CWD = 0.22 µF (Note 4) 6.6 ms tD Reset Delay Time C D = 0.22µF; Fig.2 (Note 5) 15.4 ms R ON ON State Drain Resistance Transistor LSD CH1 - CH2 HSD CH1 - CH2 LSD CH3 HSD CH3 SMPS Fig 3; 4ab 1.1 0.5 0.5 2.4 1.4 0.8 0.8 1.2 Ω Ω Ω Ω Ω SENSE Internal Sense LOW-Pass Filter 300 500 ns V ref DAC Reference Voltage D0=D1=D2 =1 (Table 1) 1 V DAC DAC Resolution (3 Bit) (See Table 1) Vref/8 V tC Discarge Time of Cosc Capacitor (Minimum TON) (Note 6) 0.4 µs VDHS HSD Gates Voltage Drive 13 15 17 V IDHS Pin 13 Overage Input Current 3 mA ISS (OUT) max SMPS Overload Protection Current 1.2 A VDLS Pin 21 Overage Input Voltage 12 V VSSF Logic VSS Fail Threshold Voltage (Fig. 2) 2.6 4.1 V VFHSD (1;2) Internal Clamp Diode Forward Voltage CH1/CH2 @I DS = 0.4A (Fig. 5) 1.2 V VFLSD (1AB;2AB) Internal Clamp Diode Forward Voltage CH1/CH2 @I DS = 0.4A (Fig. 5) 1.4 V VFHSD Internal Clamp Diode Forward Voltage CH3 @I DS = 1A (Fig. 5) 1.1 V L6280
Digital/Analog Converters (DACs) The output current levels are programmed by 5DACs each with 3 bit resolution. Channels 1 and 2 each have 2 DACs, one for the left part of the output stage and the other for the right part. When the output stage is used to drive only one load (as with DC motors), the L6280 uses only the right register. Channel 3 has only 1 DAC. Microstepping operation is easily performed with channels 1 and 2. The value of each DAC can be changed in two ways: a) the new value can be directly generated by the microprocessor and then loaded into the specified DAC; b) the value of a DAC can be incremented or decremented by 1; in this case the microproc- essor during acceleration or deceleration has only to indicate the DAC on which operate and the type of the operation, reducing the CPU’s burden. The correspondence between the DAC value and the Vref level is shown in table 1. Table 1 D2 D1 D0 V ref UNIT 111 1 V 1 1 0 0.875 V 1 0 1 0.75 V 1 0 0 0.625 V 0 1 1 0.5 V 0 1 0 0.375 V 0 0 1 0.25 V 0 0 0 0.125 V Iload = 0 is obtained by disabling all low-side driv- ers. Turn ON/OFF Characteristics and Program Se- quence During power-on the Switchmode Power Supply output stage is turned OFF till VS reaches VPFth. The pin Reset Out is held low and remains low till VSS is < VSSFth (the power stages and the logic of the L6280 are disabled. Not correct signals coming from the microproces- sor are then ignored; the microprocessor on the other hand, receives a low state signal from the Reset Out pin. When the V SS output is stabilized during a delay tD set by the CD capacitor, the pin Reset Out goes to the high level; the microproc- essor is enabled to work while the L6280 is in stand-by waiting for a keyword and initialization sequence.Every command that arrives before the keyword is ignored. At this time the programming sequence can start according to the flow diagram (Fig. 12). At first the Keyword (00111010) has to be sent to the L6280 to activate the watch - dog function that begins to control the microprocessor func- tionality. From this moment the microprocessor must send periodically the Watch-dog word (00110101) otherwise its absence is interpreted as a microprocessor failure: to prevent any dam- age both in the load and in the IC, the L6280 itself disables the power stages. No reset signal is gen- erated towards the CPU; the system must restart the sequence from Power-ON. The next step is to set the configuration of chan- nel 1 and channel 2 output stages by the initiali- zation word. The configuration can be chosen to fit in the load characteristics. To do this the micro- processor generates a word with A0, A1 = 0 and where A2, A3 choose the channel to be config- ured, D0 to D3 choose the type of configuration (unipolar, dual half bridge or full bridge; see Data and Address decoding). Every input configuration different from the allowed initialization word is ig- nored. When the initialization arrives, the L6280 sets the configuration of the output stage of the chosen channel. The initialization word has to be re- peated for the other channel (CH1 or CH2 only). If two initializations arrive for the same channel, the L6280 disables the output stages while pin Reset Out goes low for a time Td to advise the mocro- processor about the uncorrect condition. The pro- gram sequence must restart from the Keyword step. After the initialization step is succesfully completed the L6280 begins to accept com- mands. If a command is sent before the relative channel has been configured, the command is neglected. Command can be of three type: a - selection of current level loading a DAC; b - increment or decrement of a DAC; c - selection of the driving strategy of a channel (e.g. half/full step, fast/slow decay and so on). To select the current level is necessary to load a value into the appropriate DAC. The microproces- sor must select the channel via A2, A3 and (only for channel 1 and 2) left or right DAC via D3; the There are two possibilities of changing the value of a DAC; the first one is to load directly the new value, the second one is to cause an increment or a decrement in a DAC, in this way the burden of the microprocessor can be partially decreased generating inc/dec command without calculating the value. To increment od decrement a DAC the microproc- essor must select the channel via A2,A3, left or right DAC and the operation via D0 to D3 accord- ing to truth table in Datas and Address Decoding (see below). The increment or decrement is done immediately after the arrive of the command. For every configuration of the output stages are pos- sible different type of driving strategy explained in Datas and Address Decoding. L6280
This word is used during the start-up procedure to enable operations; all settings arrived before the keyword are reset. A3 A2 A1 A0 D3 D2 D1 D0 00110101 WATCHDOG The microprocessor must periodically generate this word; the value of the maximum period is set by the capacitor CD . The absence of the Watch- dog is interpreted by L6280 as a microprocessor failure. The maximum period is: T WD =C D x 1.5 / ( 50x 10E-6) Except for special words (keyword and watch- dog), the input words are organized like the fol- lowing: A0 A1 Operation selection A2 A3 Channel selection D0 D1 D2 D3 Datas A0,A1 DECODING (OPERATION SELECTION) A0,A1select the type of operation (channel initiali- zation, commands, DACs loading, DAC in- crement/decrement). A0 A1 0 0 This configuration is used to send the infor- mation about the configuration of the vchannel specified by A3 and A2; D0 to D3 are used to specify the configuration of the channel (full bridge, dual half bridge, unipo- lar motor). A0 A1 1 0 This configuration is used to change driv- ing strategy of the output stages of the channel specified by A3 and A2 (full/half step, slow/fast decay and so on). The driv- ing strategy is coded in D0 to D3, and de- pends from the configuration of the output stage. A0 A1 0 1 This configuration is used to load the value of a DAC of the channel selected by A3 and A2. D3 indicates right and left DAC just for channel 1 and 2. Figure 12: Program Sequence L6280
1 1 This configuration is used to cause an incre- ment or a decrement of a DAC. Right or left DAC and inc/dec are selected by D0 to D3 value. A2, A3 DECODING (Channel Selection) Every time a command or a initialization is sent to the L6280, a channel must be selected. This is done via A2 and A3 according to the table. A2 A3 0 1 Select channel 2 1 0 Select channel 1 1 1 Select channel 3 0 0 Used only with keyword and watchdog D0 to D3 DECODING (Datas) The meaning of D0, D3 changes according to the value of A0, A1 A0 A1 0 0 When A0, A1 are in this configuration, and channel 1 or 2 is selected, the data appear- ing in D0 to D3 set the output power stage configuration to fit the chosed load accord- ing to the allowed Truth Table. There is no need to configure channel 3. D3 D2 D1 D0 Possible configurations for channels 1 and 2 0 0 0 0 Null (power disabled) a 0 0 0 1 Unipolar motor b 0 0 1 0 Full Bridge c 0 0 1 1 Dual Half Bridge b)Full Bridge Configuration a)Unipolar Motor Configuration In this configuration D0 to D3 directly drive the low side drives: D3 D2 D1 D0 Configurations
0000 Low side drivers 1,2,3,4 OFF
0001 Low side drivers 2,3,4 OFF Low side driver 1 ON
0010 Low side drivers 1,3,4 OFF Low side driver 2 ON
0100 Low side drivers 1,2,4 OFF Low side driver 3 ON
0101 Low side drivers 2,4 OFF Low side drivers 1,3 ON
0110 Low side drivers 1,4 OFF Low side drivers 2,3 ON
1000 Low side drivers 1,2,3 OFF Low side driver 4 ON
1001 Low side drivers 2,3 OFF Low side drivers 1,4 ON
1010 Low side drivers 1,3 OFF Low side driver 2,4 ON
The following configurations are not allowed: the microprocessor does not to generate them otherwise they can cause faulty operations. D3 D2 D1 D0 0011 Always not allowed 0111 1011 1100 1101 1110 1111 This configuration is not allowed when driving a unipolar motor and it is permitted only to drive a high current solenoid. L6280
In full bridge configuration D0 to D3 set the driv- ing strategy of the bridge: D0 D1 D2 D3 X 0 0 0 Tristate left and right X 0 0 1 Chopper left, brake right X 0 1 0 Chopper right, brake left X 0 1 1 Brake left, brake right X 1 0 0 Tristate left and right X 1 0 1 Diagonal chopper X 1 1 0 Inverted diagonal chopper X 1 1 1 Tristate left and right c)Dual Half Bridge Configuration D0 D1 D2 D3 X 0 0 0 Tristate left and right X 0 0 1 Brake right, chopper left X 0 1 0 Brake right, chopper right X 0 1 1 Brake left, brake right X 1 0 0 Chopper left, chopper right X 1 0 1 Tristate left, chopper right X 1 1 0 Tristate right, chopper left X 1 1 1 Tristate left and right CHANNEL 3 For channel 3 only D0 has a meaning: it directly drives the low side driver DMOS. When D0 = 0 the low side driver DMOS is switched OFF and the current flows through external recirculation di- odes. A0 A1 1 0 When A0, A1 are in this configuration, D0 to D3 are used to set the strategy of the output power stages according to the out- put stage configuration previously selected. A1 A0 1 0 When A0, A1 are in this configuration, D0 to D2 are loaded into left or right wind- ing D/A converter, according to D3 value (only for channel 1 and 2)
0 Left channel DAC
1 Right channel DAC
For channel 3, D0 to D2 are loaded into the unique DAC. A1 A0 1 1 When A0, A1 are in this configuration, the value of D0 to D3 causes an increment or a decrement of the content of left/right DAC of a channel. The inc/dec operation and the DAC register selection (right or left) are selected according to the following truth table: D3 D2 D1 D0 dec LEFT inc LEFT dec RIGHT inc RIGHT The change in DAC registers is done immediately after receiving the data.The configurations D3, D2 = 11 and D1, D0 = 11 are not allowed. (Them can cause faulty operations) Channel 3 has only one DAC; the change in its value is done according to D0,D1 value. D1 D0 dec DAC inc DAC D1, D0 = 11 is not allowed (they can cause faulty operations). Output Operation In full bridge and dual half bridge configurations, the output stages will operate according to D1, D2, D3 values. FULL BRIDGE CONFIGURATION (CH1 and CH2) In full bridge configuration the cennection be- tween the output of the high side drivers and the corresponding low side drivers has to be made with external jumpers. The output stage diagram here below (Fig. 13) must be substituted inside the blank boxes in the following block diagrams. L6280
Ratings of 35V:a max value of 33V is reccom- mended. In this case, at each couple of outputs for the bi- polar windings, a snubber network must be con- nected. This network is done by the series of a re- sistor and of one capacitor: R snub =V S max/Imotor peak; C snub = Imotor peak/ (dv/dt) One dv/dt of 200V/µsec is generally a correct choice. Of course, care must be taken in the Printed Cir- cuit Board design regarding the ground paths and the high current loops. An example of P.C.B. layout is shown in Figure 29ab; Figure 30 shows the Schematic Diagram of The driving signals useful for this board can be easily generated by using an additional board (EMU KIT 512) not described here. On Figure 29a it can be observed the copper area near the I.C. is used to sink out the heat from the device. Useful thermal characteristics of the L6280 are shown in Figure 31 and 32. Figure 24:Application Test Circuit of the L6280 L6280
Figure 29a:L6280 PCB Components Side (1st metallization) L6280
PLCC44 PACKAGE MECHANICAL DATA DIM. mm inch A 17.4 17.65 0.685 0.695 B 16.51 16.65 0.650 0.656 C 3.65 3.7 0.144 0.146 D 4.2 4.57 0.165 0.180 d1 2.59 2.74 0.102 0.108 d2 0.68 0.027 E 14.99 16 0.590 0.630 e 1.27 0.050 e3 12.7 0.500 F 0.46 0.018 F1 0.71 0.028 G 0.101 0.004 M 1.16 0.046 M1 1.14 0.045 L6280
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications men- tioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without ex- press written approval of SGS-THOMSON Microelectronics. 1994 SGS-THOMSON Microelectronics - All Rights Reserved SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands - Singapore - Spain - Sweden - Switzerland - Taiwan - Thaliand - United Kingdom - U.S.A. L6280