L6260 STMICROELECTRONICS | Alldatasheet
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4.5 – 5.5V DISK DRIVER SPINDLE & VCM, POWER & CONTROL COMBO’S GENERAL 5V OPERATION. *REGISTER BASED ARCHI- TECTURE MINIMUM EXTERNAL COMPONENTS SLEEP AND IDLE MODES FOR LOW POWER CONSUMPTION SELECTABLE GAINS FOR BOTH V.C.M. AND SPINDLE
10 BIT (+ SIGN + GAIN ) VCM & 8 BIT SPIN-
HIGH BANDWIDTH SPEED REGULATION LOOP (ONCE PER MECH\\ELEC CYCLE AC- CURACY) VCM DRIVER CURRENT SENSE CONTROL (VOLTAGE PROPORTIONAL TO CURRENT) 300mA DRIVE CAPABILITY TWO CURRENT RANGES FOR SEEKING AND TRACKING INTERNAL REGISTER FOR POWER AMP CONTROL LINES SPINDLE DRIVER BEMF PROCESSING FOR SENSORLESS MOTOR COMMUTATION PROGRAMMABLE COMMUTATION PHASE DELAY PROGRAMMABLE SLEW-RATE FOR RE- DUCED E.M.I. 0.8Ω FOR ANY HALF BRIDGE WORST CASE SYNCHRONOUS RECTIFICATION OF THE B.E.M.F. DURING RETRACT OPERATION BIPOLAR \\ TRIPOLAR OPERATION SYNTHESIZED HALL OUTPUTS
1.0 AMP DRIVE CAPABILITY
THERMAL & CURRENT PROTECTION
DESCRIPTION
The L6260 is single chip sensorless (DC) spindle motor and voice coil controllers including power stages suitable for use in small disk drives. These devices have a serial interface for a micro- processor running up to 10 Mega bits per second. There are registers on chip to allow the setting of the desired spindle speed via the on chip Fre- quency Locked Loop (F.L.L.). No external compo- nents are required in the sensor-less operation as the control functions are integrated on chip (e.g. B.E.M.F. processing, digital masking, digital delay and sequencing). The V.C.M. drivers uses a transconductanceam- plifier, able to provide 2 different current ranges, suitable for seeking and tracking. When a low voltage is detected, a Power On Re- set (P.O.R.) is issued and the internal registers are reset, the spindle power circuitry is tri-stated, B.E.M.F. synchronous rectification is enabled, the actuator retracts and then dynamic braking of the spindle is applied. These devices are built in BICMOS technology al- lowing dense digital circuitry to be combined with MOS\\Bipolar power devices. November 1996 TQFP64 ORDERING NUMBER: L6260 BICMOS TECHNOLOGY
VCM LOGIC & DAC VCM PARK PARK/V VCM/COMP BEMF AMP SPINDLE LOGIC TRISTATE SPINDLE FLL ANALOG TEST CIRCUIT DIGITAL TEST CIRCUIT ATEST DTEST D94IN087 CHARGE PUMP CURRENT GENERATOR SPD/COMP SPD/COMP/SHT SPN/SLEW FLL/RES SPINDLE BLOCK & DAC BRK/DLY SPN/I/COMP SPIN/GND2 VPDOWN COIL/C SPIN/GND1 COIL/A COIL/B VSPIN/2 SPN/I/SNS VRECT VSPIN/1 CENTER TAP DRIVER CTAP SYNTH/HALL VOLTAGE TRIPLER VLTRIP VHTRIP C2LOW C2HIGH VPARKOUT C1LOW C1HIGH VVCM/1 VCM/MINUS VVCM/2 VCM/PLUSVCM/I/SNS/2VCM/I/SNS/1 BLOCK DIAGRAM 11 6 3348
64 GND
VSPIN_1 R/W_ COIL_A TEST SYNTH_HA LL SPN_GND_1 TRISTATE COIL_B EXTFLL/DTEST VSPIN_2 BRK_DLY COIL_C VPDOWN SPIN_GND_2 GND C2HIGH C1LOW C1HIGH TRIPGND CT AP POR_DLY VVCM_2 VCM_MINUS VCM_I_SNS2 VCM_PLUS VVCM_1 ATEST VCM_I_SNS1 UV GND SPN_DSBL_DLY GND VPARK OUT SPN1 COMP GND SPD COMP SHT AGRND FLL RES REF OUT VCC SPIN SLEW VFER_MINUS SPD COMP DAC GND GND GND PARKV GNDSCL K SPN ISNS VRECT FCLK SDIO G ND SLOAD VDC DIG GND LOW POR VHT RIP VLTRIP VCM COM P G ND PIN CONNECTION (Top view) L6260
Pin Types: I = Input, O = Output, P = Power, A = Analog (passive) Power PIN # PIN NAME DESCRIPTION PIN TYPE I\\O MAPPED? TRI-STATE @SLEEP/@POR 8 VDC Digital power. Positive nominally 5V or 3V AI No No 41 VCC Analog power. Positive nominally 5V or 3V AI No No 54 VVCM_1 VCM power supply. Positive nominally 5V or 3V AI No No
58 VVCM_2 Same as above AI No No
23 VSPIN_1 Spindle power pin. Positive nominally 5V or 3V AI No No
31 VSPIN_2 Same as above AI No No
1 GND Ground AI No No
18 SPN_GND_1 Ground for spindle circuit AI No No
27 SPN_GND_2 As above AI No No
44 DAC_GND Ground for all DACs AI No No
45 AGND Analog ground AI No No
7 DIG_GND Digital ground AI No No
63 TRIPGND Voltage tripler ground AI No No
Serial Interface & Test Pins PIN # PIN NAME DESCRIPTION PIN TYPE I\\O MAPPED? TRI-STATE @SLEEP/@POR 12 FCLCK System clock. 4-12MHz selectable via the CLK_PRESCALE bit in the System Control Register B (Reg 4 Bit 4). DI Yes No 11 SDIO Serial port data I/O running up to 10MHz. For full details of all serial port signals see the Circuit Description section. DI/O Yes Yes
10 SCLK Serial port clock (max 10Mbits/s) DI Yes No
19 R/W Read / Write signal for serial interface DI Yes No
9 SLOAD Chip select input. DI Yes No 21 TEST Used to enable one of the test modes. The mode is selcted in conjunction with the TRISTATE pin (see below for more details). DI No No 24 TRISTATE Used to enable one of the test modes. The mode is selcted in conjunction with the TEST pin (see below for more details). This pin has no effect on the spindle or VCM drivers, this is a test pin only. DI No No 60 ATEST Analog test pin. This pin carries the required analog signal to allow external testing. AO No No 26 DTEST Digital Test Output Pin. This pin also doubles as the Clock input if an external FLL is used. DI/O No No Test Mode TEST pin TRISTATE pin IOMAPPING Test 1 0 DIGITAL Test* 1 1 ANALOG Test* 1 1 TRISTATE Test 0 1 Normal Operation (non test mode) For a detailed description please refer to the Test Circuit section of the CIRCUIT OPERATION por- tion of this datasheet * These two test modes operate simultaneously through separate test pins (ATEST and DTEST). L6260
PIN DESCRIPTION (continued) Pin Types: I = Input, O = Output, P = Power, A = Analog (passive) VCM Driver and DAC PIN # PIN NAME DESCRIPTION PIN TYPE I\\O MAPPED? TRI-STATE @SLEEP/@POR 53 VCM_I_SNS1 High side of VCM sense resistor network. This pin provides the current to the network as well as sensing the total voltage across both sense resistors. Sensing the total drop across both resistors results in the low transconductance gain feedback used for track following. AN o N o
56 VCM_I_SNS2 Sensing across the lower VCM sense resistor for
high transconductance gain feedback for seek operations. AN o N o 6 VCM_COMP VCM compensation network. Typically, 200K Ω in series with 100nF is connected from this pin to Ground. AN o N o
57 VCM_PLUS VCM Power Amplifier positive output terminal A No No
55 VCM_MINUS VCM Power Amplifier negative output terminal A No No
46 PARK_V A resistor conneced between this pin and
VCM_PLUS determines the Parking Voltage AN o N o 35 VPARKOUT Output from the retract circuit. This pin is usually directly connected to the VCM_MINUS. AO No No Spindle Driver and DAC PIN # PIN NAME DESCRIPTION PIN TYPE I\\O MAPPED? TRI-STATE @SLEEP/@POR 40 SPN_SLEW The External.Spindle Driver Slew Rate resistor (Rslew), typically 250K is connected from this pin to Ground. When in nExternal Slew Rate Mode (System Control Register B, Bit 10=0), the slew rate is determined by: Slew Rate = (0.5V to Rslew) X (DAC slew +1) +20pF DAC slew = System Control Register bits 7 - 9. AN o N o
36 SPN_I_COMP A seroies RC network from this pin to ground sets
the spin driver compensation. Typical a single 4nF capacitor will provide adequate compensation. AN o N o 14 SPN_I_SNS A current sensing resistor (2.5KΩ Typical ).is connected from this pin to ground. See the Circuit Operation section for details. AO No No 20 COIL_A Spindle Power Amplifier output A. Also serves as BEMF sensing for Phase A. AN o N o 25 COIL_B Spindle Power Amplifier output B. Also serves as BEMF sensing for Phase B. AN o N o 29 COIL_C Spindle Power Amplifier output C. Also serves as BEMF sensing for Phase C. AN o N o
59 CTAP Spindle Motor Center Tap connection A No No
22 SYNTH_HALL CMOS level spindle speed output. When SYNHALL (System Control Register B, bit 5) is set to 0, this output switches state at every zero crossing of any phase. With SYNHALL = 1, the output only switches every zero crossing of Phase A. DO Yes Yes
37 SPD_COMP Change Pump RC network connection pin for FLL
mode operation. AN o N o
38 SPD_COMP_S
This pin allows for shorting of to the Charge Pump Network resistor. This operation provides a quick charge on the Charge Pump capacitor, reducing settling time once desired speed is reached. Operation is controlled by bit 9 of System Control Register A. AN o N o 39 FLL_RES Frequency Locked Loop charge pump gain resistor. (Rep), typically 12.5KΩ , is connected from this pin to Ground. Change Pump current is determined by: I = (0.5V to Rcp) X (FLLGAIN DAC +1) FLLGAIN DAC = System Control Register B bits 0-4 AN o N o L6260
PIN DESCRIPTION (continued) Pin Types: I = Input, O = Output, P = Power, A = Analog (passive) Power down sequencing, POR, other voltage pins PIN # PIN NAME DESCRIPTION PIN TYPE I\\O MAPPED? TRI-STATE @SLEEP/@POR
13 VRECT Output of the synchronous rectifier supplying power to
the retract circuitry. Filtered by an internal 400pF capacitor. Normally not externally connected. However, if retract command is to be used, a small signal silicon diode must be connected between this pin and Vcc (Cathode to VRECT) to supply the additional current which may be required to brake the VCM. AO No No
28 BRK_DLY An external parallel RC network from this point to
ground sets the Brake dELAY:T = 0.45 RC. Typical values are R = 4MΩ , C=0.1µF (0.16sec, delay). AN o N o 30 VPDOWN Voltage tripler reservoir capacitor. This is used for the brake operation when power is removed from the chip. No DC load allowed. 1µF minimum, 10µF prefered. AN o N o 61 C1HIGH Positive terminal of charge pump capacitor. 10nF (typ) for Tripler operation; 330nF (typ0 or Doubler operation AN o N o 62 C1LOW Negative terminal of charge pump capacitor. 10nF (typ) for Tripler operation; 330nF (typ) or Doubler operation AN o N o
64 C2HIGH Positive terminal of charge pump capacitor for
Tripler operation. 330nF (typ). Connected tp VHRTRIP for Doubler operation. AN o N o
2 C2LOW Negative terminal of charge pump capacitor for
Tripler operation. 330nF (typ). Not connected for Doubler operation. AN o N o
52 POR_DLY An external capacitor from this pin to ground sets
the duration of POR after power has been re- established. T (por) = 32 X C (por) where: C (por) is in pF and T is expresssed inµs. AN o N o 5 POR Power On Reset. This open drain output goes low when the voltage at either UV1 or UV2 goes below 1.25V. DO Yes No 50 UV1 Under voltage detector 1. This defines the VOLTAGE GOOD threshold by comparing the voltage on this pin to the internal 1.25V reference. An external resistor divider network and capacitor filter provides the selection of threshold and supply noise rejection. There is an internal pull-up (2µA max). Hysteresis is 20mV. AI Yes No
51 SPN_DSBL_
Spindle Disable Delay . A capacitor connected between this pin and Vcc programs the delay between POR and the disabling of the Spindle section.. Delay = 80 xC (C in pF; Delay inµs) AI Yes No 4 VHTRIP High tripler/Doubler output. 330nF (typ). 11V max. AO No No 3 VLTRIP Low tripler/Doubler output. 330nF (typ). for stability. AO No No L6260
PIN DESCRIPTION (continued) Pin Types: I = Input, O = Output, P = Power, A = Analog (passive) Auxiliary Functions PIN # PIN NAME DESCRIPTION PIN TYPE I\\O MAPPED? TRI-STATE @SLEEP/@POR 42 REFOUT Output from auxiliary OPAMP. A No No 43* VREF_MINUS (L6260 only) Negative input to auxiliary OPAMP. This is prsent ONLY on the L6260. AN o N o
26 EXTFLL/
See previous description of this pin (Serial interfaca & Test Pin section). DI/O No No ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value Units Vdd,Vp max Maximum Supply voltage 6.5 V Vin max Maximum input voltage Vdd + 0.3 V V Vin min Minimum input voltage GND - 0.5 V V Ipeak Peak sink/source output current 1.5 A Idc DC sink source output current 1.0 A P tot Maximum Total Power Dissipation 1.0 W Tstg,Tj Maximum storage/junction temperature -40 to 150 °C POWER DISSIPATION Symbol Parameter Test Condition Min. Typ. Max. Units Vdd,V p Supply voltage range 4.5 5.5 V READY QUIESCENT CURRENT VCM ENABLED SPINDLE ENABLED 20 mA IDLE QUIESCENT CURRENT VCM DISABLEDSPINDLE ENABLED 10 mA SLEEP QUIESCENT CURRENT VCM DISABLEDSPINDLE DISABLED 5m A THERMAL DATA Symbol Parameter Value Unit R th j-case Thermal Resistance Junction to Case 10 °C/W R th j-amb(*) Thermal Resistance Junction to Case 41.5 °C/W (*) In typical application with multiplayer printed circuit board. RECOMMENDED OPERATING CONDITIONS Symbol Parameter Value Unit Vddn Supply Voltage 4.5 to 5.5 V Tamb Operating Ambient Temperature 0 to 70 °C Tj Junction Temperature 0 to 125 °C L6260
ELECTRICAL CHARACTERISTICS
Symbol Parameter Test Condition Min. Typ. Max. Units Iocr Max Current Coarse Range 300 mA Iofr Max Current Fine Range 75 mA R dson ABEF Source & Sink On Resistance Coarse Tj =125 °C, Iload= 300 mA 1.0 2.5 Ohms R dson CD Sink On Resistance Fine Range C, D VCM drive transistors 5.0 10.0 Ohms Vjump Current Sense Jump Discontinuity
1 LSB
Vdeadband Current Sense Deadband 200 µV Icsbias Current Sense Bias Current 1 µA PSRR DC Power Supply Rejection Ratio Vdd 4.5 to 5.5 V 50 dB BW Current Loop Bandwidth La = 1mH Ra=40ohms Imax =75mA
20 KHz
Symbol Parameter Test Condition Min. Typ. Max. Units R es Resolution 10 Bits Resistive Ladder Plus Sign (1 Bit) Unipolar 11 bits N.L. Differential Non-Linearity 1 LSB I.N.L. Integral Non - Linearity 3.0 LSB C T Conversion Time 0 - 90 % From Input Of Last Bit (for any change of code) 1.0 µs FSTC Full Scale Temperature Coefficient 0 to 125°C 250 ppm/C Voh High Output Voltage 25 °C, No Load 0.240 0.250 0.260 V Vol Low output Voltage 25 °C, No Load 100 µV PSRR Power Supply Rejection 50 dB +3 +2 +1 +1 +2 +3 Operational Area Nominal Y(at) UNITS imax 1024 UNITS L.D.D.JT X(in) DACRegister Value D94IN090 Figure 1:Vjump vs. Deadband L6260
ELECTRICAL CHARACTERISTICS (continued) Spindle Motor Symbol Parameter Test Condition Min. Typ. Max. Units Io Maximum Output Current 1 A R dson Sink Sink On Resistance T j =125 °C,I load= 1A 0.4 Ohms R dson Total Total drive resistance R dson sink + Rdson source Tj =125 °C, Iload= 1A 0.8 Ohms dv/dt Voltage Slew Rate 0.2 2 V/ µs Spindle Current Sense FET linearity Large signal Current sense circuit linearity (spin-up). 2000:1 current sense. 1% to full scale current 5 %FS Linearity small signal Current sense circuit linearity(at speed). 500:1 current sense. 1% to 10% full scale 0.5 % BW Current loop bandwidth small signal (at speed) Lmotor 100µHt o1 µH 20 KHz FS Full scale current error 5 %FS matching Current sense matching 25 to 250 mA 5 % DAC Acceleration Control res Resolution Full scale 8 bits NL Differential Non-linearity 0.5 LSB INL Integral Non-linearity 1 LSB FS Full scale accuracy 5 % CT Conversion time 10 ms FSTC Full Scale Temp Coefficient 250 ppm/ °C V oh 1.235 1.25 1.245 V Vol 0 0.2 0.3 V Gain1X Current Sense Gain at 500:1 502 525 554 Gain5X Current Sense Gain at 2500:1 2400 2900 Step-up Converter Vsu3 Step-up converter voltage (using Tripler as a doubler) above 5V. V dd = 4.5 to 5.5 volts, Maximum load Digital Inputs(All digital inputs are CMOS compatible) Vih High level input voltage I in= TBD 30% Vdd V V il Low level input voltage I in= TBD 70% Vdd V V oh High level output voltage I out= TBD V dd-0.6 V Vol Low level output voltage I out= TBD 0.4 V Iin Input leakage current T j =125°C+ 1 - 1 µA Power On Reset(Either low voltage detector can be disabled by trying the divider to a high voltage) Tdelay Minimum delay power OK to RESET high C POR_DELAY = 0.22*H 50.32 70.4 64.46 ms Vref Voltage reference 1.235 1.25 1.265 V Retract Tretract Retract time before brake power low detected Tretract= 0.4 x RC TBD TBD ms R dson Total switch circuit resistance 10 Ohms I for Vretract 2 quadrant retract voltage V BEMF > PARK_Voltage 11 13 15 µA L6260
INTERNAL REGISTER DEFINITION System Status Register (Reg 0) Reg: 0 Name: System Status Register Type: Read only. BIT LABEL DESCRIPTION @POR 0 THERMAL Thermal shutdown = 1, normal = 0. One signifies that the chip temperature has exceeded the 180°C. The bit will reset when the temperature falls from 180°C to 140°C (the hysteresis prevents rapid changing of this bit). When this bit is activated, the spindle logic will tristate both high and low side drivers to allow the disk to coast and cool down the chip. 1 UV Under Voltage=0, good voltage =1. This signals whether the under voltage circuit has been activated or not. NOTE: When UV=0, the POR is activated and all serial port control logic is reset. This means that writes are impossible, however, the user can still poll the status of this register provided the logic voltage is sufficient for the logic to function. 2 FLL_UP Providing mainly for testing. When the FLL is sourcing current into the charge pump capacitor this is set to 1. A 0 means that the sourcing current is disabled. 3 FLL_DOWN Providing mainly for testing. When the FLL is sinking current from the charge pump capacitor this is set to 1. A 0 means that the sourcing current is disabled. 4 BEMF_SENSE Toggles with BEMF. 0 5 MASK_TIME Mask time currently in use = 1. When 1 this means the BEMF comparator will not sense the zero crossing at this time. A 0 means zero crossing sensing will occur. 6 DELAY Delay time currently in use = 1. e.g. A commutation delay is active and at the end of this delay the next commutation is executed. 7 AT_SPEED 1=spindle is at speed (set by the first ”down pulse” of the FLL. It is reset at POR.
8 UNUSED 0
9 UNUSED 0
10 UNUSED 0
11 UNUSED 0
VCM DAC Register (Reg 1) The VCM DAC register is used to control the cur- rent in the voice coil motor. All 10 bits are part of a resistor divider network. Bit 10 is the sign bit and logically controls the current direction through the VCM. Bit 11 selects the current sense resistor to use for current control. A 0 selects coarse and therefore only the lower sense resistor, a 1 se- lects the top of both resistors so that the sense resistor is the sum of the coarse and fine resis- tance’s. To clarify the manner in which the 2’s comple- ment is used here are some examples: Value entered to register (0x means hex)DAC value Sign Gain 0x000 0x000 + 0 0x800 0x000 + 1 0x3FF 0x3FF + 0 0x400 0x3FF - 0 0x401 0x3FF - 0 0x7FF 0x001 - 0 Reg: 1 Name: VCM DAC Register Type: Write only. BIT LABEL DESCRIPTION @POR 0 VDAC BIT 0 LSB resistor ladder of the 10 bit VCM DAC. This is a true unsigned 0 1 VDAC BIT 1 representation of the DAC input. The value entered here is a 2s- 0
2 VDAC BIT 2 complement of the required DAC value encoded across eleven bits 0
3 VDAC BIT 3 (10 bit data and 1 sign bit encoded into 11 bits in 2s-complement) 0
4 VDAC BIT 4 0
5 VDAC BIT 5 0
6 VDAC BIT 6 0
7 VDAC BIT 7 0
8 VDAC BIT 8 0
9 VDAC BIT 9 MSB resistor ladder. 0 10 VCMSIGN Sign bit of the above 2s-complement number. 0
11 VCMGAIN This changes the gain of the VCM DAC 0
Spin Control Register (Reg 2) The spin control register has two functions: (1) The first (bits 0-7) is to program the current to the spindle motor to allow motor control and to preset the ”at speed” voltage for the charge pump. (2) The second (bits 8-11) is to set the phase lag from when a BEMF zero crossing occurs to the next commutation. Nominally the delay would be 30 electrical degrees but it often is better to advanced the commutation, due to the presence of other sources of delay, re- lated to switching. The range is from 1.875 through to 28.125 electrical degree delay at 1.875 degree increments. Reg: 2 Name: Spin Control Register Type: Write only. BIT LABEL DESCRIPTION @POR
0 SPIN_DAC BIT 0 Spindle current limit LSB (LSB of 8 bits written to the spindle DAC) 0
1 SPIN_DAC BIT 1 0
2 SPIN_DAC BIT 2 0
3 SPIN_DAC BIT 3 0
4 SPIN_DAC BIT 4 0
5 SPIN_DAC BIT 5 0
6 SPIN_DAC BIT 6 0
7 SPIN_DAC BIT 7 Spindle current limit MSB 0
8 SPINDLY BIT 0 Spindle commutation delay LSB 0
9 SPINDLY BIT 1 0
10 SPINDLY BIT 2 0
11 SPINDLY BIT 3 Spindle commutation delay MSB 0
System Control Register A (Reg 3) Reg: 3 Name: System Control Register A Type: Write only. BIT LABEL DESCRIPTION @POR 0 SPIN_ENABLE Enable spindle functions (1 = enabled; 0 = Disabled). Together with VCM_ENABLE, determine the Normal, Idle or Sleep mode of operation. See Mode Table for details. 1 VCM_ENABLE Enable VCM functions (1 = enabled; 0 = Disabled). Together with SPIN_ENABLE, determine the Normal, Idle or Sleep mode of operation. See Mode Table for details. 2 SRESET Reset spindle state machine (sequencer). 0=Reset. All spindle and FLL registers are also reset. Also used to control the charge pump (1 = off). 3 INCRE A 0 to 1 transition of this bit increments the spindle state machine. Normally used in SEARCH mode. Must be set to 1 in RUN Mode.
4 RUN_SRCH 1=Auto-increment enabled (RUN Mode)
0 = Auto-increment disabled (SEARCH MODE) 5 8_12P Selects 8/12 pole motor: 1 = 8 pole, 0 = 12 pole 0
6 BIP_TRIP Define Tristate, Bipolar, or Tripolar operation: 0
7 UNI_TRIP See Spindle Drive Mode Table. 0 8 VCMRET Activated VCM Retract: 1 = retract. 0 9 SPEED Programs the Spindle Speed Control Method. SPEED= 0: The L6260 operates open loop, with speed error sensing performed externally and speed effort written into the SPIN_DAC. SPEED = 1: The speed is controlled internally through the built-in control loop. 10 EL_MECH Specifies electrical or mechanical cycle for the FLL control. 1 = Electrical, 0 = Mechanical 11 TEST_COUNT_RESET Writing a 0 resets the test sequence. Must be set to 1 to allow ATEST and DTEST functions. MODE OF OPERATION (REGISTER 3 BITS 0 AND 1) SPIN_ENABLE VCM_ENABLE MODE DESCRIPTION (0) DISABLED (0) DISABLED SLEEP MINIMUM POWER DISSIPATION. (0) DISABLED (1) ENABLED NOT NORMAL VCM IS FORCED TO A PARK CONDITION (1) ENABLED (0) DISABLED IDLE VCM DISABLED FOR REDUCED DISSIPATION (1) ENABLED (1) ENABLED NORMAL NORMAL MODE OF OPERATION SPINDLE DRIVE MODE (REGISTER 3 BITS 6 AND 7) BIP_TRIP UNI_TRIP SPINDLE DRIVE MODE 0 0 TRISTATE 0 1 NOT DEFINED 1 0 BIPOLAR 1 1 TRIPOLAR L6260
System Control Reg B (Reg 4) Reg: 4 Name: System Control Register B Type: Write only BIT LABEL DESCRIPTION @POR 0 FLLGAIN BIT 0 Frequency Locked Loop (FLL) gain control. A gain factor of 1 to 8 can be programmed, This register value varies the FLL gain by changing the Integrator Current. Bit 0 is the LSB.
1 FLLGAIN BIT 1 0
2 FLLGAIN BIT 2 0
3 EXT_INT External or internal spindle loop feedback. This bit is programmed to 0 for BEMF feedback, 1 for external feedback. External feedback is connected via the DTEST pin, which is configured as an input in this mode.
4 CLK_PRESCALE This selects a one bit pre-scaler for the internal clock, minimizing
the effect of differing fequencies on the FLL and logic counters. Set to 1for 4-6MHz system clock, Set to 0 for 8-12MHz system clock 5 SYNHALL This selects the signal at the SYNTH_HALL pin. When set to 0, Synth Hall pin will produce a once per BEMF crossing signal (from BEMF comparitor). Setting the bit to 1, Synth Hall pin will give a once per electrical cycle signal (from zero crossing detector). 6 SFETGAIN Selects the gain of the sense FET circuit of the spindle driver. 0 = Spindle is high transconductance loop gain, 1 = low gain
7 SLEW BIT 0 Slew rate control Bit 0 ( LSB) 0
8 SLEW BIT 1 Slew rate control Bit 1 0
9 SLEW BIT 2 Slew rate control Bit 2 (MSB) 0
10 SLEW BIT 3 Setting this bit to 1 selects an internal 250K slew rate resistor. Setting it to 0 allows slew rate control by an external resistor. 11 MASK_PHASE Selects between 7.5 ° and 15° mask time (0=15°, 1=7.5°) MOTOR PHASES Below are the three possible waveforms available from the SYNTH-HALL pin. The desired waveform is selected via ”Synth Hall” bits in the System Control Register B. Once per ”BEMF Crossing” (Once per zero cross) Once per ”electrical cycle” D94IN091 Figure 2:The following diagram explains bits 5 ”SYNTH HALL” and the effect it has on the pin named SYNTH_HALL L6260
Frequency Locked Loop Coarse Counter (Reg 5) This register contains the ”coarse” FLL counter value for the FLL. This register gives a worst case resolution of 16µs with the worst case (i.e. slow- est) 4MHz clock and has a valid range of 001 to FFF hex. Reg: 5 Name: FLL Coarse Counter Register Type: Write Only BIT LABEL DESCRIPTION @POR
0 CLATCH BIT 0 FLL Coarse counter LSB 0
1 CLATCH BIT 1 0
2 CLATCH BIT 2 0
3 CLATCH BIT 3 0
4 CLATCH BIT 4 0
5 CLATCH BIT 5 0
6 CLATCH BIT 6 0
7 CLATCH BIT 7 0
8 CLATCH BIT 8 0
9 CLATCH BIT 9 0
10 CLATCH BIT 10 0
11 CLATCH BIT 11 FLL Coarse counter MSB 0
Frequency Locked Loop Fine Counter (Reg 6) This register contains the ”fine” counter value of the FLL. The worst case resolution (i.e. with a 4MHz clock) is 1µs. It is important that the most significant bit of this register must be a zero when a write is made.Valid writes to this register must be between 001 and 7FF hex. Reg: 6 Name : FLL Fine Counter Register Type: Write only. BIT LABEL DESCRIPTION @POR
0 FLATCH BIT 0 FLL Fine counter LSB 0
1 FLATCH BIT 1 0
2 FLATCH BIT 2 0
3 FLATCH BIT 3 0
4 FLATCH BIT 4 0
5 FLATCH BIT 5 0
6 FLATCH BIT 6 0
7 FLATCH BIT 7 0
8 FLATCH BIT 8 0
9 FLATCH BIT 9 0
10 FLATCH BIT 10 0
11 FLATCH BIT 11 FLL Fine counter MSB -NOTE: On a write to this register, this bit
must be zero. L6260
This device includes a sensorless spin driver, VCM driver, power sequencing, actuator retrac- tion with dynamic braking, serial interface for a microprocessor and frequency locked loop for speed control. The device is register based and designed to operate via either 3V or 5V power supply. POR & Under Voltage The L6260 has an on chip power monitoring sys- tem that controls all aspects of powering up, Power On Reset of the Logic (POR), low voltage detection and power down sequencing. The cir- cuitry consists of a Bandgap reference generator, hysteresis comparitor (for low voltage detection) and a POR timer circuit (which controls the dura- tion of the reset). Four external pins determine the behavior of this circuit. UV1 & UV2: These two pins are provided to the user to connect to the supply voltages for low voltage detection. The voltage on these pins is compared to the internal Bandgap volt- age to determine if a low voltage on one of the supply pins has been detected. The comparitor has built in hysteresis to reduce the effects of noise on the supply lines triggering a false POR. In other words, if either one of these in- puts falls below 1.25V then the supply is re- garded as being ”under voltage”. Normally one of these pins will be connected to allow a sens- ing of a 3V supply and the other to the 5V sup- ply but this is arbitrary POR_DLY: This is a pin from which a capacitor can be connected to ground. This sets the du- ration of the reset state of the this chip. On power up, an internal current source charges the capacitor with a current of approximately 2mA. When the voltage on this pin reaches the bandgap voltage, the chip comes out of its re- set state. The duration of this reset is deter- mined by the size of an external capacitor to ground. POR: The POR pin is an output from the chip for resetting other devices. Frequency Locked Loop Fine Error Counter (Reg 7) This register contains the error detected between the ”fine” counter value of the FLL and the actual spindle rotation time (in either mechanical or elec- trical mode). Reg: 7 Name: FLL Fine Error Counter Register Type: Read Only BIT LABEL DESCRIPTION @POR
0 FINEC BIT 0 FLL Fine error count LSB 0
1 FINEC BIT 1 0
2 FINEC BIT 2 0
3 FINEC BIT 3 0
4 FINEC BIT 4 0
5 FINEC BIT 5 0
6 FINEC BIT 6 0
7 FINEC BIT 7 0
8 FINEC BIT 8 0
9 FINEC BIT 9 0
10 FINEC BIT 10 0
11 FINEC BIT 11 FLL Fine error count MSB 0
VCM LOGIC & DAC VCM PARK PARK/V VCM/COMP BEMF AMP SPINDLE LOGIC TRISTATE SPINDLE FLL ANALOG TEST CIRCUIT DIGITAL TEST CIRCUIT ATEST DTEST D94IN089A CHARGE PUMP CURRENT GENERATOR SPD/COMP SPD/COMP/SHT SPN/SLEW FLL/RES SPINDLE BLOCK & DAC BRK/DLY SPN/I/COMP SPIN/GND2 VPDOWN COIL/C SPIN/GND1 COIL/A COIL/B VSPIN/2 SPN/I/SNS VRECT VSPIN/1 CENTER TAP DRIVER CTAP SYNTH/HALL VOLTAGE TRIPLER VLTRIP VHTRIP C2LOW C2HIGH VPARKOUT C1LOW C1HIGH VVCM/1 VCM/MINUS VVCM/2 VCM/PLUSVCM/I/SNS/2VCM/I/SNS/1 220pF 4 - 12MHz TBD 62K 10nF 12.5KΩ typical 250KΩ typical 4nF 1nF 4M Ω 1µFmin(10µF Recommended) e.g. 2.5KΩ VCM coil 330nF (Typ) 330nF (Typ) for Tripler operation not used for Doubler operation 330nF(Typ) 330nF(Typ) 0.83Ω (min)3.3Ω (min)220K Ω 100nF40K Ω FOR 0.5V RETRACT Connected forDoubler operation VCC 1.5nF APPLICATION DIAGRAM L6260
The duration of the brake delay is defined by an external resistor and capacitor connected to the brake delay pin (BRK_DLY). Charge stored in an external capacitor connected to the Voltage Tri- pler (VPDOWN) is used to supply the brake delay circuit after the loss of power. During the application of power to the IC, the power on reset signal (POR) is asserted, forcing all registers to their default state (see @POR col- umn of the register definitions) and disabling the VCM and spindle drivers. Once the supply volt- age has exceeded the Voltage Good (VGT) threshold, the POR delay begins. When this delay has expired, POR is de-asserted. It is this delay whose duration is determined by an external ca- pacitor connected to the POR_D LY pin. When a low voltage condition is detected (the supply voltage falls below the VGT) the following happens (in order): 1) Internal registers are reset and POR is as- serted. 2) The automatic parking of the actuator is en- abled and the brake delay starts. 3) After the brake delay expires, all low side driv- ers are enabled to brake the spindle. Serial Interface The serial interface is designed to be compatible with the Intel 80196 (and other similar micros) se- rial interface but is capable of faster data rates, up to 10 MHz. All read and write operations must consist of 16 bits, with the 80196 this would be two 8 bit accesses. The first four bits are address and the next 12 are data. If the address is a read register then the L6260 will use the SCLK from the system to shift out 12 bits of data from the ad- dressed register. The system must provide 16 SCLK pulses to insure that the read operation completes. SYMBOL DESCRIPTION MIN. TYP. MAX. UNITS tRWS R/W setup time to SCLK going high 100 ns tSLS SLOAD setup time to SCLK going high 100 ns tRWH R/W hold time after SCLK going high 100 ns tSLH SLOAD hold time after SCLK going high 100 ns tSCKD SCLK high to Data Valid 30 50 ns tRWD R/W High to Data Valid Data bit D[0] valid from HiZ 30 50 ns tAS Address setup time to SCLK going high 30 ns tDS Data setup time to SCLK going High 30 ns tAH Address Hold after SCLK going high 10 ns tDH Data Hold time after SCLK going High 10 ns tSDZ SDIO tri-state after SLOAD going High 30 ns tRWZ SDIO tri-state after R/W going low 30 ns tPER Minimum SCLK period 100 ns tREC (*) Recycle - Time between successive accesses 100 ns (*) For 10MHz system clock operation (in other words. 1 or more clock cycles of SCLK). Serial Interface Truth Table R/W SLOAD SDIO DIRECTION 1 1 Tri-state (Port unselected) Tri-state 0 1 Tri-state (Port unselected) Tri-state 0 0 Address/Data input Input 1 0 Data output Output L6260
certain transient conditions, the control loop which regulates the load current can recirculate, causing the VCM_I_SNS voltage to be different from the commanded voltage. This information is useful in optimizing the command profile during a seek. The retract voltage is set by external components. The current loop bandwidth is greater than 20Khertz. VCM DAC The VCM DAC consists of 10 bits via the DAC, 1 bit sign and 1 gain bit. However, externally this can be viewed as being a single 11 bit signed value with a gain bit in the MSB position. The sign bit controls the direction of the current. Positive values of the DAC are regarded as moving the actuator towards the inside diameter (this is re- quired for parking/braking). The magnitude is con- verted to a voltage which is used for closed loop regulation of the magnitude of the load current. The gain bit Retract Automatic actuator retraction is initiated when any of the following conditions occur: disabling the spin system while the VCM system is still en- abled, excessive junction temperature (thermal shutdown), loss of power or microprocessor is- sued retract. In all cases except the loss of power, the voltage applied to the voice coil is lim- ited by an active clamp. When power is lost, the BEMF generated by the spinning motor is recti- fied and applied across the voice coil to perform the parking operation. Command retract is activated via the System Control Register. VCM Gain Considerations I OUT = ± 0.25⋅DAC_VALUE 1024 ⋅ 1 R S1 (High current setting) or IOUT = ± 0.25⋅DAC_VALUE 1024 ⋅ 1 R S1 + R S2 (Low current setting) Modes of Operation The L6260 provides for four different modes of operation, namely, Unipolar, Bipolar, Tripolar and Tristate. The Tripolar mode is included for achiev- ing reliable start-ups in a stuck rotor condition (lengthening drive life-time). These modes are in- itiated via the System Control Register A, bits 7 & 8 as follows: Bit 6 Bit 7 # of drivers on Tristate 0 0 None Unipolar 0 1 1 low side, no high side Bipolar 1 0 1 low side and 1 high side Tripolar 1 1 1 high side and 2 low side OR 2 high side and 1 low side Spindle compensation and Loop Equations This material will be available in the next version of this datasheet. Spindle State Machine The spindle state machine provides the logic and timing signals to the spindle driver in support of the various modes of operation. When the spindle driver is disabled (via the Sys- tem Control Register), the state machine puts the spindle driver into a high impedance mode and places all spindle related circuit into a reduced power mode. After a POR, at boot up or after RESET (via Sys- tem Control Register) the state machine is in the known state as defined by the System Control Registers (A & B) initial condition after POR (see the @POR column of these registers). When in Unipolar mode the commutation se- quence is CTR/lA, CTR/lB CTR/lC where lA = lower A driver (NOTE: Unipolar mode is only guaranteed at 3V operation). In Bipolar the com- mutation sequence is uA/lB (upper A and lower B), uA/lC, lC/uB, uB/lA, lA/uC and uC/lB. In Tripo- lar mode the state machine does not auto com- mutate, the microprocessor must increment the state. The sequence is uA/lBC (upper A and lower B & C), uAB/lC, uB/lAC, uCB/lA, uC/lAB and uAC/lB. The Uni/Bi/Tri-polar operation is set by two bits in the System Control Register A (3.7- 3.8) described above (Modes of Operation). If the RUN/SEARCH bit (System Control Register A, bit 4) is false or 0 (SEARCH mode), the com- mutation state only increments when the INC STATE bit is strobed (also in the same register, bit 3). If the RUN/SEARCH bit is true or 1 (RUN mode) the state will increment either on a INC STATE strobe or if a qualified BEMF CROSSING occurs the state will increment after the commuta- tion delay times out. If either THERMAL=1 (register.bit 0.0) or the POR=0, all the drivers are turned off. Tristate is the default mode of operation at power up. Period counters and delay and masking func- tions The period counter is an internal 11 bit register that is used to time the interval between succes- sive zero crossings. Whenever a zero crossing is encountered, the period counter is loaded into L6260
both a mask counter (9 bits) and a delay counter (11 bits). The period counter is automatically re- set to count the next zero crossing period. The clock used for the period and mask counters is a function of the system clock. If the FCLK (the system clock) is set to the 8-12MHz range then the period and mask counters are clocked at 1/64 of the system clock, other wise the registers are clocked at 1/32 of the system clock. The delay counter clock is programmable via the SPIN COM DLY bits in the Spin Control Register (2.8-2.11). This value is used to divide down the system clock. Since there is 60 electrical degrees be- tween zero-crossings, the delay counter can pro- vide 1.875 through to 28.125 electrical degree de- lay at 1.875 degree increments. When the period counter reaches zero, the mask- ing of the zero-crossing starts (to avoid seeing current recirculation spikes). The delay counter then starts to count down and when it reaches zero the masking of the BEMF is released so that zero crossings can once again be detected. The masking hides the commutation of the motor which takes place during the mask. The clocking frequency of the mask and delay counters is identical. However, the delay is 11 bits and the mask only 9 bits. This means that the mask can provide 15 electrical degrees of mask- ing time. In the System Control Register B, bit MAKE_PHASE (4.11) a bit value of zero gives this 15 electrical degrees mask time but a one gives 7.5 electrical degrees of mask. Speed Control & F.L.L. The rotational position of the motor is inferred from the BEMF wave form generated by the float- ing coil. The chip uses the instant of a particular zero-crossing and the period between successive zero crossings to dictate the commutation tim- ings. The complete control loop is on chip and the speed is controlled by a reference clock FCLK. The speed control loop uses a frequency locked loop which in conjunction with an external compen- sation network brings the frequency of the ta- chometer signal to be equal to the internally gener- ated reference frequency. The tachometer signal can either be the BEMF signal divided down to a once per mechanical revolution signal or an exter- nally generated tachometer signal, sector burst. The output of the speed control is a current de- mand signal that goes to the Spindle Driver. The spindle current and the commutation delay is programmed via the Spin Control Register. There is a ”fine” and a ”coarse” counter that defines the speed of the motor. In more detail, the two registers are used in con- junction with two down counters which form a fre- quency detector that in turn creates feedback through to a charge pump to maintain the motors speed regulation. The course counter is 12 bits and is clocked at th the rate of the frequency clock (FCLK). The fine counter is clocked at 1/4th FCLK. The on chip Frequency Locked Loop (FLL) uses the electrical cycle pulses (”ec pulse”) to time the motors rota- tion. Upon the first ec pulse, the course register’s contents (loaded via the serial port) is loaded into the internal course counter is then loaded from its corresponding register. The fine counter then also immediately starts to count down. In theory (but not normally in run mode, possibly at start up) the fine counter could count down through zero an continue counting down the 2’s complement of the original fine counter value. The period between the start of the course counter and the zero crossing during the fine counter op- eration is the programmed period. Any differences between the desired period and the ec pulse (zero crossing) is the error in the transconductance loop and corrective action is take by the charge pump. This error is a number given from a counter starting when the fine counter reaches zero and resetting when the BEMF pulse occurs. The vice versa hap- pens if the BEMF anticipate the ending of the fine counter. The error number is loaded in REG. 7. The course and fine counter arrangement is guarateedto work in all possible circumstances (pro- viding there is enough BEMF). For example if the zero crossing is within or outside the fine window or even if the zero crossing is in the course register range. Thissystem will even work if the zero crossing occurs across multiple course/finecycles. The FLL has a prescaler (defined by the System Control Register bits EL_MECH and 8_12P (3.10 & 3.5) that changes the cycle counting mecha- nism between electrical, 8 pole or 12 pole (i.e. di- viding the ec clock by 1,4 or 6) respectively. The procedure for setting the motor speed is as follows: let’s call T0 this quantity. T0 =60 SPEED DoingT0 ⋅0.9⋅FCLK 64 we obtain Ncourse e. g. the number to load in the course register. If this number exceed 4096 the desired speed is not achievable. Let’s call ErrNc the decimal part of Ncourse doing T0 ⋅0.1⋅Fclk 4 + ErrNc⋅16 we obtain Nfine e.g. the numberto load in the fine register. If this number exceed 2048 all the procedure must be repeated The spindle is enabled via the System Control Registers. The slew rate is defined by attaching a resistor to ground from the SPN _SLW pin. The current loop has a compensation RC network on the SPN _I_COMP pin and the sense resistor is at- tached to the SPN _I_SNS pin (to ground). L6260
Assuming that your motor requires 200mA run current then the sense current would be 200/500 = 400µA. Therefore for 1 volt at the sense pin a 2500 Ohm resistor is required (R = 1/400µA). Also assuming you require 1 Amp start-up cur- rent. You need to change the sense range to 5X. This also gives 1A/2500 = 400µA or 1V on a 2500 Ohm resistor. In the normal ”at-speed” running the voltage at this pin will vary between 0 and 2 volts approxi- mately (e.g. when using the FLL). When using the spindle DAC the voltage swing is from 0 to 1.25 Volts Using the Spindle DAC for Start-Up When the SPEED bit in the System Control Reg- ister A (Register 3.9) is set (to 1), the speed con- trol is given to the DAC (i.e. control is removed from the FLL). The normal method of start-up is achieved using the DAC rather than the FLL. However the FLL can be used from zero speed with an align-and-go algorithm but start-up will be slower. The 8-bit DAC gives 4.88mV per step with a maximum voltage of 1.25V. Start-Up example Assume that one needs 1A max. start current and expects a running current of 200mA. For startup, one would program the SFETGAIN bit to 0 and the SPEED bit to 1. With this value, 1A spindle current results in 1A/3000, or 333µAa t the SPN_I_SNS pin. Using a 3300Ω resistor and programming the Spindle DAC to 1V results in the desired 1A startup current. The startup algorithm is implemented by writing into the Spindle Control Register A. Once running speed is attained, the AT_SPEED bit (System Status Register, bit 7) will go to a 1. The CPU then sets the SFETGAIN bit to 1 and the SPEED bit to 1. The normal running current of 200mA again results in 200mA/600, or 333µA at the SPN_I_SNS pin. The FLL will regulate the speed with a npminal value of 1V. During ”DAC control” the FLL change pump ca- pacitor is shorted to the Spindle DAC voltage.. This allows for a smoother transition from DAC to FLL control. Power Devices When S_BIPLOAR (internal) is turned on and saturated when the spindle driver is placed in unipolar mode and has an Rdson of 1 Ohm (worst case over temperature). To support retract with- out requiring an isolation diode the transistor is designed so as not to conduct current from source to drain even if the supplies Vp and Vdd are at ground and the source is at a positive volt- age. S_A_U, S_B_U and S_C_U are the upper spindle drive transistors. They are active whenever the drive is in bipolar mode and can be turned on in pairs in tripolar mode. To support retract without requiring an isolation diode these transistors are designed so as to not conduct current from source to drain even if the supplies Vdd and Vp are at ground and the source is at a positive volt- age. S_A_L, S_B_L and S_C_L are the lower spindle drive transistors. They are active in unipolar, bipo- lar and tripolar drive. In linear mode the active transistor’s gate drive is controlled so as to bring the current in the motor to the level set by the speed control compensation circuit or the current SPINDLE MOTOR B-POLAR PHASE A PHASE B PHASE CCENTER TAP S-A-U S-B-U S-C-U S-A-L S-B-L S-C-L VCM-A-U VCM-B-U VCM-A-L VCM-B-L SR-A SR-B SR-C VRECT VDD VCM PARK CONTROLVPARK D94IN100 Figure 11. L6260
limit DAC. The power circuits will be as shown in the follow- ing figure 11. Synth Hall The Synth Hall pin can be programmed to provide one of two possible output wave forms (see regis- ter definitions). By setting the SYNTH_HALL bit in register System Control Register B (4.5) to zero, the signal is a once per BEMF crossing signal which has the same phase as the BEMF amplifier on chip with all the noise and false transitions re- moved. With this bit set to one, a once per electri- cal cycle signal with 50% duty cycle is produced. Brake The BRAKE mode commands a retract & then turns on the lower three drivers, S_A_L, S_B_L and S_C_L, to cause immediate braking of the spindle. Retract The retract voltage is defined by a resistor to ground from the R ETRACT_ V pin. Test Circuits 1) I/O Mapping Test Mode. This mode is acti- vated by taking the TEST pin high and hold- ing the TRISTATE pin low. This puts the de- vice into a test mode that allows certain pins to be directly internally connected to other pins for the purpose of testing continuity of solder joints on a board. The following table defines which pins are I/O mapped and which is an input and which is an output. Notice that I/O mapped pins in one group are not physi- cally adjacent in the package allowing more thorough testability. INPUT PIN # INPUT PIN NAME OUTPUT PIN # OUTPUT PIN NAME
20 R/W 11 SDIO
9 SLOAD 11 SDIO
10 SCLK 22 SYNTH_HALL
12 FCLK 22 SYNTH_HALL
50 UV1 5 POR
51 UV2 5 POR
2) Digital and Analog Test Mode. This mode is activated by taking both the TEST pin and TRISTATE pin high. Once this has been done the SCLK pin of the serial interface is used to clock out digital data through the DTEST pin. Simultanously, the ATEST pin cycles through carrying different analog signals from around the chip. 1 Nominal Bandgap Voltgage (normally 1.25V) Postive/Negative incrementing of the FLL 2 Low Bandgap Voltage (normally 1.23V) Spindle mask 3 Bias Voltage (normally 0.5V) Spindle delay
4 Spindle DAC Output FCLK/16 or FCLK/32 depending on
CLK_PRESCALE bit in System Control Reg B (4.4)
5 VCM DAC Output BEMF Comparitor output (raw)
6 Temperature Shutdown Voltage (input - used to
alter the point at which thermal shutdown starts operation) VCM predriver (A)
7 Connected to the A gate of the spindles Low Side
Driver. Allows Rds(on) testing. VCM predriver (F). Sleep & Idle Functions MODE STATE POWER LEVEL POWER DISS. Ready Spin & VCM enabled Full 20mA Idle Spin enabled, VCM disabled Reduced 10mA Sleep Both spin and VCM disabled Minimum 2mA (typical) 5mA (max) INVALID Spin disabled, VCM enabled* Spindle set to low gain If the spindle is disabled while the VCM is enabled the automatic parking function is invoked. 3) Tristate Test Mode. This mode is activated by keeping the TEST pin low and taking the TRISTATE pin high. This disables the digital outputs, specifically SYNTH_HALL, POR & SDIO. 4) No Test Modes. All test modes are disabled by keeping the TEST pin & TRISTATE pin low L6260
MATCAD ANALYSIS OF l6286 VCM CURRENT CONTROL LOOP (High Gain) (User specified parameters) R c : = 240⋅103 Compensation resistance C c : = 240⋅10-9 Compensation capacitance R1 : = 20 Coil resistance L : = 1.1⋅10-3 Coil inductance C s : = 100⋅10-9 Snubber capacitace R n : = 75 Snubber resistance Vdac :=4 0⋅10-3 DAC Voltage R s : = 0.8 Sense resistance Id := Vdac R s Output current Id = 0.05 (Device Parameters) gmn : = 24.2⋅10-6 Nulling OTA transconductance, with± 20% variation R on : = 3.18⋅106 Nulling OTA output resistance, with± 50% variation C on :=5 0⋅10-12 Nulling OTA output capacitance, with± 10% variation gm1 : = 1100⋅10-6 Main OTA transconductance, with± 20% variation R o1 : = 1.773⋅106 Main OTA output resistance, with± 50% variation C o1 : = 1.6⋅10-12 Main OTA output capacitance, with± 10% variation gm2 = 0.964√ Id FET transconductance, with æ 10% variation gm2 = 0216 VA = 68.7 Early voltage of FET, with ± 5% variations R o2 = VA Id FET output resistance Ro2 = 1.374⋅103 R a : = 420 Predriver output resistance, with ± 20% variation C sb : = 10.2⋅10-12 FET source-bulk capacitance, with± 10% variation C db :=4 9⋅10-12 FET drain-bulk capacitance, with± 10% variation C gd :=1 1⋅10-12 FET gate-drain capacitance, with± 10% variation C gs : = 156⋅10-12 FET gate source capacitance, with± 10% variation 1ST STAGE (OTA) TRANSFER FUNCTION: i: =√ -1 f(n) : = 10n S(n) : = 2⋅i⋅π ⋅10n n : = 2, 2.01,⋅7 A1: = gmn⋅Ron ⋅gm1 ⋅Ro1 A1 = 1.501⋅105 fp1= 1 2⋅ π ⋅ R on ⋅Con fp1 = 1.001⋅ 103 fp2= 1 2⋅ π ⋅ R eq ⋅Co1 fp2 = 4.706⋅ 105 fz1= gmn 2⋅ π ⋅ C on fz1 = 7.703⋅104 fzc= 1 2⋅ π ⋅ R c ⋅C c fzc = 6.631 Req = R o1 ⋅Rc Ro1 + Rc Req = 2.114⋅105 fpc= 1 2⋅ π ⋅ (R c + R o1)⋅C c fpc =0.791 L6260
H1 (n):= A1 ⋅ 1 + S(n) 2 ⋅ π ⋅ fzc 1 + S(n) 2 ⋅ π ⋅ fz1 1 + S(n) 2 ⋅ π ⋅ fzc 1 + S(n) 2 ⋅ π ⋅ fp1 1 + S(n) 2 ⋅ π ⋅ fp2 (OTA) 2ND STAGE (POWER NMOS) TRANSFER FUNCTION: Zsn(n) : = Rn + 1 Cs ⋅S(n) (snubber) ZL(n) : =Zsn(n)⋅ZLo(n) Zsn(n)+ ZLo(n) (load) ZLo(n) : + LS(n) + R1(motor) Ci : = Cgs = Cgd Co : = Cgd + Cdb Ra + Ci·S(n) Ro2 +- (Cgd·S(n) - gm2) - (Cgs·S(n) + gm2) Co·S(n) + 1 ZL(n) - (Cgd·S(n) 1 Ra Ro2 Ra + Ci·S(n) Ro2 +- (Cgd·S(n) - gm2) - (Cgs·S(n) + gm2) Co·S(n) + 1 ZL(n) - (Cgd·S(n) Ro2 - (Cgs·S(n) Ro2 - gm2 + Ro2 +(Cgs + Csb)·S(n) + gm2 + 1 Rs H2(n) : = D96IN361 {H 2(n)= left|[{matrix{ccol L6260
100 1K 10K 100K 1M f(n) -20 -10 (dB) 20⋅log( H(n) ) D96IN359 OPEN LOOP RESPONSE: H(n): = H1(n)⋅H2(n) |H(0)| = 1.367⋅104 |H2(0)| = 0.145 MAGNITUDE RESPONSE (dB) 100 1K 10K 100K 1M f(n) -180 -135 -90 -45 135 (dB) D96IN360 arg(H(n))⋅ 360 2⋅π PHASE RESPONSE (%) L6260
TQFP64 PACKAGE MECHANICAL DATA DIM. mm inch A 1.60 0.063 A1 0.05 0.15 0.002 0.006 D 12.00 0.472 D1 10.00 0.394 D3 7.50 0.295 e 0.50 0.0197 E 12.00 0.472 E1 10.00 0.394 E3 7.50 0.295 L1 1.00 0.0393 K 0°(min.), 7°(max.) A A1B C 3348 E D e K B TQFP64 L Seating Plane 0.10mm L6260
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS- THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. 1996 SGS-THOMSON Microelectronics – Printed in Italy – All Rights Reserved SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands - Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. L6260