L6254

L6254 STMICROELECTRONICS | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 17

Technical content

12V (±10%) OPERATION. REGISTER BASED ARCHITECTURE MINIMUM EXTERNAL COMPONENTS BICMOS + VERTICAL DMOS (1.5mm) VCM DRIVER 1.5A DRIVE CAPABILITY 0.9W TOTAL BRIDGE IMPEDANCE AT 25 °C LINEAR MODE PHASE SHIFT MODULATION (PWM MODE) INSTANTANEOUS, (GLICH FREE) SWITCH BETWEEN THE 2 MODES CLASS AB OUTPUT DRIVERS ZERO CROSSOVER DISTORSION

14 BIT DAC DEFINE OUTPUT CURRENT

SELECTABLE TRANSCONDUCTANCE

4 PROGRAMMABLE PARKING VOLTAGE

2.0A DRIVE CAPABILITY 0.8W TOTAL BRIDGE IMPEDANCE AT 25 °C BEMF, INTERNAL OR EXTERNAL, PROC- ESSING SENSOR-LESS MOTOR COMMUTATION PROGRAMMABLE COMMUTATION PHASE DELAY LINEAR MODE AND CONSTANT TOFF PWM OPERATION MODE INTERNAL FREQUENCY LOCKED LOOP SPEED CONTROL (FLL) BEMF RECTIFICATION DURING RETRACT BUILT-IN ALIGNAMENT&GO START-UP INDUCTIVE SENSING START UP OPTION RESYNCHRONIZATION DYNAMIC & REVERSE BRAKE CONTROLLABLE OUTPUT SLEW RATE OTHER FUNCTIONS 12V AND 5V MONITORING WITH EXTERNAL SET TRIP POINTS AND HYSTERESIS POWER UP/DOWN SEQUENCING LOW VOLTAGE SENSE SLUG FOR POWER DISSIPATION THERMAL SHUTDOWN AND PRETHERMAL WARNING

DESCRIPTION

The L6254 integrates into a single chip both spin- dle and VCM controllers as well as power stages. The device is designed for 12V disk drive applica- tion requiring up to 2.0A of spindle and 1.5A of VCM peak currents. A serial port with up to 25 MHz capability provides easy interface to the microprocessor. A register controlled Frequency Locked Loop (FLL) allows flexibility in setting the spindle speed. Integrated BEMF processing, digital masking, digital delay, and sequencing minimize the number of external componentsrequired. Power On Reset (POR) circuitry is included. Upon detection of a low voltage condition, POR is as- serted, the internal registers are reset, and spin- dle power circuitry is tri-stated. The BEMF is recti- fied providing power for actuator retraction followed by dynamic spindle braking. The device is built in BICMOS technology allow- ing dense digital/analog circuitry to be combined with a high power DMOS outputstage. This is preliminary information on a new product now in development. Details are subject to change without notice. April 1999 TQFP44 (10x10mm) ORDERING NUMBER: L6254 L6254 12V DISK DRIVE SPINDLE & VCM, POWER & CONTROL “COMBO” PRODUCT PREVIEW BICMOS TECHNOLOGY

LOCK LOOP SPINDLE SEQUENCER REFERENCE VOLTAGE GENERATOR

14 BIT

A A=4 SUPPLY CP FLL_RES FLL_FILTER SYS_CLK FCOM SPN_COMP BRK_CAP PWM/SLEW VCC POR_DELAY PORB VDD GND DGND V12/2 VCM_CAL ERROR_IN ERROR_OUT SENSE_OUT OUT_A OUT_B RSENSE OUT_C VCM_A+ VCC VCM_A- SENSE_IN- SENSE_IN+ D99IN1042 VCM_GND CTAP CS SW1 SDATA SCLK SDEN TR_12V TR_5V ISENSE INDEX THERMAL DAC VCM CALIBRATION BEMF RECTIFICATION PARKING VCM CURRENT CONTROL PSM/LIN START-UP RE_SYNC DYNAMIC/ REVERSE BRAKE SPINDLE CURRENT CONTROL PWM/LIN BEMF PROCESSING B C SERIAL INTERFACE REGISTERS BLOCK DIAGRAM 18 19 20 21 22 44 43 42 41 39 40 38 37 36 35 34 R_SENSE I_SENSE OUT_C CTAP FCOM PWM/SLEW INDEX OUT_A R_SENSE OUT_B GND BRK_CAP VCC DGND SYS_CLK SDATA SDEN SCLK VDD V12/2 FLL_FILTER VCM_CAL SPN_COMP VCC AGND DAC ERROR_IN TR-12V ERROR_OUT SENSE_OUT POR_DELAY TR_5V PORB VCM_GND SENSE_IN+ VCM_A- CS CP VCC SW1 FLL_RES VCC SENSE_IN- VCM_A+ D98IN847 12 13 14 15 16 PIN CONNECTION L6254

PIN DESCRIPTION (Pin Types: D = Digital, P = Power, A = Analog) N. Name Function 1 FCOM Output of the Spindle zero cross or Current Sense circuit. 2 CTAP Spindle Central Tap used for differential BEMF sensing. 3 PWM/SLEW RC network sets the Spindle Linear Slew Rate and PWM OFF-Time. 4 OUT_C Spindle DMOS Half Bridge Output and Input C for BEMF sensing. 5 I_SENSE Input to sense the voltage the SPINDLE Sense Resistor. 6 R_SENSE Output connection for the Motor Current Sense Resistor to ground. 7 OUT_B Spindle DMOS Half Bridge Output and Input B for BEMF sensing. 8 GND Spindle Ground (Substrate). 9 R_SENSE Output connection for the Motor Current Sense Resistor to ground. 10 OUT_A Spindle DMOS Half Bridge Output and Input A for BEMF sensing. 11 INDEX Input to allow Spindle to be locked to Index (servo) pulse. 12 BRK_CAP Storage Capacitor for brake circuit. typically 5.9V. 13 VCC +12V Power Supply for Spindle Power section. 14 DGND Digital Ground. 15 SYS_CLK Clock Frequency for system timers and counters. 16 SDEN Serial Data Enable. Active high input pin for the serial port enable. 17 SDATA Serial Port Data. Input/Output pin for serial data, 8bits of instruction/address followed by 8 bits of data. Open pin is at logic low as an input. 18 SCLK Serial Port Data Clock. Positive edge triggered clock input for the serial data. 19 VDD Digital/Analog power supply. +5V nominally. 20 V12/2 Reference Output for VCM control loop. Typically, half of the VCC except when parking. 21 FLL_FILTER Speed loop R/C compensation connection used for FLL mode operation. 22 VCM_CAL VCM loop offset voltage used for calibration. 23 CP External Main Charge Pump Capacitor, Typically, Vz+Vcc is about 17.8V 24 CS External Charge Pump Capacitor. 25 VCC +12V Power Supply for VCM Power section. 26 VCM_A- VCM Power Amplifier negative output terminal. 27 SENSE_IN+ Non inverting Input of the Sense Amplifier for VCM block. 28 VCM_GND Ground for VCM Power section. 29 SENSE_IN- Inverting Input of the Sense Amplifier for VCM block. 30 VCM_A+ VCM Power Amplifier positive output terminal. 31 VCC +12V Power Supply for VCM Power section. 32 FLL_RES Resistor for setting accurate bias current sources for the chip (62K required). 33 SW1 External ISOFET driver. 34 PORB Power on Reset Output. Low signal indicates the failure of the supplies.

35 TR_5V Set Point Input for 5V Supply Monitor ( 2V threshold, 100mV Hysteresis)

36 POR_DELAY Capacitor connection to set the Power on Reset Delay (3V threshold, 2µA charging)

37 SENSE_OUT Output of the Sense Amplifier. 38 ERROR_OUT Output of the Error Amplifier. 39 ERROR_IN Inverting Input of the Error Amplifier.

40 TR_12V Set Point Input for 12V Supply Monitor (2V threshold, 100mV Hysteresis)

41 DAC Output of the VCM DAC. 42 AGND Analog Ground. For bang gap voltage reference. 43 VCC +12V Power Supply for Spindle Power section.

44 SPN_COMP External RC network that defines the compensation of the Spindle Transconductance Loop

in Linear Mode. L6254

ELECTRICAL CHARACTERISTICS (All specifications are for 0 < Tamb <7 0°C, VCC = 12V; VDD = 5V, FLL_RES = 62kΩ , unless otherwise specified.) Symbol Parameter Test Condition Min. Typ. Max. Unit POWER SUPPLIES VCC 12V Supply 10.8 13.2 V IVCC VCC Current SPINDLE + VCM 20 mA SPINDLE ONLY 7 mA VCM ONLY 12 mA Vrectified VCC Supply Rectified 3.5 13.2 V V dd 5V supply 4.5 5.5 V IVdd 5V supply SPINDLE + VCM 6 mA SPINDLE ONLY 7 mA VCM ONLY 12 mA ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value Unit VCC Maximum Supply voltage -0.5 to 14 V Vdd Maximum Logic supply -0.5 to 6 V Vin max Maximum digital input voltage V dd +0.3V V Vin min Minimum digital input voltage GND - 0.3V V SPINDLE Ipeak Spindle peak sink/source output current 2.1 A VCM Ipeak VCM peak sink/source output current 1.6 A Ptot (*) Maximum Total Power Dissipation ≈ 1.7 W Tstg,Tj Maximum Storage/Junction Temperature -40 to 150 °C THERMAL DATA Symbol Parameter Value Unit R th j-case Thermal Resistance Junction to Case ≈ 20 °C/W R th j-amb(*) Thermal Resistance to Junction to ambient ≈ 40 ≈ 25 with soldered slug °C/W °C/W (*) In typical application with multilayer 120x120mm Printed Circuit Board. RECOMMENDED OPERATING CONDITIONS Symbol Parameter Value Unit VCC Supply voltage 10.8 to 13.2 V Vdd Maximum Logic supply 4.5 to 5.5 V Tamb Operating Ambient Temperature 0 to 70 °C Tj Junction Temperature 0 to 125 °C L6254

Symbol Parameter Test Condition Min. Typ. Max. Unit THERMAL SENSING TSD Shutdown Temperature 150 180 °C THYS Hysteresis 60 °C TEW Early Warning T SD -25 °C SUPPLY MONITOR V TR Trip Point Input Rising 1.92 2 2.08 V VHYS Hysteresis Voltage Input falling 100 mV IDLY Porb Delay Current TR_5V, TR_12V > V TR Vpordly = 2V 1.5 2 2.5 µA R on_por Porb Pull Down Ron V dd > 2V and sink 1mA Vpordly=2 V 500 Ω VDLY Porb Dly Threshold TR_5V, TR_12V > V TR 2.5 3.0 3.5 V IIN Input Current V IN <4 V - 1 1 µA VOLTAGE BOOST VBOOST Output Voltage V CC +5 V CC +6.3 V Fosc Internal Oscillator 130 200 250 kHz SW1 OUTPUT R GATE Gate Driver for External Mosfet Internal Resistor to CP 200 k Ω VGATE Off Gate State Voltage for External Mosfet IO = 1mA VCC = 3.5V 0.7 V DIGITAL LOGIC LEVELS VIH Input Logic ”1” V DD = 5.5V 2.4 V V IL Input Logic ”0” V DD = 4.5V 0.5 V VOH Output Logic ”1” I SOURCE =2 0µAV dd-0.2 V V OL Output Logic ”0” I SOURCE = -400µA 0.4 V FSYSCLK System Clock 20 25 MHz VCM, DAC Resolution 14 Bits Differential Linearity 1 LSB Change -Tested By design -0.5 0.5 LSB Integral Linearity 9 Bits Midscale Offset Referenced to V CC /2 -5 5 mV TC Convertion Time 5 µs Full Scale Voltage Referenced to V CC /2 ±1V Full Scale Error -4 4 % VCM, ERROR AMPLIFIER AVOL Open Loop Gain DC 50 db VOS Input Offset Voltage -5 5 mV IIB Input Bias Current -250 250 nA ELECTRICAL CHARACTERISTICS (Continued) L6254

Symbol Parameter Test Condition Min. Typ. Max. Unit VICM Input Common Mode Range V CC /2- 0.5 VCC /2+ 0.5 V Vclamp Output Clamp Voltage -1mA < I O <1 m A Lowside/Highside clamp VCC /2± 2.2V V FODB Unity Gain Bandwidth 10 MHz VCM, POWER STAGE R DS(ON) Output ON Resistance (Each device) Tj=2 5°C Tj= 125°C 0.5 0.8 Ω Ω IO Operating Current 1.3 A IO(LEAK) Output Leakage Current V CC = 14V 1.0 mA VCM, CURRENT SENSE ANPLIFIER AV Voltage Gain 3.88 4 4.12 V/V VICM Input Common Mode Range -0.3 V CC +0.3 V VOCM Output Common Mode Range -3mA < I O <3 m A 2 V CC -2 V VOS Output Offset Voltage SENSE_IN ( ±)=V CC /2 -15 15 mV F3dB 3dB Bandwidth 1 MHz CMRR Input Common Mode Rejection 50 dB PSRR Power Supply Rejection Ratio 60 dB VCM, RETRACT Vpark RETRACT VOLTAGE PKV_1 = 0 & PKV_2 = 0 PKV_1 = 0 & PKV_2 = 1 PKV_1 = 1 & PKV_2 = 0 PKV_1 = 1 & PKV_2 = 1 725 531 398 1080 mV mV mV mV Tretract Retract Time limited by the internal oscillator 200kHz RT0 = 0 & RT1 = 0 RT0 = 0 & RT1 = 1 RT0 = 1 & RT1 = 0 RT0 = 1 & RT1 = 1 320 640 160 320 ms ms ms ms SPINDLE, PWM CURRENT SENSE COMPARATOR T DLY Delay to FCOM Out 200 500 ns SPINDLE, POWER STAGE R DS(ON) Output On Resistance (Each device) Tj=2 5°C Tj= 125°C 0.45 0.74 Ω Ω IO Start-Up Current 2A IO(LEAK) Output Leakage Current VCC = 14V 1.0 mA dVO /dt Output Slew Rate (Linear) R slew = 100kΩ 0.2 0.3 0.5 V/ µs Output Slew Rate (PWM) Reg#8Eh, Bit 0 = 0 Reg#8Eh, Bit 0 = 1 V/µs V/µs BEMF MIN Minimum BENF Voltage for Detection 20 28 40 mVp-p VHYS Hysteresis 15 mV FLL CHARGE PUMP OUTPUT ILEAK Off State Leakage 0 < Vfll_res , 3V -50 +50 nA ELECTRICAL CHARACTERISTICS (Continued) L6254

Figure 1. Serial Port Timing Information.

are provided before SDEN* goes low, the data transferis aborted. and instruction information. The first bit is R/W instruction bit, 0 is for WRITE and 1 is for READ. Following 7 bits are Address. Figure 2. Serial Port Data Transfer Format.

0 VDAC BIT8 VCM DAC bit 8

1 VDAC BIT9 VCM DAC bit 9

2 VDAC BIT10 VCM DAC bit 10

3 VDAC BIT11 VCM DAC bit 11

4 VDAC BIT12 VCM DAC bit 12

5 VDAC BIT13 MSB resistor ladder of the 14 bit VCM DAC

INTERNAL REGISTER DEFINITION VCM DAC (High and Low) Registers Bit 0 through 5 of the VCM DAC (High) Registers and bit 0 through 7 of the VCM DAC (Low) Registers control the absolute value of the voice coil current. Bit is the sign bit, controlling the current direction. All the 13 bits are part of a resistor divider network. Note. It is required to write on register 1 to make effective changes on register 0. Reg: Name: Type: Address: VCM DAC (Low) Registers Write only 1Eh BIT LABEL DESCRIPTION

0 VDAC BIT0 LSB resistor ladder of the 14 bit VCM DAC

1 VDAC BIT1 VCM DAC bit 1

2 VDAC BIT2 VCM DAC bit2

3 VDAC BIT3 VCM DAC bit3

4 VDAC BIT4 VCM DAC bit4

5 VDAC BIT5 VCM DAC bit5

6 VDAC BIT6 VCM DAC bit6

7 VDAC BIT7 VCM DAC bit7

Reg: Name: Type: Address: Spindle Control Register Write only 2Eh BIT LABEL DESCRIPTION 0 INCRE_SEQ A 0 to 1 transition of this bit increments the spindle Sequencer.

1 START_UP 1 = Spindle Internal start up, 0 = Spindle External start up

2 R_SEQ Reset Spindle sequencer. 1 = Reset sequencer to phase 1. 3 RUN 1 = Start Spindle ALIGN & GO, 0 = Reset Spindle control logic. 4 SPIN_EN Enable Spindle section. 1 = Enable, 0 = Disable. 5 MEC/ELEC Specifies electrical or mechanical cycle for Spindle FLL control. 1=Electrical, 0 = Mechanical. 6 PWM/LINEAR Selects Spindle PWM or Linear Output Current Control. 1 = PWM, 0=Linear. 7 EXT/INT External or internal Spindle loop feedback. 1 = external feedback via index pin. L6254

INTERNAL REGISTER DEFINITION Reg: Name: Type: Address: Spindle Delay Register Write only 3Eh BIT LABEL DESCRIPTION 0 MASK_TIME Spindle BEMF Mask Time. 0 = 15 degree, 1 = 7.5 degree 1 MIN2 Control Spindle PWM on time Min 1 Min2 Min. on Time 0 0 5.9 µs 2 MIN1 0 1 1.4 µs 10 1 2 µs 1 1 5.21 µs 3 8_12_POLE Selects 8 or 12 pole motors. 1 = 8 pole, 0 = 12 pole.

4 SD3 Spindle commutation delay MSB

5 SD2 Spindle commutation delay bit

6 SD1 Spindle commutation delay bit

7 SD0 Spindle commutation delay LSB

SD3-0 set the phase delay from BEMF zero crossing to the next commutation. The 30 theoretical degree value can be changed to compensate for switching and other delays that are always present. The delay adjustment range is from 1.875 through to 30 electrical degrees in 1.875 degree increments. Reg: Name: Type: Address: FLL Coarse Counter Register Write only 4Eh BIT LABEL DESCRIPTION

0 C4 Bit 4 of Spindle FLL Coarse Counter

1 C5 Bit 5 of Spindle FLL Coarse Counter

2 C6 Bit 6 of Spindle FLL Coarse Counter

3 C7 Bit 7 of Spindle FLL Coarse Counter

4 C8 Bit 8 of Spindle FLL Coarse Counter

5 C9 Bit 9 of Spindle FLL Coarse Counter

6 C10 Bit 10 of Spindle FLL Coarse Counter

7 C11 MSB of Spindle FLL Coarse Counter

INTERNAL REGISTER DEFINITION Reg: Name: Type: Address: FLL Coarse/Fine Counter Register Write only 5Eh BIT LABEL DESCRIPTION

0 F8 Bit 8 of Spindle FLL Fine Counter

1 F9 Bit 9 of Spindle FLL Fine Counter

2 F10 MSB of Spindle FLL Fine Counter

3 2/3_PHASE 1 = 2 Phase Brake, 0 = 3 Phase Brake

4 C0 LSB of Spindle FLL Coarse Counter

5 C1 Bit 1 of Spindle FLL Coarse Counter

6 C2 Bit 2 of Spindle FLL Coarse Counter

7 C3 Bit 3 of Spindle FLL Coarse Counter

Reg: Name: Type: Address: FLL Fine Counter Register Write only 6Eh BIT LABEL DESCRIPTION

0 F0 LSB of Spindle FLL Fine Counter

1 F1 Bit 1 of Spindle FLL Fine Counter

2 F2 Bit 2 of Spindle FLL Fine Counter

3 F3 Bit 3 of Spindle FLL Fine Counter

4 F4 Bit 4 of Spindle FLL Fine Counter

5 F5 Bit 5 of Spindle FLL Fine Counter

6 F6 Bit 6 of Spindle FLL Fine Counter

7 F7 Bit 7 of Spindle FLL Fine Counter

INTERNAL REGISTER DEFINITION Reg: Name: Type: Address: Spindle Status Register Read only 7Eh BIT LABEL DESCRIPTION 0 THERMAL Thermal Shutdown = 0 indicates that the chip temperature has exceeded 160 °C. The bit will reset (=1) when the temperature falls below 130°C. When Thermal Shutdown =0, the spindle logic will tristate both high and low side drivers, protecting the output circuitry.

1 THERM_WARN Thermal Shutdown Warning =0 indicates that the chip temperature is

approximately 25°C before the device goes in thermal shut down.

2 ROTOR_STUCK 0 = A sequential Spindle BEMF has not been detected

3 FAULT 1 = Rapid deceleration of the Spindle motor or High frequency on FCOM signal. 4 MASK_TIME Mask Time toggled to ”0” indicates that the Spindle BEMF is masked.

5 ERROR_LOCK 0 = Indicates error Spindle speed > 16msec/sample, either electrical or

mechanical. 6 ALIGN 0 indicate that the Spindle is in the Internal Start-Up Align Phase. 7 GO 0 indicate that the Spindle is in the Internal Start-Up Go Phase. Reg: Name: Type: Address: Spindle FLL Register Write only 8Eh BIT LABEL DESCRIPTION 0 SSLEW Spindle PWM (chopping) Slew Rate. 0 = 10V µS, 1 = 20VµS 1 ICP Spindle FLL Charge pump current. 1= 25 µA, 0 = 100µA. 2 Unused. Set = 0.

3 ISNS 1 = Puts output of the Spindle sense amplifier on FCOM pin and changes limit to

roughly 1/3 of normal.

4 IL1 Adjust maximum voltage on Spindle Rsense

5 IL0 Adjust maximum voltage on Spindle Rsense

6 CPL 1 = Spindle FLL Charge pump low

7 CPH 1 = Spindle FLL Charge pump high

”IL0” ”IL1” ”ISNS” V(I_SENSE) LIMIT ( ±10%) 0 0 0 0.45V 1 0 0 0.50V 0 1 0 0.55V 1 1 0 0.75V 0 0 1 0.15V 1 0 1 0.20V 0 1 1 0.25V 1 1 1 0.30V L6254

INTERNAL REGISTER DEFINITION Reg: Name: Type: Address: System Control Register Write only 9Eh BIT LABEL DESCRIPTION

0 PKV_1 VCM Parking Voltage

1 PKV_2 VCM Parking Voltage

2 VR 1 = connects internal VR reference (2V) to level shift Opamp (for

Vcm calibration).

3 RT0 (*) VCM Retract Time

4 DOUBLE 1 = Spindle Internal Start-Up Align and Energization time doubled. 5 VCM_EN Enable VCM section. 1 = Enable, 0 = Disable.

6 RT1 (*) VCM Retract Time

7 RETRACT 1= VCM retract

0 0 0.725V 0 1 0.531V 1 0 0.398V 1 1 1.080V 0 0 320ms 0 1 640ms 1 0 160ms 1 1 320ms (*) When program Retract Time (RT0 and RT1), Bit 2 REG#8Eh must be always written to 0. L6254

INTERNAL REGISTER DEFINITION Reg: Name: Type: Address: Test Control Register Write only AEh BIT LABEL DESCRIPTION 0 Unused. Set = 0 1 Unused. Set = 0 2 Unused. Set = 0 3 Unused. Set = 0

4 FLL_OUT 1 = Spindle Mech/Elec (see bit 5 register 2) output, 0 = Spindle

zero crossing output. 5 REV_BRAKE Spindle Reverse Brake command. 1 = Brake. “0” has to be reinserted to enable the spindle start up. 6 Unused. Set = 0

7 VB/DIS 1 = Disable Vboost

Reg: Name: Type: Address: VCM Control Register Write only BEh BIT LABEL DESCRIPTION 0 VCMS VCM PSM (chopping) Slew Rate. 0 = 10V/ µs, 1 = 20V/µs 1 VCMH 1 = Forces VCM outputs to be High in PSM mode. 2 SLEEP Unused (for future power saving mode). 3 COMSLEW Spindle PWM (phase commutation) Slew Rate. 0 = 30V µs, 1=2 V µs. 4 Unused. Set = 0 5 Unused. Set = 0 6 Unused. Set = 0 7 Unused. Set = 0 L6254

0 ID_REV_0 Minor Revision Bit 0. 1 ID_REV_1 Minor Revision Bit 1. 2 ID_REV_2 Minor Revision Bit 2. 3 ID_REV_3 Minor Revision Bit 3. 4 ID_REV_4 Minor Revision Bit 0. 5 ID_REV_5 Minor Revision Bit 1. 6 ID_REV_6 Minor Revision Bit 2. 7 ID_REV_7 Minor Revision Bit 3. Figure 3. Application Circuit.

TQFP44 (10 x 10) DIM. mm inch A 1.60 0.063 A1 0.05 0.15 0.002 0.006 C 0.09 0.20 0.004 0.008 D 12.00 0.472 D1 10.00 0.394 D3 8.00 0.315 e 0.80 0.031 E 12.00 0.472 E1 10.00 0.394 E3 8.00 0.315 L1 1.00 0.039 K 0°(min.), 3.5°(typ.), 7°(max.) A A1B Seating Plane C 2333 E D e K B TQFP4410 L 0.10mm .004 OUTLINE AND MECHANICAL DATA L6254

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics  1999 STMicroelectronics – Printed in Italy – All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands - Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. http://www.st.com L6254