L6225

L6225_03 STMICROELECTRONICS | Alldatasheet

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Technical content

■ OPERATING SUPPLY VOLTAGE FROM 8 TO 52V ■ 2.8A OUTPUT PEAK CURRENT (1.4A DC) ■ R DS(ON) 0.73Ω TYP. VALUE @ Tj = 25 °C ■ OPERATING FREQUENCY UP TO 100KHz ■ NON DISSIPATIVE OVERCURRENT PROTECTION ■ PARALLELED OPERATION ■ CROSS CONDUCTION PROTECTION ■ THERMAL SHUTDOWN ■ UNDER VOLTAGE LOCKOUT ■ INTEGRATED FAST FREE WHEELING DIODES TYPICAL APPLICATIONS ■ BIPOLAR STEPPER MOTOR ■ DUAL OR QUAD DC MOTOR

DESCRIPTION

The L6225 is a DMOS Dual Full Bridge designed for motor control applications, realized in MultiPower- BCD technology, which combines isolated DMOS Power Transistors with CMOS and bipolar circuits on the same chip. Available in PowerDIP20 (16+2+2), PowerSO20 and SO20(16+2+2) packages, the L6225 features a non-dissipative protection of the high side PowerMOSFETs and thermal shutdown. BLOCK DIAGRAM D99IN1091A GATE LOGIC OVER CURRENT DETECTION OVER CURRENT DETECTION GATE LOGIC VCP VBOOT EN A IN1A IN2A EN B IN1B IN2B VBOOT 10V VS A VSB OUT1 A OUT2 A OUT1 B OUT2 B SENSE A CHARGE PUMP VOLTAGE REGULATOR THERMAL PROTECTION VBOOT VBOOT 10V 10V BRIDGE A BRIDGE B SENSE B OCD A OCD B ORDERING NUMBERS: L6225N (PowerDIP20) L6225PD (PowerSO20) L6225D (SO20) PowerDIP20 (16+2+2) PowerSO20 SO20 (16+2+2) DMOS DUAL FULL BRIDGE DRIVER

RECOMMENDED OPERATING CONDITIONS Symbol Parameter Test conditions Value Unit VS Supply Voltage VSA = VSB = VS 60 V VOD Differential Voltage between VS A, OUT1A, OUT2A, SENSEA and VS B, OUT1B, OUT2B, SENSEB VSA = VSB = VS = 60V; VSENSEA = VSENSEB = GND 60 V VBOOT Bootstrap Peak Voltage VSA = VSB = VS VS + 10 V VIN,VEN Input and Enable Voltage Range -0.3 to +7 V VSENSEA, VSENSEB Voltage Range at pins SENSEA and SENSE B -1 to +4 V IS(peak) Pulsed Supply Current (for each VS pin), internally limited by the overcurrent protection VSA = VSB = VS; tPULSE < 1ms 3.55 A IS RMS Supply Current (for each VS pin) VSA = VSB = VS 1.4 A Tstg, TOP Storage and Operating Temperature Range -40 to 150 °C Symbol Parameter Test Conditions MIN MAX Unit VS Supply Voltage VSA = VSB = VS 85 2 V VOD Differential Voltage Between VS A, OUT1A, OUT2A, SENSEA and VS B, OUT1B, OUT2B, SENSEB VSA = VSB = VS; VSENSEA = VSENSEB 52 V VSENSEA, VSENSEB Voltage Range at pins SENSEA and SENSE B (pulsed tW < trr) (DC) V V IOUT RMS Output Current 1.4 A Tj Operating Junction T emperature -25 +125 °C fsw Switching Frequency 100 KHz

PIN CONNECTIONS (Top View) (5) The slug is internally connected to pins 1,10,11 and 20 (GND pins). Symbol Description PowerDIP20 SO20 PowerSO20 Unit R th-j-pins MaximumThermal Resistance Junction-Pins 13 15 - °C/W R th-j-case Maximum Thermal Resistance Junction-Case - - 2 °C/W R th-j-amb1 MaximumThermal Resistance Junction-Ambient 1 (1) Mounted on a multi-layer FR4 PCB with a dissipating copper surface on the bottom side of 6cm2 (with a thickness of 35µm). 41 52 - °C/W R th-j-amb1 Maximum Thermal Resistance Junction-Ambient 2 (2) Mounted on a multi-layer FR4 PCB with a dissipating copper surface on the top side of 6cm2 (with a thickness of 35µm). -- 3 6 °C/W R th-j-amb1 MaximumThermal Resistance Junction-Ambient 3 (3) Mounted on a multi-layer FR4 PCB with a dissipating copper surface on the top side of 6cm2 (with a thickness of 35µm), 16 via holes and a ground layer. -- 1 6 °C/W R th-j-amb2 Maximum Thermal Resistance Junction-Ambient 4 (4) Mounted on a multi-layer FR4 PCB without any heat sinking surface on the board. 57 78 63 °C/W PowerDIP20/SO20 PowerSO20 (5) GND OUT1 A SENSE A IN2A IN1A VCP EN A OUT2 A VS A VS B OUT2 B VBOOT IN2B EN B IN1B SENSE B OUT1 B GND10 GND GND D99IN1092A GND OUT1 B SENSE B IN1B IN2B EN B VBOOT OUT2 B VS B GND15 D99IN1093A IN1 A IN2A SENSE A OUT1 A GND GND VS A OUT2 A VCP EN A

(6) Also connected at the output drain of the Overcurrent and Thermal protection MOSFET. Therefore, it has to be driven putting in series a resistor with a value in the range of 2.2kΩ - 180KΩ , recommended 100kΩ PIN DESCRIPTION PACKAGE Name Type FunctionSO20/ PowerDIP20 PowerSO20 PIN # PIN # 1 6 IN1 A Logic Input Bridge A Logic Input 1. 2 7 IN2 A Logic Input Bridge A Logic Input 2. 3 8 SENSE A Power Supply Bridge A Source Pin. This pin must be connected to Power Ground directly or through a sensing power resistor. 4 9 OUT1 A Power Output Bridge A Output 1. GND GND Signal Ground terminals. In PowerDIP and SO packages, these pins are also used for heat dissipation toward the PCB. 7 12 OUT1 B Power Output Bridge B Output 1. 8 13 SENSE B Power Supply Bridge B Source Pin. This pin must be connected to Power Ground directly or through a sensing power resistor. 9 14 IN1 B Logic Input Bridge B Logic Input 1. 10 15 IN2 B Logic Input Bridge B Logic Input 2. 11 16 EN B Logic Input (6) Bridge B Enable. LOW logic level switches OFF all Power MOSFETs of Bridge B. This pin is also connected to the collector of the Overcurrent and Thermal Protection transistor to implement over current protection. If not used, it has to be connected to +5V through a resistor. 12 17 VBOOT Supply Voltage Bootstrap Voltage needed for driving the upper PowerMOSFETs of both Bridge A and Bridge B. 13 18 OUT2 B Power Output Bridge B Output 2. 14 19 VS B Power Supply Bridge B Power Supply Voltage. It must be connected to the supply voltage together with pin VSA. 17 2 VS A Power Supply Bridge A Power Supply Voltage. It must be connected to the supply voltage together with pin VSB. 18 3 OUT2 A Power Output Bridge A Output 2. 19 4 VCP Output Charge Pump Oscillator Output. 20 5 EN A Logic Input (6) Bridge A Enable. LOW logic level switches OFF all Power MOSFETs of Bridge A. This pin is also connected to the collector of the Overcurrent and Thermal Protection transistor to implement over current protection. If not used, it has to be connected to +5V through a resistor.

ELECTRICAL CHARACTERISTICS

(Tamb = 25 °C, Vs = 48V, unless otherwise specified) Symbol Parameter Test Conditions Min Typ Max Unit VSth(ON) Turn-on Threshold 5.8 6.3 6.8 V VSth(OFF) Turn-off Threshold 5 5.5 6 V IS Quiescent Supply Current All Bridges OFF; Tj = -25°C to 125°C (7) 51 0 m A Tj(OFF) Thermal Shutdown Temperature 165 °C Output DMOS Transistors R DS(ON) High-Side + Low-Side Switch ON Resistance Tj = 25 °C 1.47 1.69 Ω Tj =125 °C (7) 2.35 2.70 Ω IDSS Leakage Current EN = Low; OUT = V S 2m A EN = Low; OUT = GND -0.3 mA Source Drain Diodes VSD Forward ON Voltage I SD = 1.4A, EN = LOW 1.15 1.3 V trr Reverse Recovery Time I f = 1.4A 300 ns tfr Forward Recovery Time 200 ns Logic Input VIL Low level logic input voltage -0.3 0.8 V VIH High level logic input voltage 2 7 V IIL Low Level Logic Input Current GND Logic Input Voltage -10 µA IIH High Level Logic Input Current 7V Logic Input Voltage 10 µA Vth(ON) Turn-on Input Threshold 1.8 2.0 V Vth(OFF) Turn-off Input Threshold 0.8 1.3 V Vth(HYS) Input Threshold Hysteresis 0.25 0.5 V Switching Characteristics tD(on)EN Enable to out turn ON delay time (8) ILOAD =1.4A, Resistive Load 500 800 ns tD(on)IN Input to out turn ON delay time ILOAD =1.4A, Resistive Load (dead time included) 1.9 µs tRISE Output rise time(8) ILOAD =1.4A, Resistive Load 40 250 ns tD(off)EN Enable to out turn OFF delay time (8) ILOAD =1.4A, Resistive Load 500 800 1000 ns tD(off)IN Input to out turn OFF delay timeILOAD =1.4A, Resistive Load 500 800 1000 ns tFALL Output Fall Time (8) ILOAD =1.4A, Resistive Load 40 250 ns

(7) Tested at 25°C in a restricted range and guaranteed by characterization. Figure 1. Switching Characteristic Definition

Figure 2. Overcurrent Detection Timing Definition

Figure 8. Overcurrent Protection Waveforms

APPLICATION INFORMATION

A typical application using L6225 is shown in Fig. 11. Typical component values for the application are shown in Table 2. A high quality ceramic capacitor in the range of 100 to 200 nF should be placed between the power pins (VS A and VSB) and ground near the L6225 to improve the high frequency filtering on the power supply and reduce high frequency transients generated by the switching. The capacitors connected from the ENA and ENB inputs to ground set the shut down time for the Brgidge A and Bridge B respectively when an over current is detected (see Overcurrent Protection). The two current sources (SENSE A and SENSEB) should be connected to Power Ground with a trace length as short as possible in the layout. To increase noise immunity, unused logic pins (except ENA and ENB) are best connected to 5V (High Logic Level) or GND (Low Logic Level) (see pin description). It is recommended to keep Power Ground and Signal Ground separated on PCB. Table 2. Component Values for Typical Application Figure 11. Typical Application

1 IN1A

from the die to the power or sense pins of the package must carry current in both of the associated half bridges. DS(ON) of the devices on the same die is well matched. In this configuration the resulting Bridge has the following characteristics. Figure 12. Parallel connection for higher current ration, the resulting bridge has the following characteristics.

e a2 A E PSO20MEC DETAIL A T D 11 0 1120 E1E2 h x 45 DETAIL Alead sluga3 S Gage Plane 0.35 L DETAIL B R DETAIL B (COPLANARITY) GC - C - SEATING PLANE b c NN H BOTTOM VIEW DIM. mm inch A 3.6 0.142 a1 0.1 0.3 0.004 0.012 a2 3.3 0.130 a3 0 0.1 0.000 0.004 b 0.4 0.53 0.016 0.021 c 0.23 0.32 0.009 0.013 D (1) 15.8 16 0.622 0.630 D1 9.4 9.8 0.370 0.386 E 13.9 14.5 0.547 0.570 e 1.27 0.050 e3 11.43 0.450 E1 (1) 10.9 11.1 0.429 0.437 E2 2.9 0.114 E3 5.8 6.2 0.228 0.244 G 0 0.1 0.000 0.004 H 15.5 15.9 0.610 0.626 h 1.1 0.043 L 0.8 1.1 0.031 0.043 N 8˚ (typ.) S 8˚ (max.) T 10 0.394 (1) “D and E1” do not include mold flash or protusions. - Mold flash or protusions shall not exceed 0.15mm (0.006”) - Critical dimensions: “E”, “G” and “a3”. PowerSO20 0056635 JEDEC MO-166 Weight: 1.9gr

DIM. mm inch a1 0.51 0.020 B 0.85 1.40 0.033 0.055 b 0.50 0.020 b1 0.38 0.50 0.015 0.020 D 24.80 0.976 E 8.80 0.346 e 2.54 0.100 e3 22.86 0.900 F 7.10 0.280 I 5.10 0.201 L 3.30 0.130 Z 1.27 0.050 Powerdip 20 OUTLINE AND MECHANICAL DATA

A eB D E L K H A1 C SO20MEC h x 45˚ SO20 DIM. mm inch A 2.35 2.65 0.093 0.104 A1 0.1 0.3 0.004 0.012 B 0.33 0.51 0.013 0.020 C 0.23 0.32 0.009 0.013 D 12.6 13 0.496 0.512 E 7.4 7.6 0.291 0.299 e 1.27 0.050 H 10 10.65 0.394 0.419 h 0.25 0.75 0.010 0.030 L 0.4 1.27 0.016 0.050 K 0˚ (min.)8˚ (max.) OUTLINE AND MECHANICAL DATA

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners © 2003 STMicroelectronics - All rights reserved STMicroelectronics GROUP OF COMPANIES Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States L6225