L6180 STMICROELECTRONICS | Alldatasheet
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OCTAL LINE RECEIVER FOR: - EIA STD RS232D RS423A RS422A - CCIT V.10 V.11 V.28 X.26 NO EXTERNAL COMPONENTS INPUT FAIL SAFING CAPABILITY HIGH CROSSTALK REJECTION L6180 DATA RATE < 100KBIT/S L6181 DATA RATE < 1MBIT/S 50V EOS OUTPUT PROTECTION
DESCRIPTION
L6180/1 is an octal line receiver in a plastic DIP or PLCC designed to meet a wide range of digital communications requirements as outlined in the EIA standards RS232A without additional compo- nents, as well as the low speed applications of RS422A. The receiver meets the CCIT recommendations V.10, V.11, X.26 and V.28 low speed applications (below 100KBS). A low pass filter on the input starts to roll off at a frequency of 100KHz. This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice. October 1993 BLOCK DIAGRAM ORDERING NUMBER: L6180A DIP 28 L6180D PLCC28 L6181A DIP 28 L6181D PLCC28 DIP 28 PLCC 28
Symbol Parameter Value Unit VCC Supply Voltage 7 V VDD Supply Voltage 13.5 V VSS Logic Supply Voltage -13.5 V C RR Common Mode Range ±15 V VID Differential Input Voltage ±25 V Ptot Power Dissipation (PLCC 28) 800 mW Power Dissipation (DIP 28) 1200 mW IOS Output Sink Current 50 mA t Output Short Circuit Time 1 sec Top Operating Free Air Temperature Range 0 to 70 °C Tstg Storage Temperature Range -65 to 150 °C ESD 2KV max ESD 50 µJ Input Transient Protection 50V min EOS 100 µs PIN CONNECTIONS (Top views) DIP28 PLCC28 L6180 - L6181
ELECTRICAL CHARACTERISTICS (VCC =5 V±5%; VCM = -7 to 7V; Tamb = 0 to 70°C; VSS = -9 to 13.5V; VDD = 9 to 13.5V; unless otherwise specified.) Symbol Parameter Test Condition Min. Typ. Max. Unit VIN Input Current (See Fig.1 and note2) VCC = 0 to 5.25V; VSS ,VDD = 0 to 13.5V VIN = - 10 to 10V VIN = - 15 to 15V ±4.25 mA mA R I Input Resistance V IA or VIB = 3 to 15V; (see fig.1) R I= [(VIA or VIN)− VIOC] IIN
37 K Ω
VFS Failsafe Output Voltage I O = -440µA (See Fig.3) 2.7 V VOH High Level Output Voltage V CC = 4.75V; VID = -1V; IOH = -440µA 2.7 V VOL Low Level Output Voltage V CC = 5.25V; VID = -1V; IOL = 2mA 0.4 V VIT2 VIOH Comparator Threshold Voltage (See Fig.4) 1.8 2.2 2.6 V IIH2 High Operating Threshold Voltage VOL = 0.4V; IOL =2 m A ; (See Fig.4) -25 -75 mV IIH1 Low Operating Threshold Voltage VOH = 2.7V; IO = -440µA (See Fig.4) -125 -175 mV VH Input Hysteresis Voltage |V TH2 -V TH1 | 50 150 mV VIOC1 Open Circuit Input Voltage Measured in accordance with V.28 and RS-232D (see note 4 and 7) 0.6 2 V V IOCH Open Circuit Input Voltage Measured in presence of AC Input Signal (see note 7) 3.5 4 4.5 V IOS Open Short Circuit Current V CC = 5.25V; VO =0 ;VID = 1V; (see note 5) 20 100 mA VIBV Input for Balance Test (see Figure 7 and note 11) 0.4 V C I Input Capacitance 100 pF VCC Supply Current V CC = 4.75V to 5.25V; (see note 6) 100 mA Vdd Supply Current V dd = 9 to 3.5V; (see note 6) 30 mA VSS Supplyt Current V SS = -9 to 13.5V; (see note 6) 30 mA IOS Open Short Circuit Current V CC = 5.25V; VO =0 ;VID = 1V; (see note 5) 20 100 mA Tplh Propagation Delay Low to High RL = 390Ω ;C L = 50pF; |VIN = 1V|; (see fig 5 test Circuit Fig. 6) 0 1500 ns Tphl Propagation Delay Low to High RL = 390Ω ;C L = 50pF; |VIN = 1V|; (see fig 5 test Circuit Fig. 6) 0 1500 ns VIOCH Delay VIOCL to VIOCH Switching (see note 7A) 5 ms VIOCL Delay VIOCH to VIOCL Switching (see note 7B) 200 ms Vist |Tplh-T phl|R L = 390Ω ;C L = 50pF; |VIN| = 1V;(see fig. 5; Test Circuit Fig. 6) 0 500 ns TSKEW1 Skew between rec’s in PKg Tp (1) hl/1h - Tp (2) hl/1h R L = 390Ω ;C L = 50pF; |VIN| = 1V;(see fig. 5; Test Circuit Fig. 6) 0 300 ns fA Frequency Accepted (Receiver will Output) VIN = 200mVpp; (see fig. 8 and note 7;
100 KHz
ELECTRICAL CHARACTERISTICS (VCC =5 V±5%; VCM = -7 to 7V; Tamb = 0 to 70°C; VSS = -9 to 13.5V; VDD = 9 to 13.5V; unless otherwise specified.) Symbol Parameter Test Condition Min. Typ. Max. Unit fR Frequency Rejected (No Receiver Output) VIN = 2Vpp; (see fig. 8 and note 7)
5 MHz
Note: 1) The algebric convent ion, where the less positive (more negative) is designed the minimum 2) With the voltage VIA or (VIB) ranging between±15V, while VIB or (VIA) is open or grounded, the resultant input current IIAor (IIB) shall remain within the shaded region shown in the graph in Fig.1. 3) Either Point B’ or Point A’ is grounded in Figure 1 4) VICC measured from grounded to (+) input with (-) input grounded VICC measured from grounded to (+) input with (-) input grounded 5) Not more than one output should be shorted at a time and for less than 1 seond 6) The sum of the product of the maximum supply currents and voltages cannot exceed themaximum power dissipation 7) A: The conditions for the inpit switching from V IOCL to VIOCH mode is: Vidin start bit ”spacing condition”for less than TpVioch(5ms). B: The conditions for the input switching from VIOCH to VIOCL mode is: Vid > WW2 for greater than TpVIOCL (200ms) 8) An example of a frequency response plot meeting the rejection/acce ptance requirements is provided in figure 8. LINE TRANSIENT IMMUNITY (Considering the following cases; powered ON, Powered OFF-LOW im- pedancepower supply and powered OFF-HIGH impedance supply) Symbol Parameter Test Condition Min. Typ. Max. Unit ESD Static tested per MIL-STD-883 (see note 9) 2K V EOS Stress transient pulse both polarities for 100µs (see note 9 and Fig. 2) 50 V Note: 9) All pins are required to withstand this parameters. 10) Input pins are required to withstand fig.2 without any degradation to the circuit. 11) The balance test requirement can be met by use of a current limit circuit which reduces the input bias current I ib(see figure 7) for input voltages below a threshold voltage given by (Iibx 1K) - 400mV. Figure 1:Input Current Voltage Mesurements L6180 - L6181
Figure 3:Output Failsafing Figure 2:EOS Requiremets The output assumes a logic ”1”under the following conditions, (see figure 3)
1 Both inputs open
2 Both inputs shorted
3 Signal Opencircuit
3a Common grounded, signal open circuit
4 Common open, generator powered-on
5 Generatorpowered-down (see note 7)
6 Common open, generator powered-down
6a Signal grounded, common open, generator powered-down
7 Less than 250mVpp differential signal
PLCC28 PACKAGE MECHANICAL DATA DIM. mm inch A 12.32 12.57 0.485 0.495 B 11.43 11.58 0.450 0.456 D 4.2 4.57 0.165 0.180 D1 2.29 3.04 0.090 0.120 D2 0.51 0.020 E 9.91 10.92 0.390 0.430 e 1.27 0.050 e3 7.62 0.300 F 0.46 0.018 F1 0.71 0.028 G 0.101 0.004 M 1.24 0.049 M1 1.143 0.045 L6180 - L6181
DIP28 PACKAGE MECHANICAL DATA DIM. mm inch a1 0.63 0.025 b 0.45 0.018 b1 0.23 0.31 0.009 0.012 b2 1.27 0.050 D 37.34 1.470 E 15.2 16.68 0.598 0.657 e 2.54 0.100 e3 33.02 1.300 F 14.1 0.555 I 4.445 0.175 L 3.3 0.130 L6180 - L6181
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications men- tioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without ex- press written approval of SGS-THOMSON Microelectronics. 1995 SGS-THOMSON Microelectronics - All Rights Reserved SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands - Singapore - L6180 - L6181