L5NK65Z

STL5NK65Z STMICROELECTRONICS | Alldatasheet

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Technical content

N-CHANNEL 650V - 1.5Ω - 4.2A PowerFLAT™ Zener-Protected SuperMESH™Power MOSFET ■ TYPICAL R DS (on) = 1.5 Ω ■ EXTREMELY HIGH dv/dt CAPABILITY ■ IMPROVED ESD CAPABILITY ■ 100% AVALANCHE RATED ■ GATE CHARGE MINIMIZED ■ VERY LOW INTRINSIC CAPACITANCES ■ VERY GOOD MANUFACTURING REPEATIBILITY

DESCRIPTION

The SuperMESH™ series is obtained through an extreme optimization of ST’s well established strip- based PowerMESH™ layout. In addition to pushing on-resistance significantly down, special care is tak- en to ensure a very good dv/dt capability for the most demanding applications. Such series comple- ments ST full range of high voltage MOSFETs in- cluding revolutionary MDmesh™ products.

APPLICATIONS

■ LIGHTING ■ IDEAL FOR OFF-LINE POWER SUPPLIES, ADAPTORS AND PFC

ORDERING INFORMATION

TYPE V DSS R DS(on) ID (1) Pw (1) STLNK65Z 650 V < 1.8 Ω 4.2 A 75 W SALES TYPE MARKING PACKAGE PACKAGING STL5NK65Z L5NK65Z PowerFLAT™ (5x5) TAPE & REEL PowerFLAT ™(5x5) (Chip Scale Package) INTERNAL SCHEMATIC DIAGRAM

Note: 1. The value is rated according to Rthj-F. 2. When Mounted on FR-4 Board of 1inch2, 2 oz Cu 3. Pulse width limited by safe operating area 4. ISD <4.2A, di/dt<300A/µs, VDD <V (BR)DSS , TJ<TJMAX AVALANCHE CHARACTERISTICS GATE-SOURCE ZENER DIODE PROTECTION FEATURES OF GATE-TO-SOURCE ZENER DIODES The built-in back-to-back Zener diodes have specifically been designed to enhance not only the device’s ESD capability, but also to make them safely absorb possible voltage transients that may occasionally be applied from gate to souce. In this respect the Zener voltage is appropriate to achieve an efficient and cost- effective intervention to protect the device’s integrity. These integrated Zener diodes thus avoid the usage of external components. Symbol Parameter Value Unit VDS Drain-source Voltage (VGS = 0) 650 V VDGR Drain-gate Voltage (RGS = 20 kΩ ) 650 V VGS Gate- source Voltage ± 30 V ID (2) Drain Current (continuous) at TC = 25°C (Steady State) Drain Current (continuous) at TC = 100°C 0.76 0.48 A A IDM (2) Drain Current (pulsed) 3 A PTOT (2) Total Dissipation at TC = 25°C (Steady State) 2.5 W PTOT (1) Total Dissipation at TC = 25°C (Steady State) 75 W Derating Factor (2) 0.02 W/°C dv/dt (4) Peak Diode Recovery voltage slope 4.5 V/ns Tstg Storage Temperature –55 to 150 °C Tj Max. Operating Junction Temperature Symbol Parameter Max. Unit Rthj-F Thermal Resistance Junction-Foot (Drain) 1.67 °C/W Rthj-amb (2) Thermal Resistance Junction-ambient 50 °C/W Symbol Parameter Max Value Unit IAR Avalanche Current, Repetitive or Not-Repetitive (pulse width limited by Tj max) 4.2 A EAS Single Pulse Avalanche Energy (starting Tj = 25 °C, ID = IAR , VDD = 50 V) 190 mJ Symbol Parameter Test Conditions Min. Typ. Max. Unit BV GSO Gate-Source Breakdown Voltage Igs=± 1mA (Open Drain) 30 V

ELECTRICAL CHARACTERISTICS (TCASE =25°C UNLESS OTHERWISE SPECIFIED) ON/OFF DYNAMIC SWITCHING SOURCE DRAIN DIODE Note: 1.Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %. 2. Pulse width limited by safe operating area. 3. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS . Symbol Parameter Test Conditions Min. Typ. Max. Unit V(BR)DSS Drain-source Breakdown Voltage ID = 1 mA, VGS = 0 650 V IDSS Zero Gate Voltage Drain Current (VGS = 0) VDS = Max Rating VDS = Max Rating, TC = 125 °C µA µA IGSS Gate-body Leakage Current (VDS = 0) VGS = ± 20V ±10 µA VGS(th) Gate Threshold Voltage VDS = VGS , ID = 50µA 3 3.75 4.5 V R DS(on) Static Drain-source On Resistance VGS = 10V, ID = 2.1 A 1.5 1.8 Ω Symbol Parameter Test Conditions Min. Typ. Max. Unit gfs (1) Forward Transconductance V DS = 10 V, ID = 2.1 A 5 S C iss C oss C rss Input Capacitance Output Capacitance Reverse Transfer Capacitance V DS = 25V, f = 1 MHz, VGS = 0 680 pF pF pF C oss eq. (3) Equivalent Output Capacitance VGS = 0V, VDS = 0V to 480 V 98 pF R G Gate Input Resistance f=1 MHz Gate DC Bias = 0 Test Signal Level = 20mV Open Drain 4 Ω Symbol Parameter Test Conditions Min. Typ. Max. Unit td(on) tf td(off) tf Turn-on Delay Time Fall Time Turn-off Delay Time Fall Time VDD = 325 V, ID = 2.1 A R G = 4.7Ω VGS = 10 V (Resistive Load see, Figure 3) 140 ns ns ns ns Q g Q gs Q gd Total Gate Charge Gate-Source Charge Gate-Drain Charge VDD = 520V, ID = 4.2 A, VGS = 10V 4.4 13.7 35 nC nC nC Symbol Parameter Test Conditions Min. Typ. Max. Unit ISD ISDM (2) Source-drain Current Source-drain Current (pulsed) 0.76 A A VSD (1) Forward On Voltage ISD = 0.76 A, VGS = 0 1.6 V trr Q rr IRRM Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD = 4.2 A, di/dt = 100A/µs VDD = 100V, Tj = 150°C (see test circuit, Figure 5) 375 1.76 ns µC A

Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times Fig. 4: Gate Charge test Circuit Fig. 2: Unclamped Inductive WaveformFig. 1: Unclamped Inductive Load Test Circuit Fig. 3: Switching Times Test Circuit For Resistive Load

DIM. mm. inch A 0.90 1.00 0.035 0.039 A1 0.02 0.05 0.001 0.002 D 5.00 0.197 E 5.00 0.197 e 1.27 0.050 PowerFLAT ™ (5x5) MECHANICAL DATA

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