L5985_08 STMICROELECTRONICS | Alldatasheet
Document overview
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- PDF pages: 37
Technical content
Datasheet sections
- 1 Pin settings
- 1.1 Pin connection
- 1.2 Pin description
- 2 Maximum ratings
- 2.1 Absolute maximum ratings
- 2.2 Thermal data
- 3 Electrical characteristics
- 4 Functional description
- 4.1 Oscillator and synchronization
- 4.2 Soft-start
- 4.3 Error amplifier and compensation
- 4.4 Over-current protection
- 4.5 Inhibit function
- 4.6 Hysteretic thermal shutdown
- 5 Application information
- 5.1 Input capacitor selection
- 5.2 Inductor selection
- 5.3 Output capacitor selection
- 5.4 Compensation network
- 5.4.1 Type III compensation network
- 5.4.2 Type II compensation network
- 5.5 Thermal considerations
- 5.6 Layout considerations
- 5.7 Application circuit
- 6 Package mechanical data
- 7 Order codes
- 8 Revision history
Features
■ 2 A DC output current ■ 2.9 V to 18 V input voltage ■ Output voltage adjustable from 0.6 V ■ 250 kHz switching frequency, programmable up to 1 MHz ■ Internal soft-start and Inhibit ■ Low dropout operation: 100 % duty cycle ■ Voltage feed-forward ■ Zero load current operation ■ Over current and thermal protection ■ VFQFPN8 3 mm x 3 mm package
Applications
■ Consumer: STB, DVD, DVD recorder, car audio, LCD TV and monitors ■ Industrial: Chargers, PLD, PLA, FPGA ■ Networking: XDSL, modems, DC-DC modules ■ Computer: Optical storage, hard disk drive, printers, audio/graphic cards ■ LED driving
Description
The L5985 is a step down switching regulator with
2.5 A (min) current limited embedded power
MOSFET, so it is able to deliver up to 2 A DC current to the load depending on the application condition. The input voltage can range from 2.9 V to 18 V, while the output voltage can be set starting from
0.6 V to V
IN. Having a minimum input voltage of 2.9 V, the device is suitable for 3.3 V bus. Requiring a minimum set of external components, the device includes an internal 250 kHz switching frequency oscillator that can be externally adjusted up to 1 MHz. The VFQFPN8 package with exposed pad allows reducing the RthJA down to approximately 60 °C/W. VFQFPN8 3 mm x 3 mm Figure 1. Application circuit
1 Pin settings
1.1 Pin connection
Figure 2. Pin connection (top view)
1.2 Pin description
Table 1. Pin description
1 OUT Regulator output
2 SYNCH
turn on have a phase shift of half a period. 1.9 V the device is OFF and with INH lower than 0.6 V the device is ON.
4 COMP Error amplifier output to be used for loop frequency compensation
external resistor divider is required from Vout to FB pin. works at its free-running frequency of 250 kHz.
7 GND Ground
2 Maximum ratings
2.1 Absolute maximum ratings
2.2 Thermal data
Table 2. Absolute maximum ratings Table 3. Thermal data
- Package mounted on demonstration board.
3 Electrical characteristics
TJ = 25 °C, VCC = 12 V, unless otherwise specified. Table 4. Electrical characteristics
- Specification refered to T J from -40 to +125 °C. Specification in the -40 to +125 °C temperature range are
assured by design, characterization and statistical correlation.
4 Functional description
synchronization signal. Its switching frequency can be adjusted by a external resistor. The voltage and frequency feed forward are implemented. z The soft-start circuitry to limit inrush current during the start up phase. z The high-side driver for embedded p-channel power MOSFET switch. z The peak current limit sensing block, to handle over load and short circuit conditions. z A voltage monitor circuitry (UVLO) that checks the input and internal voltages. z The thermal shutdown block, to prevent thermal run away. Figure 3. Block diagram
4.1 Oscillator and synchronization
shown in Figure 6 by external resistor connected to ground. according to the input voltage change (see Figure 5.a). through the input capacitor [see L5988D data sheet]. Figure 4. Oscillator circuit block diagram (Figure 5.c). This changing has to be taken into account when the loop stability is studied. sawtooth, due to the external synchronization.
4.2 Soft-start
avoids inrush current surge and makes the output voltage increases monothonically. soft-start time and then the output voltage slew rate depend on the switching frequency. Figure 7. Soft-start scheme
4.3 Error amplifier and compensation
mode operational amplifier so with high DC gain and low output impedance. compensation network selection). Table 5. Uncompensated error amplifier characteristics
L5985 Functional description
4.4 Over-current protection
The L5985 implements the over current protection sensing current flowing through the power MOSFET. Due to the noise created by the switching activity of the power MOSFET, the current sensing is disabled during the initial phase of the conduction time. This avoids an erroneous detection of a fault condition. This interval is generally known as “masking time” or “blanking time”. The masking time is about 200 ns. When the over current is detected, two different behaviors are possible depending on the operating condition. 1. Output voltage in regulation. When the over current is sensed, the power MOSFET is switched off and the internal reference (V REF), that biases the non-inverting input of the error amplifier, is set to zero and kept in this condition for a soft-start time (TSS, 2048 clock cycles). After this time, a new soft-start phase takes place and the internal reference begins ramping (see Figure 8.a). 2. Soft-start phase. If the over current limit is reached the power MOSFET is turned off implementing the pulse by pulse over current protection. During the soft-start phase, under over current condition, the device can skip pulses in order to keep the output current constant and equal to the current limit. If at the end of the "masking time" the current is higher than the over current threshold, the power MOSFET is turned off and it will skip one pulse. If, at the next switching on at the end of the "masking time" the current is still higher than the threshold, the device will skip two pulses. This mechanism is repeated and the device can skip up to seven pulses. While, if at the end of the "masking time" the current is lower than the over current threshold, the number of skipped cycles is decreased of one unit. At the end of soft-start phase the output voltage is in regulation and if the over current persists the behavior explained above takes place. (see Figure 8.b) So the over current protection can be summarized as an “hiccup” intervention when the output is in regulation and a constant current during the soft-start phase. If the output is shorted to ground when the output voltage is on regulation, the over current is triggered and the device starts cycling with a period of 2048 clock cycles between “hiccup” (power MOSFET off and no current to the load) and “constant current” with very short on- time and with reduced switching frequency (up to one eighth of normal switching frequency). See figure 32 for short circuit behavior.
Figure 8. Over current protection strategy
4.5 Inhibit function
ensures that the voltage at the pin reaches the inhibit threshold and the device is disabled. The pin is also VCC compatible.
4.6 Hysteretic thermal shutdown
area, so ensuring an accurate and fast temperature detection.
5 Application information
5.1 Input capacitor selection
affecting the overall system efficiency. current and an ESR value compliant with the expected efficiency. Where Io is the maximum DC output current, D is the duty cycle, η is the efficiency. Considering η = 1, this function has a maximum at D = 0.5 and it is equal to Io/2. Table 6. Input capacitors
5.2 Inductor selection
minimum inductance value in order to have the expected current ripple has to be selected. The rule to fix the current ripple value is to have a ripple at 20 %-40 % of the output current. where FSW is the switching frequency 1/(TON + TOFF). inductance value to have ΔIL = 30 % of IO is about 18 μH. output current that can be delivered, without reaching the current limit. In the table below some inductor part numbers are listed. Table 7. Inductors
5.3 Output capacitor selection
the drop dominates and the voltage ripple is 25 mV. have to be chosen in order to sustain the load transient. In the table below some capacitor series are listed. Table 7. Inductors (continued)
5.4 Compensation network
will be considered as ideal, that is, its bandwidth is much larger than the system one. Table 8. Output capacitors
Figure 9. Error amplifier, PWM modulator and LC output filter
5.4.1 Type III compensation network
Figure 10. Type III compensation network and the open loop gain (GLOOP(f) = GPW0 · GLC(f) · GTYPEIII(f)) are drawn.
Figure 11. Open loop gain: module bode diagram
- Choose a value for R 1, usually between 1 k and 5 k.
- Choose a gain (R 4/R1) in order to have the required bandwidth (BW), that means:
where K is the feed forward constant and 1/K is equals to 9.
- Calculate C 4 by placing the zero at 50 % of the output filter double pole frequency (fLC):
- Calculate C 5 by placing the second pole at four times the system bandwidth (BW):
- Set also the first pole at four times the system bandwidth and also the second zero at
The suggested maximum system bandwidth is equals to the switching frequency divided by 3.5 (FSW/3.5), anyway lower than 100 kHz if the FSW is set higher than 500 kHz. For example with VOUT = 3.3 V, VIN = 12 V, IO = 2 A, L = 15 μH, COUT = 22 μF , ESR < 1 mΩ, the type III compensation network is: In Figure 12 is shown the module and phase of the open loop gain. The bandwidth is about 75 kHz and the phase margin is 47°. R1 4.99kΩ= R2 1.1kΩ= R3 150Ω= R4 4.99kΩ= C3 3.3nF= C4 10nF= C5 100pF=,, , ,, ,
Figure 12. Open loop gain bode di agram with ceramic output capacitor
5.4.2 Type II com pensation network
In Figure 13 the type II network is shown.
Where fESR is the ESR zero: Equation 23 and Vs is the saw-tooth amplitude. The voltage feed forward keeps the ratio Vs/Vin constant. 3. Calculate C 4 by placing the zero one decade below the output filter double pole: Equation 24 4. Then calculate C 3 in order to place the second pole at four times the system bandwidth (BW): Equation 25 For example with VOUT = 3.3 V, VIN = 12 V, IO = 2 A, L = 15 μH, COUT = 330 μF, ESR = 50 mΩ, the type II compensation network is: Equation 26 In Figure 15 is shown the module and phase of the open loop gain. The bandwidth is about 37 kHz and the phase margin is 46°. fESR fLC 2 BW fESR VIN fESR R1 1.1kΩ= R2 249Ω= R4 10kΩ= C4 68nF= C5 68pF=,,,,
Figure 15. Open loop gain bode diagram wi th electrolytic/tantalum output capacitor
5.5 Thermal considerations
The thermal design is important to prevent the thermal shutdown of device if junction temperature goes above 150 °C. The three different sources of losses within the device are: a) conduction losses due to the not negligible R DS(on) of the power switch; these are equal to: Equation 27 Where D is the duty cycle of the application and the maximum RDS(on) is 220 mΩ. Note that the duty cycle is theoretically given by the ratio between VOUT an VIN, but actually it is quite higher to compensate the losses of the regulator. So the conduction losses increases compared with the ideal case. b) switching losses due to power MOSFET turn ON and OFF; these can be calculated as: Equation 28 Where T RISE and TFALL are the overlap times of the voltage across the power switch (VDS) and the current flowing into it during turn ON and turn OFF phases, as shown in Figure 16. TSW is the equivalent switching time. For this device the typical value for the equivalent switching time is 50 ns. c) Quiescent current losses, calculated as: Equation 29 where IQ is the quiescent current. (IQ = 2.4 mA) The junction temperature TJ can be calculated as: Equation 30 Where TA is the ambient temperature and PTOT is the sum of the power losses just seen. RthJA is the equivalent thermal resistance juction to ambient of the device; it can be calculated as the parallel of many paths of heat conduction from the junction to the ambient. For this device the path through the exposed pad is the one conducting the largest amount of heat. The Rth JA measured on the application demonstration board described in the following paragraph is about 60 °/W. PON RDSON IOUT() 2 D⋅⋅= PSW VIN IOUT TRISE TFALL+() PQ VIN IQ⋅= TJ TA Rth JA PTOT⋅+=
Figure 16. Switching losses
5.6 Layout considerations
added as close as possible to the input voltage pin of the device. of the converter allowing high power conversion. In Figure 17 a layout example is shown.
Figure 17. Layout example
5.7 Application circuit
In Figure 18 the demonstration board application circuit is shown. Figure 18. Demonstration board application circuit Table 9. Component list
6 Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com
Figure 33. Package dimensions Table 9. VFQFPN8 (3x3x1.08 mm) mechanical data
7 Order codes
Table 10. Order codes
8 Revision history
Table 11. Document revision history