L5980 STMICROELECTRONICS | Alldatasheet
Document overview
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- PDF pages: 37
Technical content
Datasheet sections
- 1 Pin settings
- 1.1 Pin connection
- 1.2 Pin description
- 2 Maximum ratings
- 3 Electrical characteristics
- 4 Functional description
- 4.1 Oscillator and synchronization
- 4.2 Soft-start
- 4.3 Error amplifier and compensation
- 4.4 Over-current protection
- 4.5 Inhibit function
- 4.6 Hysteretic thermal shutdown
- 5 Application informations
- 5.1 Input capacitor selection
- 5.2 Inductor selection
- 5.3 Output capacitor selection
- 5.4 Compensation network
- 5.4.1 Type III compensation network
- 5.4.2 Type II compensation network
- 5.5 Thermal considerations
- 5.6 Layout considerations
- 5.7 Application circuit
- 6 Package mechanical data
- 7 Order codes
- 8 Revision history
Features
0.7A DC output current 2.9V to 18V input voltage Output voltage adjustable from 0.6V 250kHz switching frequency, programmable up to 1MHz Internal soft-start and inhibit Low dropout operation: 100% duty cycle Voltage feed-forward Zero load current operation Over current and thermal protection VQFN3x3-8L package
Applications
Consumer: STB, DVD, DVD recorder, car audio, LCD TV and monitors Industrial: Chargers, car battery, PLD, PLA, FPGA Networking: XDSL, modems, DC-DC modules Computer: Optical storage, hard disk drive, printers, audio/graphic cards Figure 1. Application circuit
Description
The L5980 is step down switching regulator with 1A current limited embedded power MOSFET, so it is able to deliver in excess of 0.7A DC current to the load depending on the application condition. The input voltage can range from 2.9V to 18V, while the output voltage can be set starting from 0.6V to V IN. Having a minimum input voltage of 2.9V, the device is suitable also for 3.3V bus. Requiring a minimum set of external components, the device includes an internal 250kHz switching frequency oscillator that can be externally adjusted up to 1MHz. The QFN package with exposed pad allows reducing the R thJA down to approximately 60°C/W. VFQFPN8 3x3
1 Pin settings
1.1 Pin connection
Figure 2. Pin connection (top view)
1.2 Pin description
Table 1. Pin description
1 OUT Regulator output
2 SYNCH
powers turn on have a phase shift of half a period. 1.9V the device is OFF and with INH lower than 0.6V the device is ON.
4 COMP Error Amplifier output to be used for loop frequency compensation
external resistor divider is required from Vout to FB pin. works at its free-running frequency of 250kHz.
7 GND Ground
2 Maximum ratings
Table 2. Absolute maximum ratings
3 Electrical characteristics
TJ=25°C, VCC=12V, unless otherwise specified. Table 3. Electrical characteristics
- Specification refered to T J from -40 to +125°C. Specification in the -40 to +125°C temperature range are
assured by design, characterization and statistical correlation.
4 Functional description
resistor. The voltage and frequency feed forward are implemented. z The soft start circuitry to limit inrush current during the start up phase. z The High-side driver for embedded p-channel power MOSFET switch. z The peak current limit sensing block, to handle over load and short circuit conditions. z A voltage monitor circuitry (UVLO) that checks the input and internal voltages. z A thermal shutdown block, to prevent thermal run away. Figure 3. Block diagram
4.1 Oscillator and synchronization
shown in Figure 6 by external resistor connected to ground. sawtooth according to the input voltage change (see Figure 5.a). through the input capacitor [see L5988D Data sheet]. Figure 4. Oscillator circuit block diagram (Figure 5.c). This changing has to be taken into account when the loop stability is studied. sawtooth, due to the external synchronization.
4.2 Soft-start
avoids inrush current surge and makes the output voltage increases monothonically. soft start time and then the output voltage slew rate depend on the switching frequency. Figure 7. Soft start scheme.
4.3 Error amplifier and compensation
Mode Operational Amplifier so with high DC gain and low output impedance. compensation network selection). Table 4. Uncompensated Error Amplifier characteristics
4.4 Over-current protection
time” or “blanking time”. The masking time is about 200ns.
- Output voltage in regulation. When the over current is sensed, the power MOSFET
reference begins ramping (see Figure 8.a).
- Soft start phase. If the over current limit is reached the power MOSFET is turned off
Figure 30. for short circuit behavior.
Figure 8. Over current protection strategy
4.5 Inhibit function
ensures that the voltage at the pin reaches the inhibit threshold and the device is disabled. The pin is also VCC compatible.
4.6 Hysteretic thermal shutdown
area, so ensuring an accurate and fast temperature detection.
5 Application informations
5.1 Input capacitor selection
affecting the overall system efficiency. current and an ESR value compliant with the expected efficiency. function has a maximum at D=0.5 and, considering η=1, it is equal to Io/2. Table 5. Input MLCC capacitors
5.2 Inductor selection
minimum inductance value in order to have the expected current ripple has to be selected. The rule to fix the current ripple value is to have a ripple at 20%-40% of the output current. where FSW is the switching frequency, 1/(TON + TOFF). value to have ∆IL=30% of IO is about 45µH. output current that can be delivered, without reaching the current limit. In the table below some inductor part numbers are listed. Table 6. Inductors
5.3 Output capacitor selection
across it. This ripple is due to the capacitive component and the resistive component (ESR). the application requirements. value. So 100uF with ESR=40mΩ is compliant with the requested output voltage ripple. have to be chosen in order to sustain the load transient . In the table below some capacitor series are listed. Table 6. Inductors (continued) Table 7. Output capacitors
5.4 Compensation network
will be considered as ideal, that is, its bandwidth is much larger than the system one. and how to keep it constant in spite of the external synchronization). Table 7. Output capacitors (continued)
Figure 9. The Error amplifier, the PWM modulator and the LC output filter .
5.4.1 Type III compensation network
Figure 10. Type III compensation network and the open loop gain (GLOOP(f)=GPW0 · GLC(f) · GTYPEIII(f)) are drawn.
Figure 11. Open loop gain: module Bode diagram
- Choose a value for R 1, usually between 1kΩ and 5kΩ.
- Choose a gain (R 4/R1) in order to have the required bandwidth (BW), that means:
where K is the feed forward constant and 1/K is equals to 9.
- Calculate C 4 by placing the zero at 50% of the output filter double pole frequency (fLC):
- Calculate C 5 by placing the second pole at four times the system bandwidth (BW):
- Set also the first pole at four times the system bandwidth and also the second zero at
Application informations L5980 Equation 21 The suggested maximum system bandwidth is equals to the switching frequency divided by 3.5 (FSW/3.5), anyway lower than 100kHz if the FSW is set higher than 500kHz. For example with VOUT=3.3V, VIN=12V, IO=0.7A, L=47µH, COUT=22µF , the type III compensation network is: In Figure 12 is shown the module and phase of the open loop gain. The bandwidth is about 57kHz and the phase margin is 45°. 4B W⋅ fLC R1 4.99kΩ= R2 1.1kΩ= R3 120Ω= R4 5.6kΩ= C3 6.8nF= C4 10nF= C5 100pF=,, , ,, ,
Figure 12. Open loop gain bode di agram with ceramic output capacitor
5.4.2 Type II com pensation network
In Figure 13 the type II network is shown. Figure 13. Type II compensation network and the open loop gain (GLOOP(f)=GPW0 · GLC(f) · GTYPEII(f)) are drawn. Figure 14. Open loop gain: module bode diagram
Application informations L5980 The guidelines for positioning the poles and the zeroes and for calculating the component values can be summarized as follow: 1. Choose a value for R 1, usually between 1k and 5k, in order to have values of C4 and C5 not comparable with parasitic capacitance of the board. 2. Choose a gain (R 4/R1) in order to have the required bandwidth (BW), that means: Equation 22 Where fESR is the ESR zero: Equation 23 and Vs is the saw-tooth amplitude. The voltage feed forward keeps the ratio Vs/Vin constant. 3. Calculate C 4 by placing the zero one decade below the output filter double pole: Equation 24 4. Then calculate C 3 in order to place the second pole at four times the system bandwidth (BW): Equation 25 For example with VOUT=1.2V, VIN=12V, IO=0.7A, L=22µH, COUT=220µF , ESR=50mΩ, the type II compensation network is: In Figure 15 is shown the module and phase of the open loop gain. The bandwidth is about 35kHz and the phase margin is 49°. fESR fLC 2 BW fESR VIN fESR R1 1.1kΩ= R2 249Ω= R4 12kΩ= C4 47nF= C5 68pF=,,,,
Figure 15. Open loop gain bode diagram wi th electrolytic/tantalum output capacitor
Application informations L5980
5.5 Thermal considerations
The thermal design is important to prevent the thermal shutdown of device if junction temperature goes above 150°C. The three different sources of losses within the device are: a) conduction losses due to the not negligible R DSON of the power switch; these are equal to: Equation 26 Where D is the duty cycle of the application and the maximum RDSON is 300mΩ. Note that the duty cycle is theoretically given by the ratio between VOUT an VIN, but actually it is quite higher to compensate the losses of the regulator. So the conduction losses increases compared with the ideal case. b) switching losses due to power MOSFET turn ON and OFF; these can be calculated as: Equation 27 Where TRISE and TFALL are the overlap times of the voltage across the power switch (VDS) and the current flowing into it during turn ON and turn OFF phases, as shown in Figure 16. TSW is the equivalent switching time. For this device the typical value for the equivalent switching time is 50ns. c) Quiescent current losses, calculated as: Equation 28 where IQ is the quiescent current (IQ=20uA). The junction temperature TJ can be calculated as: Equation 29 Where TA is the ambient temperature and PTOT is the sum of the power losses just seen. RthJA is the equivalent thermal resistance junction to ambient of the device; it can be calculated as the parallel of many paths of heat conduction from the junction to the ambient. For this device the path through the exposed pad is the one conducting the largest amount PON RDSON IOUT() 2 D⋅⋅= PSW VIN IOUT TRISE TFALL+() PQ VIN IQ⋅= TJ TA Rth JA PTOT⋅+=
Figure 16. Switching losses
5.6 Layout considerations
the input voltage pin of the device. of the converter allowing high power conversion. In Figure 17 a layout example is shown.
Figure 17. Layout example
5.7 Application circuit
In Figure 18 the demo board application circuit is shown. Figure 18. Demo board application circuit Table 8. Component list
Package mechanical data L5980
6 Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect. The category of the second level interconnect is marked on the package and on the inner box label, in compliance with the JEDEC Standard JESD97. The maximum ratings related to soldering condition are also marked on the inner box label. ECOPACK® is an ST trademark. ECOPACK specifications are available at: www.st.com
Figure 33. Package dimensions Table 9. VFQFPN8 (3x3x1.08mm) mechanical data
7 Order codes
Table 10. Order codes
8 Revision history
Table 11. Document revision history