L5963_V01 STM | Alldatasheet
Document overview
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Technical content
Datasheet sections
- 1 Overview
- 2 Block diagram
- 3 Application diagrams
- 4 Pins description
- 5 Electrical specifications
- 5.1 Absolute maximum ratings
- 5.2 Thermal data
- 5.3 Electrical characteristics
- 6 Functional Description
- 6.1 Operative modes
- 6.2 Blocks functional description
- 6.2.1 Unregulated supply input voltage (VINLDO)
- 6.2.2 Low voltage warning monitor (related pins: VDIN, VDOUT, VDDLY)
- 6.2.3 Power-good reset (related pins: LDOOK, LDOOKDLY)
- 6.2.5 Over voltage shutdown
- 6.2.6 Power ground (PGND1 and PGND2)
- 6.2.7 Signal ground (SGND)
- 6.2.8 PWM signal ground (SWGND)
- 6.2.9 TAB
- 6.2.10 Linear regulator
- 6.2.11 High-side driver (HSD)
- 6.2.12 Switching regulators
- 7 Application information
- 7.1 Output inductor (Lo)
- 7.2 Output capacitors (COUT)
- 7.3 Input capacitors (C
- 7.4 Bootstrap capacitor (CBOOT)
This is information on a product in full production. L5963 Automotive dual monolithic switching regulator with LDO and HSD Datasheet - production data Featuress AEC-Q100 qualified Two step-down synchronous switching voltage regulators with internal power switches: – Wide input voltage range (from 3.5 V to 26 V) – Internal high-side/ low-side NDMOS – 1 V minimum output – 3.0 A load current – 250 kHz free-run frequency – 250 kHz < f < 2 MHz synchronization range – Integrated soft-start – Independent hardware enable pins – Independent power supply – 180° PWM output phase shift – Programmable switching frequency divider by 1, 2, 4 or 8 between the two DC/DC regulators – Power good function One standby / linear regulator – Output voltage programmable with external resistor divider – 250 mA maximum current capability – Backup function – Power good function One high side driver – 0.5 V max drop @ 0.5 A – Protected against short to ground and battery, loss of ground and battery, unsupplied short to battery Programmable under voltage battery detector – Under voltage threshold adjustable through dedicated pin (VDIN) Load dump protection Independent thermal protection on all regulators Independent current limit on all regulators Extremely low quiescent current in standby conditions Power good / adjustable voltage detector outputs to realize customized power up/down sequences
Description
L5963 is a dual step-down switching regulator with internal power switches, high side driver and a low drop-out linear regulator that can operate as standby regulator or normal LDO. All the regulators can be connected directly to the vehicle battery. In addition to an adjustable voltage detector, voltage supervisors are available. The two DC-DC converters can work in free-run condition or synchronize themselves to an external clock. DC/DCs' PWM outputs have a 180° phase shift. The high operating frequency allowed by the synchronization input helps to reduce AM and FM interferences and grants the use of small and low cost inductors and capacitors. This IC finds application in the automotive segment, where load dump protection and wide input voltage range are mandatory. A slug-up package option is available for applications which require heatsink use. In standby condition the device guarantees extremely low quiescent current (25 μA typical @ -40 °C < T < 85 °C) '!0'03 '!0'03 PowerSSO-36 (exposed pad) PowerSSO-36 (slug-up) *$3*36 VQFPN-48 Table 1. Device summary
1 Overview
The L5963 integrates two switching mode synchronous step down converters, a linearly regulated power supply, a protected high side driver and voltage detectors. To guarantee a robust operation, all the outputs have independent thermal protection and current limitation. The two switching mode synchronous step-down converters employ voltage mode control and feed forward functions to provide good load regulation and line regulation. Each converter has its own enable. The users can adjust the output voltage of the two converters by an external resistor divider. If the converters need to work with a frequency different from the free running frequency, in order to consider EMC performance in system level, they can be synchronized to an external clock by applying it on the SYNCIN pin. The frequency should be higher than half of the free running frequency. If there are more than one L5963 in the system they can work in Master-Slave configuration, to make sure all L5963 have the same operating frequency of the Master device. This Master-Slave function is implemented by a dedicated pin SYNCOUT which always gives the operating frequency of DC/DC1. A dedicated voltage detector is integrated in the first switching converter to monitor DC/DC1 output. When the output voltage of DC/DC1 goes above the threshold, SW1OK is released and goes back to high with configurable delay set by a capacitor on the SW1OKDLY pin. The linear regulator can work as standby regulator with low Iq or as a non-standby regulator. Connecting its enable ENLDO to its supply VINLDO the regulator works as a standby regulator, while connecting ENLDO to a voltage lower than 5 V the regulator works as non- standby regulator, with higher load capability but also higher quiescent current. In standby state, i.e. only the linear regulator is powered and works as a standby regulator, with a load below 100 μA the device has a quiescent current of just 25 μA. The small drop-out voltage of the linear regulator allows its use with low operating supply voltage. In many cases, the linear regulator has to provide voltages to devices which need the reset function, like a MCU: this is provided by the LDOOK output, that is pulled low when VOUTLDO goes below a threshold. Once VOUTLDO returns above that threshold, with a specified hysteresis, LDOOK goes back to high with a configurable delay set by a capacitor on pin LDOOKDLY. The high side driver is enabled by a dedicated pin and has a very low drop-out voltage. Protection circuits, like independent thermal protection, OCP , OVP and some special protections (loss of GND, SPU, short to supply and so on), are implemented to make it very robust. L5963 also embeds a voltage monitor (VDOUT), adjustable by means of an external resistor divider, that can be used to sense the battery or other voltages in the system. Sensing voltage is fed to pin VDIN. For instance, VDOUT might be used to monitor the output of DC/DC2, realizing in this way the Power Good function for that block. VDOUT is pulled low when voltage on VDIN goes below the specified threshold. Once VDIN returns above that threshold, with a specified hysteresis, VDOUT goes back to high with a configurable delay set by a capacitor on pin LDOOKDLY Two different packages are available. The PowerSSO-36 slug-down allows to dissipate the heat on the board and reduce the application size. The slug has to be connected to the ground plane. This is the package suggested for standard applications. When this is not enough, because the L5963 is used as pre-regulator for high consuming applications and both the 2 DC-DC are working at high currents, the PSSO36 slug-up allows the use of a heat-sink to make easier power dissipation.
2 Block diagram
Figure 1. Block diagram
3 Application diagrams
Figure 2. Example of a typical application diagram
Figure 3. Example of usage of two regulators in the same application
4 Pins description
Figure 4. PowerSSO-36 pinout configuration Table 2. PowerSSO-36 pins description
2 PGND1 Ground Switching regulator 1 power ground
4 BS1 Supply Switching regulator 1 boosted supply
5 PWM1 Output Switching regulator 1 switching output
7 VINSW1 Supply Switching regulator 1 supply voltage
8 SYNCOUT Output External synchronization output (push-pull)
9 SYNCIN Input External synchronization input
10 FRDIV Input/output Switching frequency divider setting
11 VDOUT Output Voltage detector output (open drain)
12 FBSW1 Input/output Switching regulator 1 feedback voltage
13 COMP1 Input/output Switching regulator 1 compensation
14 SGND Ground Ground for linear blocks
15 VDIN Input Voltage detector threshold setting
16 VINHSD Supply High Side Driver supply
17 HSD Output High Side Driver output
18 VDDLY Input/output Voltage Detector delay setting
19 FBLDO Input/output LDO feedback voltage
20 VOUTLDO Output LDO output
21 LDOOK Output LDO voltage detector output (open drain)
22 LDOOKDLY Input/output LDOOK delay setting
23 VINLDO Supply LDO supply
24 COMP2 Input/output Switching regulator 2 compensation
25 FBSW2 Input/output Switching regulator 2 feedback voltage
26 SWGND Ground Low-power switching ground
27 VBAT Supply Common linear blocks supply voltage
28 SW1OKDLY Input/output SW1OK delay setting
30 SW1OK Output Switching regulator 1 voltage detector output (open drain)
31 VINSW2 Supply Switching regulator 2 supply voltage
33 PWM2 Output Switching regulator 2 switching output
34 BS2 Supply Switching regulator 2 boosted supply
36 PGND2 Ground Switching regulator 2 power ground
Table 2. PowerSSO-36 pins description (continued)
Figure 5. VQFPN-48 pinout configuration Table 3. VQFPN-48 pins description
1 BS2 Supply Switching regulator 2 boosted supply
5 PGND2 Ground Switching regulator 2 power ground
6 PGND2 Ground Switching regulator 2 power ground
7 PGND1 Ground Switching regulator 1 power ground
8 PGND1 Ground Switching regulator 1 power ground
12 BS1 Supply Switching regulator 1 boosted supply
13 PWM1 Output Switching regulator 1 switching output
15 SYNCOUT Output External synchronization output (push-pull)
16 SYNCIN Input External synchronization input
17 VINSW1 Supply Switching regulator 1 supply voltage
18 VINSW1 Supply Switching regulator 1 supply voltage
19 FRDIV Input/output Switching frequency divider setting
20 VDOUT Output Voltage detector output (open drain)
21 FBSW1 Input/output Switching regulator 1 feedback voltage
22 COMP1 Input/output Switching regulator 1 compensation
23 SGND Ground Ground for linear blocks
24 VDIN Input Voltage detector threshold setting
26 VINHSD Supply High Side Driver supply
27 VINHSD Supply High Side Driver supply
28 HSD Output High Side Driver output
29 HSD Output High Side Driver output
30 VDDLY Input/output Voltage Detector delay setting
31 FBLDO Input/output LDO feedback voltage
32 VOUTLDO Output LDO output
33 VOUTLDO Output LDO output
35 LDOOK Output LDO voltage detector output (open drain)
36 LDOOKDLY Input/output LDOOK delay setting
37 VINLDO Supply LDO supply
38 COMP2 Input/output Switching regulator 2 compensation
39 FBSW2 Input/output Switching regulator 2 feedback voltage
40 SWGND1 Ground Low-power switching ground
41 VBAT Supply Common linear blocks supply voltage
42 SW1OKDLY Input/output SW1OK delay setting
44 SW1OK Output Switching regulator 1 voltage detector output (open drain)
45 VINSW2 Supply Switching regulator 2 supply voltage
46 VINSW2 Supply Switching regulator 2 supply voltage
48 PWM2 Output Switching regulator 2 switching output
Table 3. VQFPN-48 pins description (continued)
5 Electrical specifications
5.1 Absolute maximum ratings
5.2 Thermal data
Table 4. Absolute maximum ratings Table 5. Thermal data (PowerSSO-36) Table 6. Thermal data (VQFPN-48)
5.3 Electrical characteristics
VBAT = VIN = 14.4 V, Tamb = 25 °C unless otherwise specified. Table 7. Electrical characteristics
1 Vacpp on VINLDO -7 0-d B
Table 7. Electrical characteristics (continued)
- Tests involving switching frequencies higher than 1 MHz are guaranteed by design.
- Test guaranteed by application measurements.
L5963 Functional Description
6 Functional Description
6.1 Operative modes
L5963 has three main operative modes: Shutdown mode: all enable pins are low and the device is completely off. In this condition the quiescent current is typically 1.5 μA. Standby mode: the linear regulator is configured as stand-by regulator by connecting ENLDO directly to VINLDO. In this condition the quiescent current is typically 25 μA. Normal mode: the linear regulator works as LDO and/or other blocks (DC/DC or HSD) are turned on.
6.2 Blocks functional description
6.2.1 Unregulated supply input voltage (VINLDO)
This terminal provides the power for internal circuitry to bias band-gap reference, standby regulator and other circuitry in the device. If backup function is needed, an external capacitor connected to this pin shall be charged through an external diode which is used to block reverse discharging. With backup function, when the system battery is removed or drops too low suddenly, the internal bias and regulator can operate correctly for a certain time, which avoids MCU to work abnormally and allows MCU to have enough time to turn-off.
6.2.2 Low voltage warning monitor (related pins: VDIN, VDOUT, VDDLY)
An external voltage can be sensed through the VDIN pin. This voltage is scaled using an external resistor network and compared with an internal threshold to detect a low voltage condition (Figure 9.). Once the input voltage is below the threshold, the low voltage warning output terminal (VDOUT) is pulled low after the designed glitch-filtering (~12 μs). VDOUT is an open drain output. If the input returns above the threshold with the specified hysteresis, VDOUT is released after a defined delay, determined by the capacitor on pin VDDLY. The threshold is fixed to 0.95 V typ. The capacitor on VDDLY pin sets VDOUT delay. A current source (~9 μA) on this pin charges the external capacitor to generate the required delay, programmable by adjusting the value of the capacitor. This voltage monitor can also be used to monitor DC/DC2 output. Changing the ratio of the external resistor divider the low voltage warning threshold can be adjusted.
Figure 9. Low voltage warning monitor & delay schematic
6.2.3 Power-good reset (related pins: LDOOK, LDOOKDLY)
LDOOKDLY is used to adjust the delay in the release of LDOOK output.
6.2.4 Power-good function of DC/DC1 (related pins: SW1OK, SW1OKDLY)
is used to adjust its delay.
6.2.5 Over voltage shutdown
VBAT pin, the other (OV2) detects VINLDO pin. threshold with the specified hysteresis. below the detection threshold with the specified hysteresis. and the regulator continues to work even if VINLDO increases.
6.2.6 Power ground (PGND1 and PGND2)
respectively. All switching nodes are referred to these two pins.
6.2.7 Signal ground (SGND)
This pin is the ground reference for standby regulator, HSD and internal bias.
6.2.8 PWM signal ground (SWGND)
This pin is the ground reference for signal part of DC/DC1 and DC/DC2.
6.2.9 TAB
TAB is connected to the device substrate. potential to avoid parasitic activation.
6.2.10 Linear regulator
Figure 10. Linear regulator diagram output voltage is set by an external resistor divider through the feedback pin FBLDO. As a non standby regulator, it has higher load capability (up to 250 mA).
Figure 11. Enable timing for standby regulator (ENLDO pin connect to supply directly) The linear regulator works as a non-standby regulator if ENLDO is <5 V.
Figure 12. Enable timing for linear regulator (pin ENLDO isn't connected to VINLDO) dropout voltage of 500 mV at rated load current. This regulator has an independent thermal protection and a current-limiting circuit. the battery drops too low (backup functionality).
6.2.11 High-side driver (HSD)
The HSD pin is the output of the high side driver. It has a dedicated enable pin ENHSD.
Functional Description L5963 Thermal protection The HSD has an independent thermal shutdown protection. If the local die temperature exceeds the thermal shutdown detection threshold, the HSD is disabled. It is enabled once the local die temperature falls below the detection threshold with the specified hysteresis. The invoking of thermal shut down on HSD does not directly affect any other outputs or circuitry in the IC. Short to ground The high side driver output is protected against shorts to ground. The faulted output returns to its pre-fault operating condition once the fault is removed. Short to supply The high-side driver is protected against shorts to battery. In such an event, the IC is not damaged. External components connected directly to the IC are not damaged by such exposure. Loss of ground protection The high side driver is protected against excessive leakage current to an external ground during a loss of supply ground (i.e. ground is open). During this event, the HSD is disabled and the IC is not damaged. Loss of battery protection (Unpowered shorts to battery, SPU) The high-side driver is protected against unpowered shorts to battery. In such an event, in typical applicative conditions, the IC will not suffer any damage. Below-ground protection The HSD output can be brought below ground by the inductive load. In this case, Power PMOS is turned on to charge the output, protecting itself.
6.2.12 Switching regulators
Figure 13. Switching regulators diagram regulation and line regulation.
Functional Description L5963 Both switching regulators can operate up to a 100% duty cycle. Once every four switching periods, the PWM output is forced low for 100ns typ to refresh the bootstrap capacitor. Their features include: Wide input voltage range (from 3.5 V to 26 V) Min output of 1 V 250 kHz free-run frequency and synchronization range from 250 kHz to 2 MHz. The voltage feed forward is implemented in all frequency range Internal 85 mΩ high-side and 105 mΩ low-side switching MOSFET Up to 3 A load current capability Power ok (SW1OK) output Internal soft start function to minimize startup inrush current Pulse-by-pulse current limiting (OCP) Discontinuous mode detection (DMC) Over temperature protection (OTP) UVLO with stop threshold at 2.8 V (typ) Load dump protection Externally adjustable compensation Stable with ceramic output capacitors Oscillator/switching frequency The internal oscillator provides a constant frequency clock of 250 kHz. The switching frequency of DC/DC1 and DC/DC2 are determined by the internal frequency clock and the external synchronization clock. When no clock is applied to the SYNCIN pin or the synchronization clock is lower than 125 kHz (half of the internal clock), the two switching regulators work both with the internal 250 kHz clock. When the SYNCIN pin has a synchronization clock larger than 125 kHz, the external synchronization clock is adopted. There is a phase shift of 180° between PWM1 and PWM2, and the frequency of PWM2 can be the same, 1/2, 1/4, 1/8 of PWM1 one. The division factor is programmed by FRDIV pin. The switching clock of DC/DC1 can be sent out by pin SYNCOUT to synchronize another device, in view of reducing EM disturbance. Internal high-side and low-side Power MOSFET / Bootstrap structure The two synchronous switching regulators don't need the external Schottky diode. Each of them integrates a high-side and a low-side n-channel Power MOSFET, which allows a very low drop voltage under high load current operation (up to 3 A). The Bootstrap structure is used to drive the high-side n-channel Power MOSFET. A Bootstrap capacitor of about 47 nF is needed. Internal soft start function (SS) To reduce the inrush current during startup, an internal soft start is implemented. The total soft start time is about 400 μs and it doesn't change with operating frequency.
L5963 Functional Description Pulse-by-pulse current limiting (OCP) The current in the upper MOSFET is monitored and if it exceeds the pulse-by-pulse over- current threshold (ILIM) then the upper MOSFET is turned off. Normal PWM operation resumes on the next oscillator clock pulse. DC/DCs’ embed leading edge blanking to prevent falsely triggering the pulse-by-pulse current limit when the upper MOSFET is turned on. The blanking time is about 100 ns, so the minimum switching on time should be bigger than 100 ns: Equation 1 From the above equation, when the input and output voltage are already known, the switching frequency should be within the range of the above equation, otherwise the OCP function is not guaranteed. Pulse-by-pulse current limiting is always active. The threshold of OCP is about 3.5 A for dc-dc1 and 4A for dc-dc2. Low-Side Over Current Protection (LS OCP) LS OCP protects DC/DCs by limiting inductor current, when either the load is too high at high frequency or when the output of the converter is shorted to ground. The current in the low-side MOSFET is monitored and, if it exceeds the pulse-by-pulse overcurrent threshold (ILIM), it prevents the turning on of the high-side MOSFET in the successive switching period. In high frequency and high load conditions, the inductor current cannot decrease even if HS OCP is triggered due to the blanking time, which results in the inductor current getting higher and higher every switching period. If inductor current reaches LS OCP threshold, that is set to a level higher than HS OCP one, PWM switching is stopped, waiting for the inductor current to decrease to a lower value. PWM switching will recover as soon as LS OCP is released. If high load and high frequency conditions remain, for instance in case of a short circuit being present on the regulator output, another LS OCP will occur. Upon removal of the short circuit PWM switching will immediately recover, bringing the regulator back to normal operation. Discontinuous Mode Detection (DMD) In order to save quiescent current when switching regulators are working in light load condition, L5963 embeds a Discontinuous Mode Detection (DMD) circuit: DMD prevents inductor current to continuously flow to ground during T off by turning off LS MOSFET and leaving PWM in tristate. Over temperature protection (OTP) Each DC/DC has its own OTP, which detects the local temperature and shuts down the regulator when temperature reaches the specified threshold. Dump protection If the voltage on VBAT supply exceeds the over-voltage shut-down threshold, DC/DCs are disabled. Once VBAT returns to working conditions, the output recovers to the normal state. I NS I $ NS 6N S37 /54 !
Functional Description L5963 Under voltage lock out (UVLO) The UVLO circuit generates the shutdown signal to turn off DC/DCs when VBAT is lower than the specified threshold. They are turned back on once VBAT goes above the detection threshold with the specified hysteresis.
7 Application information
7.1 Output inductor (Lo)
The value of the output inductor (Lo) is usually calculated to satisfy the peak-to-peak ripple current requirement. For the best compromise of cost, size and performance, it is suggested to keep the inductor current ripple between 20% and 40% of the maximum current. For example, if IL = IRipple = 0.3 x IOUT(max). Where, IOUT(max) is the maximum output current. Then, the inductor value can be estimated by the following equation: Equation 2 Where, fSW is the switching frequency, VIN(max) is the maximum input voltage. If VOUT = 3.3 V, VIN(max) = 26 V, fSW = 250 kHz, IL = 0.3 x 3 A = 0.9 A Equation 3 The next higher available value should be used, so L = 15 μH. The peak current flowing in Inductor is IL(peak) = IOUT(max) + IL / 2. If the Inductor value decreases, the peak current increases. The peak current has to be lower than the current limit of the device. An inductor having saturation current higher than the device current limit has to be chosen. , 6 I ) /54 37 , /54 t u ¹¸' MAX , ( (t uu u§
Application information L5963
7.2 Output capacitors (COUT)
Output capacitors are selected to support load transients and output ripple current, as well as to get loop stability. The amount of voltage ripple can be calculated by the output ripple current flowing in the Inductor: Equation 4 Usually the first term is dominant. However, if a ceramic capacitor (which is recommended) is adopted, the first term on the above equation can be neglected as the ESR value is very low. For example, in case Vout = 3.3 V, Vin = 14 V, fSW = 250 kHz, IL = 0.3 x 3 A = 0.9 A, in order to have a Vout = 5%* Vout =0.165 V, a 4.7 μF ceramic capacitor is needed. In case of not negligible ESR (electrolytic or tantalum capacitors), the capacitor is chosen taking into account its ESR value. In the above example, if a 100 μF with ESR = 100 mΩ electrolytic capacitor is chosen, the voltage drop on ESR dominates and the voltage ripple is 90 mV. The output capacitor is also important to sustain the output voltage during a load transient. In general, minimizing the ESR value and increasing the output capacitance results in a better transient response. The ESR can be minimized by simply adding more capacitors in parallel, or by using higher quality capacitors. If ceramic capacitors are chosen, in presence of a fast load transient the output voltage will change by the amount. Equation 5 Where: Iout(max), Iout(min) refer to the worst case load in the system and Vout is the tolerance of the regulated output voltage, 5% of Vout. For example, Vout = 5 V, Vin = 14 V, Iout(max) =1.5 A, Iout(min) = 0.5 A, L = 22 μH Equation 6 So two 10 μF ceramic capacitors in parallel are needed. The output capacitor is also important for loop stability: it fixes the double LC filter pole and the zero due to its ESR. In Section 7.5: Compensation network, it will be illustrated how to consider its effect in the system stability. '' '6% 3 2 ) ) # F OUT , OUT SW u uu '6 )) OUT OUT MAX OUT MIN OUT u u #6OUT #OUT 6OUT & u u )OUTMAX )OUTMIN 6OUT
7.3 Input capacitors (C IN)
The input capacitors must be chosen to support the maximum input operating voltage and the maximum RMS input current required by the device. The input capacitors must deliver the RMS current according to below equation: Equation 7 Where Io is the maximum DC output current and D is the duty cycle. This function has a maximum at D = 0.5 and it is equal to I o/2. Equation 8 Vdl is the voltage drop across the low side DMOS, and Vdh is the voltage drop across the high side DMOS. For example, with 20% duty cycle, the input/output current multiplier is 0.400. Therefore, if the regulator is delivering 3 A of steady-state load current, the input capacitor(s) must support 0.400 × 3 A or 1.2 Arms. Ceramic capacitors can deliver quite a bit of current but their total capacitance is relatively low. Electrolytic capacitors typically offer much more capacitance than ceramic capacitors, but can typically deliver a current of 100 to 500 mArms. So a good design will employ both types of capacitors with the ceramic capacitors placed closest to the input pins of the device. As a result, ceramic capacitors which have very low ESR and inductance are the best for filtering the high frequency switching noise, and electrolytic capacitors are typically able to provide more current over extended periods of time where VIN would otherwise droop.
7.4 Bootstrap capacitor (CBOOT)
A bootstrap capacitor must be connected between the BOOT and SW pins to provide floating gate drive to the high-side MOSFET. For most applications 47 nF is sufficient. This should be a ceramic capacitor with a voltage rating of at least 6 V.
7.5 Compensation network
The compensation network has to assure stability and good dynamic performance. The loop of the device is based on the voltage mode control, compatible with TYPE III compensation network ( Figure 14). The error amplifier is a voltage operational amplifier with large bandwidth, which is much larger than the closed-loop one. )RMS )O $$ u 6DH 6OUT 6DL 6IN 6DL
Figure 14. Closed loop system with TYPE III network
- Choose a value for R 1, usually between 2 k and 5 kΩ.
- Choose a gain (R 2/R1) that shifts the Open Loop Gain up to give the desired
an R2 that accomplishes this, given the system parameters and a chosen R1.
- C2 is calculated by placing the zero at 50% of the output filter double pole frequency:
- C1 can be calculated by placing the first pole at the ESR zero frequency:
- Set the second pole at half the switching frequency and also set the second zero at the
Figure 15. TYPE III compensated network diagram Here an example of calculating the external components network step by step. Assume TYPE III Compensation network. Using Equation 13, to find the inductor value, assume inductor ripple current of 0.9 A.
Application information L5963 The next higher available value should be used, so L = 22 μH. STEP 2 - Inductor peak current Using Equation 14, the peak inductor current is: Equation 14 STEP 3 - Calculate the output capacitance Using Equation 15, the output capacitance is: Equation 15 So choose two 10 μF ceramic capacitors in parallel, and the voltage ripple is within the spec. Equation 16 (ESR can be neglect due to ceramic cap) IL(peak) = Iout(max) + IL /2 = 3 A + (0.9/2) A= 3.45 A #OUT 6OUT X u u u )OUTMAX )OUTMIN 6OUT' XX & ''6 %32 u' )OUT , uu # F XX XX M6, OUT SW
STEP 4 - Calculate loop compensation values. Using Equation 17 to determine the "double pole": Equation 17 Using Equation 18 to determine the zero due to the ESR of the output capacitor Cout with ESR = 10 m: Equation 18 DBW = fc = 0.14 x fsw = 35kHz Choose R1 = 5 k, using Equation 19: Equation 19 R4 =1.24 kΩ PWM modulator gain. Equation 20 Where VIN is the typical input operating voltage, VOSC is the saw-tooth peak-to-peak value. Using Equation 21: Equation 21 R2 = 2.4 kΩ Using Equation 22: Equation 22 Choose C2 = 16 nF Using Equation 23: Equation 23 F OUT uuuu u K(Z S F # %32 K(Z%32 OUT uu uu uu u S 2 2 K K OUT 2%& 'AIN 6 ULATOR /3# MOD 2 $"7 F 6 2 K K,# /3# K K u u uu ' # 2§F & § uuu u u S # 2#F %32 §§§ u uu u u uuu S u &
Table 8. Components value for different output voltage cases
8 Thermal design
The PCB design should take into account also thermal aspects. the package junction to ambient thermal resistance. more thermal shut-down protections intervene. is the efficiency, as shown in Figure 7 and 8. Rthj-amb is the junction to ambient thermal resistance, as defined in Table 5 and Table 6. The slug has to be connected to the ground plane, whenever possible. Table 9. Maximum suggested power for L5963 in PSSO36 slug-down package Table 10. Maximum suggested power for L5963 in QFN48 package
It is possible to improve performance and application thermal behavior, adopting some expedients: Use the bottom layer as heat-sink, Shield inner layer tracks with ground planes, Use large paths for ground connections, instead of narrow and long paths with sharp corners, and transfer all ground connections to other layers by a proper number of vias, Place compensation network very close to the chip to reduce noise, Put coils and capacitors close to the pins, and build output path with large and short tracks.
9 Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark.
9.1 Package variation
This device use package Variations Option B to define exposed pad (see Table 11) or slug-up (see Table 12) dimensions.
9.2 PowerSSO-36 (exposed pad) package information
Figure 16. PowerSSO-36 (exposed pad) package outline Table 11. PowerSSO-36 exposed pad package mechanical data
Table 11. PowerSSO-36 exposed pad package mechanical data (continued)
- Values in inches are converted from mm and rounded to 4 decimal digits.
- Dimensions D and E1 do not include mold flash or protrusions. Allowable mold flash or protrusions is ‘0.25
9.3 PowerSSO-36 (slug-up) package information
Figure 17. PowerSSO-36 (slug-up) package outline Table 12. PowerSSO-36 slug-up package mechanical data
- Values in inches are converted from mm and rounded to 4 decimal digits.
- "D” and “E" do not include mold flash or protrusions Mold flash or protrusions shall not exceed 0.15 mm per
Table 12. PowerSSO-36 slug-up package mechanical data (continued)
Figure 18. VFQFPN-48 (7x7x1.0 - opt. D) package outline
9.5 Package marking information
Figure 19. PowerSSO-36 (exp. pad) marking information Table 13. VFQFPN-48 (7x7x1.0 - opt. D) package mechanical data
- Values in inches are converted from mm and rounded to 4 decimal digits.
– Two order codes in Table 1: Device summary on page 1. – Figure 21: VFQFPN-48 (7x7x1.0) marking information on page 47. – Section 8: Thermal design. Table 14. Document revision history 29-Oct-2015 1 Initial release.