STL55NH3LL STMICROELECTRONICS | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 14
Technical content
Datasheet sections
- 1 Electrical ratings
- 2 Electrical characteristics
- 2.1 Electrical characteristics (curves)
- 3 Test circuits
- 4 Package mechanical data
- 5 Revision history
Features
■ Improved die-to-footprint ratio ■ Very low profile package (1mm max) ■ Very low thermal resistance ■ Very low gate charge ■ Low threshold device Application ■ Switching applications
Description
This application specific Power MOSFET is the latest generation of STMicroelectronics unique “STripFET™” technology. The resulting transistor is optimized for low on-resistance and minimal gate charge. The chip-scaled PowerFLAT™ package allows a significant board space saving, still boosting the performance. Figure 1. Internal schematic diagram Table 1. Device summary
1 Electrical ratings
Table 2. Absolute maximum ratings
- Guaranteed for test time ≤ 15 ms
- The value is rated according R thj-c
- Pulse width limited by safe operating area
- The value is rated according R thj-pcb
Table 3. Thermal resistance
- When mounted on FR-4 board of 1inch², 2oz Cu, t < 10 sec
Table 4. Avalanche data
2 Electrical characteristics
Table 5. On/off states Table 6. Dynamic
Table 7. Switching times Table 8. Source drain diode
- Pulse width limited by safe operating area
- Pulsed: pulse duration=300 µs, duty cycle 1.5%
2.1 Electrical characteri stics (curves)
Figure 2. Safe operating area Figure 3. Thermal impedance Figure 4. Output characteristics Figure 5. Transfer characteristics Figure 6. Normalized B VDSS vs temperature Figure 7. Static drain-source on resistance
Figure 14. Allowable I av vs time in avalanche
3 Test circuits
Figure 15. Switching times test circuit for Figure 16. Gate charge test circuit Figure 17. Test circuit for inductive load Figure 18. Unclamped inductive load test Figure 19. Unclamped inductive wavefo rm Figure 20. Switching time waveform
Figure 21. Gate charge waveform
4 Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com
DIM. mm. inch A1 0.02 0.05 0.0007 0.0019 A3 0.20 0.007 D 5.00 0.196 D1 4.75 0.187 E 6.00 0.236 E1 5.75 0.226 e 1.27 0.050 PowerFLAT™ (6x5) MECHANICAL DATA
5 Revision history
Table 9. Document revision history 18-Mar-2008 1 First release.