L5150GJ_V01 STM | Alldatasheet
Document overview
- Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
- PDF pages: 29
Technical content
Datasheet sections
- 1 Block diagram and pins descrip tion
- 2 Electrical specifications
- 2.1 Absolute maximum ratings
- 2.2 Thermal data
- 2.3 Electrical characteristics
- 2.4 Electrical characteristics curves
- 3 Application information
- 3.1 Voltage regulator
- 3.2 Reset
- 3.3 Early warning
- 3.4 Enable
- 4 Package and PCB thermal data
- 4.1 PowerSSO-12 thermal data
- 5 Package information
- 5.1 PowerSSO-12 package information
- 5.2 PowerSSO-12 packing information
- 6 Revision history
Features
AEC-Q100 qualified Operating DC supply voltage range 5.6 V to 40 V Low dropout voltage Low quiescent current consumption Precision output voltage 5 V ± 2% Reset circuit sensing the output voltage Programmable reset pulse delay with external capacitor Adjustable reset threshold Early warning Very wide stability range with low value output capacitor Thermal shutdown and short-circuit protection Wide temperature range (Tj = -40 °C to 150 °C) Enable input for enabling / disabling the voltage regulator
Description
L5150GJ is a low dropout linear regulator with microprocessor control functions such as power on reset, low voltage reset, early warning, on/off control. Typical quiescent current is 55 µA in very low output current mode and enabled regulator. It drops to 5 µA with not enabled regulator. On chip trimming results in high output voltage accuracy (+/-2%). Accuracy is kept over wide temperature range, line and load variation. Early warning circuit monitors the input voltage and compares it with an internal voltage reference. Output voltage reset threshold can be adjusted down to 3.5 V by means of an external voltage divider. The maximum input voltage is 40 V. The max output current is internally limited. Internal temperature protection disables the voltage regulator output. In addition, only low-value ceramic capacitor on output is required for stability. Max DC supply voltage V S 40 V Max output voltage tolerance ΔV o ±2% Max dropout voltage V dp 500 mV Output current I o 150 mA Quiescent current I qn 5 µA(1) 55 µA(2) 1. Typical value with regulator disabled. 2. Typical value with regulator enabled. PowerSSO-12 GAPGP01380 Table 1. Device summary
1 Block diagram and pins description
Figure 1. Block diagram Figure 2. Configuration diagram (top view)
Table 2. Pins description to 3.5 V. Connect to GND if not needed. ground to adjust the reset delay time. Keep open if not needed. (Co 220 nF for regulator stability). 7V S Supply voltage, block directly to GND on the IC with a capacitor.
10 EW i
a resistor divider. Connect to VS if not needed.
12 EW o
reference voltage. Keep open if not needed.
2 Electrical specifications
2.1 Absolute maximum ratings
extended periods may affect device reliability.
2.2 Thermal data
Table 3. Absolute maximum ratings Table 4. Thermal data
- The values quoted are for PCB 77 mm x 86 mm x 1.6 mm, FR4, double copper layer with single heatsink
layer, copper thickness 70 µm, thermal vias, copper area 2 cm2.
2.3 Electrical c haracteristics
Table 5. General
- Measured output current when the output voltage has dropped 1 00 mV from its nominal value obtained at
- Vs - V o measured dropout when the output voltage has dropped 100 mV from its nominal value obtained at
Table 6. Reset Table 5. General (continued)
2.4 Electrical char acteristics curves
Table 7. Early warning Table 8. Enable Figure 3. Output voltage vs. Tj Figure 4. Output voltage vs. V S
Figure 23. PSRR
3 Application information
3.1 Voltage regulator
GND and a thermal shutdown are provided. Figure 24. Application schematic Stability region is reported in Figure 25.
3.2 Reset
The reset circuit monitors the output voltage Vo. If the output voltage becomes lower than Vo_th then Res goes low with a delay time (trr). When the output voltage becomes higher than Vo_th then Res goes high with a delay time trd. This delay is obtained by 32 periods of oscillator. The oscillator period is given by: Equation 1 Tosc = [(VRhth - VRlth) x Ctr] / Icr + [(VRhth - VRlth) x Ctr] / Idr where: Icr = 20 µA is an internally generated charge current, Idr = 20 µA is an internally generated discharge current, VRhth = 2.5 V (typ) and VRlth = 0.9 V (typ) are two voltage thresholds, Ctr is an external capacitor put between Vcr pin and GND.
Figure 27. Reset time diagram
3.3 Early warning
Figure 28. Early warning time diagram
3.4 Enable
L5150GJ is also provided with an enable input, an high signal switches the regulator on.
4 Package and PCB thermal data
4.1 PowerSSO-12 thermal data
Figure 29. PowerSSO-12 PC board
- Layout condition of R th and Zth measurements (PCB: double layer, thermal vias,
footprint dimension 4.1 mm x 6.5 mm ). Figure 30. Rthj-amb vs PCB copper area in open box free air condition
Table 9. PowerSSO-12 thermal parameter
5 Package information
specifications, grade definitions and product status are available at: www.st.com.
5.1 PowerSSO-12 pa ckage information
Figure 33. PowerSSO-12 package outline
Table 10. PowerSSO-12 package mechanical data
5.2 PowerSSO-12 pa cking information
Figure 34. PowerSSO-12 tube shipment (no suffix) Figure 35. PowerSSO-12 tape and reel shipment (suffix “TR”)
6 Revision history
Table 11. Document revision history 09-Aug-2007 1 Initial release. Modified Description on cover page. – added Ioth_H, Ioth_L, Ioth parameters. – changed I_leak typ. value from 3 µA to 1.8 µA. Modified Section 3.2: Reset.
Table 11. Document revision history (continued)
Updated Table 2: Pins description. Updated Section 3.1: Voltage regulator. Corrected Equation 3 on Section 3.2: Reset. Updated footnote description of Table 4: Thermal data. Updated Table 9: PowerSSO-12 thermal parameter. 30-Jan-2012 9 Updated Figure 25: Stability region on page 16. 07-Feb-2012 10 Modified Figure 25: Stability region on page 16. 19-Sep-2013 12 Updated disclaimer. 03-Jun-2015 13 Changed in Table 5 the typical value of SVR from 60 dB to 48 dB. 27-Sep-2018 14 Updated title and Features.