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Sample & Buy T echnical Documents Tools & Software Support & Community LM5109B SNVS477C –FEBRUARY 2007–REVISED JANUARY 2016 LM5109BHighVoltage1-APeakHalf-BridgeGateDriver
1 Features 3 Description
The LM5109B device is a cost-effective, high-voltage 1• Drives Both a High-Side and Low-Side N-Channel gate driver designed to drive both the high-side andMOSFET the low-side N-channel MOSFETs in a synchronous• 1-A Peak Output Current (1.0-A Sink and 1.0-A buck or a half-bridge configuration. The floating Source) high-side driver is capable of working with rail voltages up to 90 V. The outputs are independently• Inputs Compatible With Independent TTL and controlled with cost-effective TTL andCMOS CMOS-compatible input thresholds. The robust level• Bootstrap Supply Voltage to 108-V DC shift technology operates at high speed while• Fast Propagation Times (30 ns Typical) consuming low power and providing clean level
- Drives 1000-pF Load With 15-ns Rise and Fall transitions from the control input logic to the high-side gate driver. Undervoltage lockout is provided on bothTimes the low-side and the high-side power rails. The• Excellent Propagation Delay Matching (2 ns device is available in the 8-pin SOIC and thermally-Typical) enhanced 8-pin WSON packages.
- Supply Rail Undervoltage Lockout Device Information(1)• Low Power Consumption PART NUMBER PACKAGE BODY SIZE (NOM)• 8-Pin SOIC and Thermally-Enhanced 8-Pin SOIC (8) 4.90 mm × 3.91 mmWSON Package LM5109B WSON (8) 4.00 mm × 4.00 mm
2 Applications (1) For all available packages, see the orderable addendum at
the end of the data sheet.• Current-Fed, Push-Pull Converters
- Half- and Full-Bridge Power Converters
- Solid-State Motor Drives
- Two-Switch Forward Power Converters Simplified Application Diagram An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.
SNVS477C –FEBRUARY 2007–REVISED JANUARY 2016 www.ti.com Table of Contents
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision B (March 2013) to Revision C Page
- Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Changes from Revision A (March 2013) to Revision B Page
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5 Pin Configuration and Functions
DESCRIPTION
NO.(1) NAME TYPE(2) Positive gate drive supply – Locally decouple to VSS using low ESR and ESL capacitor located1 VDD P as close to IC as possible. High-side control input – The HI input is compatible with TTL and CMOS input thresholds.2 HI I Unused HI input must be tied to ground and not left open. Low-side control input – The LI input is compatible with TTL and CMOS input thresholds.3 LI I Unused LI input must be tied to ground and not left open. 4 VSS G Ground – All signals are referenced to this ground. 5 LO O Low-side gate driver output – Connect to the gate of the low-side N-MOS device. High-side source connection – Connect to the negative terminal of the bootstrap capacitor and6 HS P to the source of the high-side N-MOS device. 7 HO O High-side gate driver output – Connect to the gate of the high-side N-MOS device. High-side gate driver positive supply rail – Connect the positive terminal of the bootstrap 8 HB P capacitor to HB and the negative terminal of the bootstrap capacitor to HS. The bootstrap capacitor must be placed as close to IC as possible. (1) For 8-pin WSON package, TI recommends that the exposed pad on the bottom of the package be soldered to ground plane on the PCB and the ground plane must extend out from underneath the package to improve heat dissipation. (2) G = Ground, I = Input, O = Output, and P = Power Copyright © 2007–2016, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: LM5109B
SNVS477C –FEBRUARY 2007–REVISED JANUARY 2016 www.ti.com
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT VDD to VSS –0.3 18 V HB to HS –0.3 18 V LI or HI to VSS –0.3 VDD + 0.3 V LO to VSS –0.3 VDD + 0.3 V HO to VSS VHS – 0.3 VHB + 0.3 V HS to VSS(2) –5 90 V HB to VSS 108 V Junction temperature –40 150 °C Storage temperature, Tstg –55 150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) In the application the HS node is clamped by the body diode of the external lower N-MOSFET, therefore the HS voltage will generally not exceed –1 V. However in some applications, board resistance and inductance may result in the HS node exceeding this stated voltage transiently. If negative transients occur on HS, the HS voltage must never be more negative than VDD – 15 V. For example, if VDD = 10 V, the negative transients at HS must not exceed –5 V.
6.2 ESD Ratings
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±1500 V(ESD) Electrostatic discharge V Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VDD 8 14 V HS(1) –1 90 V HB VHS + 8 VHS + 14 V HS slew rate 50 V/ns Junction temperature –40 125 °C (1) In the application, the HS node is clamped by the body diode of the external lower N-MOSFET, therefore the HS voltage will generally not exceed –1 V. However in some applications, board resistance and inductance may result in the HS node exceeding this stated voltage transiently. If negative transients occur on HS, the HS voltage must never be more negative than VDD – 15 V. For example, if VDD = 10 V, the negative transients at HS must not exceed –5 V.
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6.4 Thermal Information
THERMAL METRIC(1) D (SOIC) NGT (WSON) UNIT
8 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance 117.6 42.3 °C/W RθJC(top) Junction-to-case (top) thermal resistance 64.9 34.0 °C/W RθJB Junction-to-board thermal resistance 58.1 19.3 °C/W ψJT Junction-to-top characterization parameter 17.4 0.4 °C/W ψJB Junction-to-board characterization parameter 57.6 19.5 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance – 8.1 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.
6.5 Electrical Characteristics
TJ = 25°C (unless otherwise specified), VDD = VHB = 12 V, VSS = VHS = 0 V, No Load on LO or HO PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY CURRENTS TJ = 25°C 0.3 IDD VDD quiescent current LI = HI = 0 V mA TJ = –40°C to 125°C 0.6 TJ = 25°C 1.8 IDDO VDD operating current f = 500 kHz mA TJ = –40°C to 125°C 2.9 TJ = 25°C 0.06 IHB Total HB quiescent current LI = HI = 0 V mA TJ = –40°C to 125°C 0.2 TJ = 25°C 1.4 IHBO Total HB operating current f = 500 kHz mA TJ = –40°C to 125°C 2.8 TJ = 25°C 0.1 IHBS HB to VSS current, quiescent VHS = VHB = 90 V µA TJ = –40°C to 125°C 10 IHBSO HB to VSS current, operating f = 500 kHz 0.5 mA INPUT PINS LI AND HI TJ = 25°C 1.8 VIL Low level input voltage threshold V TJ = –40°C to 125°C 0.8 TJ = 25°C 1.8 VIH High level input voltage threshold V TJ = –40°C to 125°C 2.2 TJ = 25°C 200 RI Input pulldown resistance kΩ TJ = –40°C to 125°C 100 500 UNDERVOLTAGE PROTECTION TJ = 25°C 6.7 VDDR VDD rising threshold VDDR = VDD – VSS V TJ = –40°C to 125°C 6.0 7.4 VDDH VDD threshold hysteresis 0.5 V TJ = 25°C 6.6 VHBR HB rising threshold VHBR = VHB – VHS V TJ = –40°C to 125°C 5.7 7.1 VHBH HB threshold hysteresis 0.4 V LO GATE DRIVER TJ = 25°C 0.38 VOLL Low-level output voltage ILO = 100 mA, VOHL = VLO – VSS V TJ = –40°C to 125°C 0.65 TJ = 25°C 0.72 VOHL High-level output voltage ILO = −100 mA, VOHL = VDD – VLO V TJ = –40°C to 125°C 1.2 IOHL Peak pullup current VLO = 0 V 1 A IOLL Peak pulldown current VLO = 12 V 1 A Copyright © 2007–2016, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: LM5109B
6.6 Switching Characteristics
Figure 1. Typical Test Timing Diagram
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44 C L = 0 pF
6.7 Typical Characteristics
Figure 3. HB Operating Current vs FrequencyFigure 2. VDD Operating Current vs Frequency Figure 4. Operating Current vs Temperature Figure 5. Quiescent Current vs Temperature Figure 6. Quiescent Current vs Voltage Figure 7. Propagation Delay vs Temperature
Figure 8. LO and HO High Level Output Voltage Figure 9. LO and HO Low Level Output Voltage Figure 10. Undervoltage Rising Thresholds Figure 11. Undervoltage Hysteresis vs Temperature Figure 12. Input Thresholds vs Temperature Figure 13. Input Thresholds vs Supply Voltage
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7 Detailed Description
7.1 Overview
the low-side and the high-side power rails.
7.2 Functional Block Diagram
7.3 Feature Description
7.3.1 Start-Up and UVLO
the bootstrap capacitor (VHB–HS) will only disable the high-side output (HO). Table 1. VDD UVLO Feature Logic Operation
Table 2. VHB-HS UVLO Feature Logic Operation
7.3.2 Level Shift
provides excellent delay matching with the low-side driver.
7.3.3 Output Stages
side output stage is referenced to VSS and the high-side is referenced to HS.
7.4 Device Functional Modes
dependent on the states of the HI and LI pins. The output HO and LO will be low if input state is floating. Table 3. INPUT and OUTPUT Logic Table (1) HO is measured with respect to the HS. (2) LO is measured with respect to the VSS.
7.5 HS Transient Voltages Below Ground
- HS must always be at a lower potential than HO. Pulling HO more than –0.3 V below HS can activate
be placed as close to the IC pins as possible to be effective.
- HB to HS operating voltage must be 15 V or less. Hence, if the HS pin transient voltage is –5 V, VDD must
be ideally limited to 10 V to keep HB to HS below 15 V.
- Low-ESR bypass capacitors from HB to HS and from VDD to VSS are essential for proper operation. The
leads of the IC which must be avoided for reliable operation.
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8 Application and Implementation
validate and test their design implementation to confirm system functionality.
8.1 Application Information
from the controller into the driver. independent flexibility to control ON and OFF-time of the output.
8.2 Typical Application
Figure 14. LM5109B Driving MOSFETs in a Half-Bridge Converter
8.2.1 Design Requirements
Table 4 lists the design parameters of the LM5109B. Table 4. Design Example
8.2.2 Detailed Design Procedure
8.2.2.1 Select Bootstrap and VDD Capacitor
The bootstrap capacitor must maintain the VHB-HS voltage above the UVLO threshold for normal operation. Calculate the maximum allowable drop across the bootstrap capacitor with Equation 1.
- VDD = Supply voltage of the gate drive IC
- VDH = Bootstrap diode forward voltage drop
- VHBL = VHBRmax – VHBH, HB falling threshold (1) Then, the total charge needed per switching cycle is estimated by Equation 2. where
- QG = Total MOSFET gate charge
- IHBS = HB to VSS Leakage current
- DMax = Converter maximum duty cycle
- IHB = HB Quiescent current (2) Therefore, the minimum CBoot must be: (3) In practice, the value of the CBoot capacitor must be greater than calculated to allow for situations where the power stage may skip pulse due to load transients. TI recommends having enough margins and place the bootstrap capacitor as close to the HB and HS pins as possible. CBoot = 100 nF (4) As a general rule the local VDD bypass capacitor must be 10 times greater than the value of CBoot, as shown in Equation 5. CVDD = 1 µF (5) The bootstrap and bias capacitors must be ceramic types with X7R dielectric. The voltage rating must be twice that of the maximum VDD considering capacitance tolerances once the devices have a DC bias voltage across them and to ensure long-term reliability.
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LOL Gate FET_Int VI R R R DD OHL LOH Gate GFET_Int VI R R R DD DH OLH HOL Gate GFET_Int V V I R R R DD DH OHH HOH Gate GFET_Int V V 10 V 1 VI 0.48 AR R R 1.2 V / 100 mA 4.7 2.2 : : DD DH DBoot(pk) Boot V V 10 V 1 VI 4 A R 2.2 | : LM5109B www.ti.com SNVS477C –FEBRUARY 2007–REVISED JANUARY 2016
8.2.2.2 Select External Bootstrap Diode and Its Series Resistor
The bootstrap capacitor is charged by the VDD through the external bootstrap diode every cycle when low-side MOSFET turns on. The charging of the capacitor involves high peak currents, and therefore transient power dissipation in the bootstrap diode may be significant and the conduction loss also depends on its forward voltage drop. Both the diode conduction losses and reverse recovery losses contribute to the total losses in the gate driver circuit. For the selection of external bootstrap diodes, refer to AN-1317 Selection of External Bootstrap Diode for LM510X Devices, SNVA083. Bootstrap resistor RBOOT is selected to reduce the inrush current in DBOOT and limit the ramp up slew rate of voltage of VHB-HS during each switching cycle, especially when HS pin have excessive negative transient voltage. RBOOT recommended value is between 2 Ω and 10 Ω depending on diode selection. A current limiting resistor of 2.2 Ω is selected to limit inrush current of bootstrap diode, and the estimated peak current on the DBoot is shown in Equation 6. where
- VDH is the bootstrap diode forward voltage drop (6)
8.2.2.3 Selecting External Gate Driver Resistor
The external gate driver resistor, RGATE, is sized to reduce ringing caused by parasitic inductances and capacitances and also to limit the current coming out of the gate driver. Peak HO pullup current are calculated in Equation 7. where
- IOHH = Peak pullup current
- VDH = Bootstrap diode forward voltage drop
- RHOH = Gate driver internal HO pullup resistance, provide by driver data sheet directly or estimated from the testing conditions, that is RHOH = VOHH / IHO
- RGate = External gate drive resistance
- RGFET_Int = MOSFET internal gate resistance, provided by transistor data sheet (7) Similarly, Peak HO pulldown current is shown in Equation 8. where
- RHOL is the HO pulldown resistance (8) Peak LO pullup current is shown in Equation 9. where
- RLOH is the LO pullup resistance (9) Peak LO pulldown current is shown in Equation 10. where
- RLOL is the LO pulldown resistance (10) For some scenarios, if the applications require fast turnoff, an anti-paralleled diode on RGate could be used to bypass the external gate drive resistor and speed up turnoff transition. Copyright © 2007–2016, Texas Instruments Incorporated Submit Documentation Feedback 13 Product Folder Links: LM5109B
GD_R SW GD_R Gate GFE QG1 T & G n I t DD R ¦ R R RP 2 V Q u u u u LM5109B SNVS477C –FEBRUARY 2007–REVISED JANUARY 2016 www.ti.com
8.2.2.4 Estimate the Driver Power Loss
The total driver IC power dissipation can be estimated through the following components. 1. Static power losses, PQC, due to quiescent current – IDD and IHB PQC = VDD × IDD + (VDD – VDH) × IHB (11) 2. Level-shifter losses, PIHBS, due high-side leakage current – IHBS PIHBS = VHB × IHBS × D where
- D is the high-side switch duty cycle (12) 3. Dynamic losses, PQG1&2, due to the FETs gate charge – QG where
- QG = Total FETs gate charge
- fSW = Switching frequency
- RGD_R = Average value of pullup and pulldown resistor
- RGate = External gate drive resistor
- RGFET_Int = Internal FETs gate resistor (13) 4. Level-shifter dynamic losses, PLS, during high-side switching due to required level-shifter charge on each switching cycle – QP PLS = VHB × QP × fSW (14) In this example, the estimated gate driver loss in LM5109B is shown in Equation 15. (15) For a given ambient temperature, the maximum allowable power loss of the IC can be defined as shown in Equation 16. where
- PLM5109B = The total power dissipation of the driver
- TJ = Junction temperature
- TA = Ambient temperature
- RθJA = Junction-to-ambient thermal resistance (16) The thermal metrics for the driver package is summarized in the Thermal Information table of the data sheet. For detailed information regarding the thermal information table, please refer to the Texas Instruments application note entitled Semiconductor and IC Package Thermal Metrics (SPRA953).
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8.2.3 Application Curves
channel (HI, LI, HO, and LO) is labeled and displayed on the left hand of the waveforms. The testing condition: load capacitance is 1 nF, VDD = 12 V, fSW = 500 kHz. Figure 15. Rising Time and Turnon Propagation Delay Figure 16. Falling Time and Turnoff Propagation Delay
9 Power Supply Recommendations
keeping a 4-V margin to allow for transient voltage spikes. requirements. In a similar manner, the current pulses delivered by the HO pin are sourced from the HB pin. Therefore a 22-nF to 220-nF local decoupling capacitor is recommended between the HB and HS pins.
10 Layout
10.1 Layout Guidelines
- Low-ESR and low-ESL capacitors must be connected close to the IC between VDD and VSS pins and
- To prevent large voltage transients at the drain of the top MOSFET, a low-ESR electrolytic capacitor and a
good-quality ceramic capacitor must be connected between the MOSFET drain and ground (VSS).
- To avoid large negative transients on the switch node (HS) pin, the parasitic inductances between the source
of the top MOSFET and the drain of the bottom MOSFET (synchronous rectifier) must be minimized.
- Grounding considerations:
current. Minimizing this loop length and area on the circuit board is important to ensure reliable operation.
10.2 Layout Example
Figure 17. Layout Example
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
- AN-1317 Selection of External Bootstrap Diode for LM510X Devices, SNVA083
- Semiconductor and IC Packaging Thermal Metrics, SPRA953
11.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.
11.3 Trademarks
E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
11.5 Glossary
SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Copyright © 2007–2016, Texas Instruments Incorporated Submit Documentation Feedback 17 Product Folder Links: LM5109B
www.ti.com 15-Oct-2015 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples LM5109BMA NRND SOIC D 8 95 TBD Call TI Call TI -40 to 125 L5109 BMA LM5109BMA/NOPB ACTIVE SOIC D 8 95 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 L5109 BMA LM5109BMAX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 L5109 BMA LM5109BSD/NOPB ACTIVE WSON NGT 8 1000 Green (RoHS & no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 125 5109BSD LM5109BSDX/NOPB ACTIVE WSON NGT 8 4500 Green (RoHS & no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 125 5109BSD (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device.
www.ti.com 15-Oct-2015 Addendum-Page 2 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 15-Oct-2015 Pack Materials-Page 1
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM5109BMAX/NOPB SOIC D 8 2500 367.0 367.0 35.0 LM5109BSD/NOPB WSON NGT 8 1000 203.0 203.0 35.0 LM5109BSDX/NOPB WSON NGT 8 4500 346.0 346.0 35.0 PACKAGE MATERIALS INFORMATION www.ti.com 15-Oct-2015 Pack Materials-Page 2
www.ti.com SDC08A (Rev A)
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