L4985 STMICROELECTRONICS | Alldatasheet
Document overview
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- PDF pages: 27
Technical content
Datasheet sections
- 1 Block diagram and typical application
- 2 Pin connection and functions
- 3 Electrical data
- 3.1 Absolute maximum ratings
- 3.2 Thermal data
- 4 Electrical characteristics
- 5 Application information
- 5.1 Theory of operation
- 5.2 OFF-time modulator
- 5.3 High voltage startup
- 5.4 Input line discharge (X-cap discharge function)
- 5.5 Soft-start
- 5.6 No load operation (burst-mode function)
- 5.7 Idle operation (external burst-mode function)
- 5.8 Disable operation (DISABLE function)
- 5.9 Protections
- 5.9.1 AC brown-in (BI function)
- 5.9.2 AC brownout (BO function)
- 5.9.3 Output overvoltage (OVP function)
- 5.9.4 Overcurrent (OCP1 function)
- 5.9.5 Inductor saturation detection (OCP2 function)
- 5.9.6 Feedback failure detection
- 5.10 Line feedforward
- 6 Package information
- 6.1 SO-8 package information
- 7 Ordering information
Datasheet sections
Features
- Peak current mode CCM-operated
- 800 V high voltage startup with integrated input voltage sensing
- Active input filter capacitor discharge
- Proprietary multiplier “emulator” with minimum THD of line current in all operating conditions (CCM and DCM)
- Extremely few external components
- Protections: feedback loop failure, OVP, OCP, inductor saturation, brown-in, brownout (compliant to medical SMPS standards)
- Inductor current sense
- Disable and low consumption function
- In-rush current monitoring
- Soft-start for smooth startup
- 1.2% (@ Tj = 25 °C) internal reference voltage
- 65 kHz (A version) and 130 kHz (B version) switching frequency
- SO8 package Application
- PFC pre-regulators for: – IEC61000-3-2 and JEIDA-MITI compliant SMPS in excess of 1 kW – Desktop PC, server, web server, game console – High power LED luminaries – Industrial and medical SMPS according to IEC 60601-1-2
Description
The L4985 is a peak current-mode PFC controller for boost converter with a proprietary multiplier “emulator” which in addition to the innovative THD optimizers guarantee very low Total Harmonic Distortion (THD) performance in all operating conditions. The device comes in a pin SO package and offers a high performance/ low-component count solution for CCM-operated boost PFC pre-regulators in EN61000-3-2 and JEIDA-MITI compliant applications, in a power range that spans from few hundred W to some kW. The device, thanks to a proprietary off-time modulator, operates in quasi-fixed frequency in all operating conditions. Two options are available, 65 kHz for A and 130 kHz for B. The 800V high voltage start-up block includes also the circuitry to discharge the X-capacitors of the EMI filter to a safe level. This allows the unit to meet safety regulation (such as IEC 61010-1 or IEC 62368-1) without using the traditional discharge resistor in parallel to the X-capacitors. The device features low consumption and disable functions allowing usage in applications supposed to comply even with the latest energy saving requirements issued by Energy Star, the Department of Energy (DoE) in the United States, the European Code of Conduct, the European Union’s Ecodesign Directive, and other guidelines. Product status link L4985 L4985A L4985B L4985ATR L4985BTR Product summary Order codes Package Packaging L4985A SO-8 Tube L4985B Tube L4985ATR Tape and reel L4985BTR Tape and reel CCM PFC controller with high voltage startup L4985 Datasheet DS13769 - Rev 3 - January 2022 For further information contact your local STMicroelectronics sales office.
Product label In addition to an overvoltage protection able to keep the output voltage under control during transient conditions, the IC is provided also with a protection against feedback loop failures or erroneous settings and boost inductor saturation. The brownout protection function allows to design medical equipment according to the latest regulations driven by IEC 60601-1-2 which requires the output regulation in case of mains dips lasting up to 500 msec. Soft-start limits the peak current. The totem-pole output stage, capable of 0.7 A source and 1.5 A sink current, is suitable for big MOSFET or IGBT drives. L4985 DS13769 - Rev 3 page 2/27
1 Block diagram and typical application
Figure 1. Block diagram Figure 2. Typical application
2 Pin connection and functions
Figure 3. Pin connection (top view) Table 1. Pin description
1 VCC
to get a clean bias voltage. source current and 1.5 A sink current (typical values).
3 GND
separate from any pulsed current return. Current sense input. The inductor current is sensed through a resistor RS on the current return side. adding a series resistor (RTHD_CCM) for improved THD in CCM operation. circuit does. In this way, the peak inductor current is limited at a maximum of 0.49/RS. Inverting input of the trans-conductance Error Amplifier (OTA). overshoot, the switching activity is stopped until VFB < VFB_R (2.55V typ.). Section 5.9.6 Feedback failure detection for further details.
No. Name Function
6 COMP
Output pin of the trans-conductance Error Amplifier (OTA). A compensation network is placed between this pin and GND to allow stability of the control loop and ensure high PF and THD. To avoid uncontrolled rise of the output voltage at light or zero load, when VCOMP < VCOMP_S (1 V typ. Burst Mode condition) the gate driver pin (GD) is forced low and the switching activity is stopped. If the Burst Mode condition is triggered when GD is high, the system is allowed to complete the current on-time and the system stoppage takes place after GD falling edge. The pin can be also used to disable the device by forcing VCOMP < VCOMP_DIS (0.7 V typ.) by means of an external pull-down active network. 7 N.C. High voltage spacer. This pin is not internally connected to isolate the high voltage section and ease compliance with safety regulations (creepage distance) on the PCB. 8 HV High voltage start-up generator input / AC voltage sensing input. The pin, able to withstand 800 V, has to be connected to the AC side of the input bridge via a pair of diodes (1N400x type) to sense the AC input voltage. If the voltage on the pin is higher than VHV_START (29 V typ.), an internal pull-up circuit charges the capacitor connected between the pin VCC and GND. Initially the current is low for safety in case of a shorted VCC, and then it goes to the normal level as far as the VCC pin reaches the start-up threshold (VCC_ON). The generator is re-enabled when the voltage on the VCC pin falls below the UVLO threshold (VCC_OFF). The pin is used also to sense the AC voltage, which is used by the AC brownout, the input voltage feedforward and the THD-CCM optimizer functions. An internal logic circuit detects that the unit has been detached from the power line; if this event occurs then, the HV pin sinks a current to discharge the X-capacitors of the EMI filter to a safe level. This allows the unit to meet safety regulations (such as IEC 61010-1 or IEC 62368-1) without using the traditional discharge resistor in parallel to the X-capacitor, thus saving the associated power losses and enabling ultra-low consumption in standby conditions. In case an AC brownout condition is detected the internal generator is alternatively turned on and off and, as a consequence, the voltage at VCC pin cycles between the start-up threshold and the UVLO threshold. L4985 Pin connection and functions DS13769 - Rev 3 page 5/27
3 Electrical data
3.1 Absolute maximum ratings
Table 2. Absolute maximum ratings Table 3. Recommended operating conditions. VCC 1 IC supply voltage -0.3 24.5 V Internal clamp at 24.5 V min. FB 5 Feedback input -0.3 3.0 V Internal clamp at 3 V min.
3.2 Thermal data
Table 4. Thermal data
4 Electrical characteristics
Tj = -25 to 125 °C, VCC = 15 V, CGD = 1 nF unless otherwise specified. Table 5. Electrical characteristics
Electrical characteristics
Symbol Parameter Test Condition Min. Typ. Max. Unit TDB_ACBI Brown-in debounce time First time VCC > VCC_ON 0.8 1 1.2 ms 32 40 48 ms X-CAPACITOR DISCHARGE FUNCTION VHV_MIN Peak residual voltage IHV_DIS > 5 mA 45 V IHV_DIS Discharge current VHV = 45 V 5 mA TDECT_XCAP Detection time 51 64 77 ms ERROR AMPLIFIER VREF Voltage feedback input threshold Tj = 25 °C 2.47 2.5 2.53 V 10 V < VCC < 24.5 V(1) 2.45 2.57 V IFB Input bias current VFB = 0 to 3 V -0.1 0 0.1 µA VFBCLAMP Internal clamp level IFB = 1 mA 3.0 3.3 V gm Transconductance gain VREF -150 mV < VFB < VREF +150 mV 160 200 240 µS RO Output impedance 5 MΩ ICOMP Source current VCOMP = 3 V, VFB=1.9 V 0.7 1 1.45 mA Sink current VCOMP = 3 V, VFB=3.0 V 0.7 1 1.45 mA VCOMP Upper saturation voltage ISOURCE = 0.2 mA 5.0 V Lower clamp voltage VFB = 3.0 V 0.8 0.9 DYNAMIC (D_OVP) and STATIC (S_OVP) OVERVOLTAGE PROTECTIONS VCOMP_S Burst mode threshold S_OVP (Static OVP) Voltage falling(1) 0.95 1.00 1.05 V VCOMP_R Restart threshold after S_OVP Voltage rising(1) 1 1.05 1.1 V VFB_S D_OVP disable threshold 10 V < VCC < 24.5 V 2.595 2.675 2.755 V VFB_R Restart threshold after D_OVP 10 V < VCC < 24.5 V 2.44 2.55 2.65 V DISABLE VCOMP_DIS Disable threshold Voltage falling(1) 0.65 0.7 0.75 V VCOMP_EN Enable threshold Voltage rising(1) 0.85 0.9 0.95 V ICOMP_DIS Pull-up current at disable 8 12 16 µA CURRENT SENSING ICS Leakage bias current VCS = -0.5 V 15 21 µA VCS = 0.235 V 7.5 10 14 µA VCS_OFS CS level shifter offset CS = 0 V 3 10 17 mV VCS_GAIN CS level shifter gain C = -0.5 V 0.94 0.98 1.02 V/V VCS_OCP1 1st level overcurrent threshold -510 -490 -470 mV TSS_OCP1 1st level OCP threshold ramp up time 104 130 156 ms TBLK Leading edge blanking HV > 73 V rising 120 150 180 ns HV < 45 V falling 235 310 385 ns td(H-L) Delay to output 110 ns VCS_OCP2 2nd level overcurrent threshold -0.80 -0.75 -0.70 V VCS_ZCD Zero current threshold -15 -10 -5 mV L4985
Symbol Parameter Test Condition Min. Typ. Max. Unit CURRENT SENSE DISCONNECTION VCSD Current sense disconnection threshold Voltage rising 165 200 235 mV TCSD_DB Disconnection debounce time 8 10 12 µs EQUIVALENT MULTIPLIER KM Equivalent multiplier gain VHVPK < 200 V(1) 0.405 0.44 0.475 V/V VHVPK > 235 V(1) 0.092 0.10 0.108 V/V THD CCM-OPTIMIZER KCCM 0.51 0.55 0.59 H FEEDBACK FAILURE PROTECTION/EXTERNAL BURST MODE (EBM) VFB_FF/EBM Feedback failure protection (on FB) / External burst mode threshold Voltage falling(1) 460 500 540 mV Hysteresis 50 mV TFF/EBM_DB FFP/EBM debounce time 1.25 1.8 2.35 µs IFB_EBM FB current during EBM VFB < VFB_FF/EBM 70 100 135 µA FB current at exit EBM VFB_FF/EBM < VFB < VREF 0.75 1 1.25 mA SWITCHING FREQUENCY FSW Switching frequency (L4985A) TON = 9µs, VHVPK < 200 V 60 65 71 kHz TON = 3µs, VHVPK > 235 V Switching frequency (L4985B) TON = 4.5µs, VHVPK < 200 V 120 130 142 kHz TON = 1.5µs, VHVPK > 235 V MAXIMUM ON-TIME TON_MAX Maximum on-time L4985A 32 40 50 µs L4985B 16 20 26 µs MINIMUM OFF-TIME TOFF_MIN Minimum off-time L4985A 0.75 1.0 1.35 µs L4985B 0.35 0.5 0.75 µs GATE DRIVER VOL Output low voltage Isink = 200 mA 0.7 V Isink = 5 mA 0.02 V VOH Output high voltage 15V<VCC<24.5 V, Isource = 5 mA 11 12 13 V VCC = 9 V, Isource = 5 mA 7.85 V Isrcpk Peak source current -0.7 A Isnkpk Peak sink current 1.5 A tf Voltage fall time VGD from 8 V to 1 V 3 7 15 ns tr Voltage rise time VGD from 1 V to 8 V 5 10 15 ns UVLO saturation VCC = 0 V to VCC_ON, Isink = 1 mA 1.1 V 1. Parameters tracking each other. 2. The VCC pin is self-limited by an internal clamp when the device is in switching modality. 3. Equivalent to just before burst-mode condition. 4. Equivalent to full-load condition. L4985
5 Application information
5.1 Theory of operation
The L4985A/B implements a conventional peak current mode control, based on fixed-off-time (FOT) control technique, with some proprietary circuitries that permit to ideally achieve the same performance of the more complex/expensive average current mode control. Referring to Figure 4, the power switch on-time (TON) is programmed by the output voltage control loop comparing the current sense signal VCS with the internal current reference VCS_REF in order to keep the VOUT regulation; whereas the power switch off-time (TOFF) is programmed by the “OFF-TIME modulator” circuitry in order to keep quasi-fixed the switching frequency FSW in all operating conditions (see “Section 5.1 OFF-time modulator” section for more details). Figure 4. Control loop connections rectification operated by the input bridge) is the instantaneous line input voltage. in a standard current-mode PFC, but without using the standard multiplier block and without the AC line sensing.
Application information
DS13769 - Rev 3 page 10/27
where K M = K 1 K 2 is the equivalent multiplier gain (see Electrical characteristics table for details). CCM optimizer” in order to achieve sinusoidal input current in CCM operation. external RTHD_CCM resistor that is subtracted to the inductor current sense voltage R S I L θ .
2 K C C M Δ I L θ
LP is the inductor value, ∆IL(θ) is the inductor current ripple, KCCM (0.55 typ.) is the circuitry gain. Figure 5. Left key waveforms of the circuit in figure Figure 6. Right key waveforms of the circuit in
Now considering that the input current IIN(θ) of the converter is the average value of the inductor current in a switching cycle results: Equation 5 (5) I I N θ C C M = I L , PK θ − Δ I L θ Selecting the THD-CCM optimizer resistor equal to: Equation 6 (6) R THD _ C C M = K C C M R S L P and replacing equations #2 and #4 in equation #3, after some calculations the inductor peak current results: Equation 7 (7) I L , P K θ = 1 R S K M V O UT V C V I N θ + Δ I L θ Finally replacing equation #7 in equation #5, the input current of the converter results: Equation 8 (8) I I N θ C C M = 1 R S K M V O U T V C V I N θ which is sinusoidal and in phase with the VIN(θ) input voltage (ideally zero-THD and unity-PF) Considering the DCM operation (TR>0), through geometrical consideration, the input current IIN(θ) of the converter can be expressed by: Equation 9 (9) I I N θ D CM = 1
2 I L , PK θ
T ON θ + T FW θ T ON θ + T FW θ + T R θ Equation 9 shows that the term TR>0 introduces distortion if IL,PK(θ) has a sinusoidal shape like in a standard PFC. Referring to Figure 4, the sinusoidal voltage V G θ = V C K 1 V I N θ V OU T is then opportunely shaped by the “THD-DCM” optimizer block, which generates the current reference voltage expressed by: Equation 10 (10) V CS _ RE F θ DC M = V G θ T ON θ + T F W θ + T R θ T ON θ + T F W θ Replacing equation #1 in equation #10, and considering that in DCM operation the peak of the inductor current is I L , P K θ = Δ I L θ , after some calculations results: Equation 11 (11) I I N θ D CM = 1 R S K M V OU T V C V I N θ which is sinusoidal and in phase with the VIN(θ) input voltage (ideally zero-THD and unity-PF), and it has the same gain like in CCM operation.
5.2 OFF-time modulator
The device embeds a novel OFF-time modulator which is able to achieve quasi-fixed switching frequency in all operating conditions (CCM and DCM operation) and independent from the input/output voltage, the load conditions and the converter’s parasitic as the existing modulators. L4985 OFF-time modulator DS13769 - Rev 3 page 12/27
Figure 7. OFF-time modulator - details external power switch is turned on (Q signal goes high). Figure 8. Left OFF-time modulator timing – Line Figure 9. Right OFF-time modulator timing –
5.3 High voltage startup
Figure 10, in order to supply the IC during the initial start-up phase before the self-supply winding is operating.
Figure 10. Embedded high voltage start-up circuitry 1 mA typical till the VCC pin voltage is lower than VCC_SO (1 V typ.). and restart the operations performing the soft-start.
5.4 Input line discharge (X-cap discharge function)
discharge the X capacitors of the EMI filter to a safe level. regulation maximum discharging time.
5.5 Soft-start
to VCS_OCP1 (-0.49 V typ.) in TSS_OCP1 time (130 ms typ.), as shown in Figure 11 .
Figure 11. Soft-start circuitry details
5.6 No load operation (burst-mode function)
and in tracking with the threshold VCOMP_S) the device restarts the switching activity. ON-time and the system stoppage takes place after GD falling edge. voltage VCC_ON and restart the operation performing the soft-start.
5.7 Idle operation (external burst-mode function)
without implementing the soft-start, as soon as the FB voltage exceeds the VFB_FF/EBM threshold by 50 mV typ. the EBM function, the suggested value of the FB filter capacitor CFB is 3.3 nF.
Figure 12. External Burst-Mode (EBM) function – circuit details threshold the internal HV-startup is turned on to bring VCC voltage to the turn-on threshold VCC_ON. Figure 13. External Burst-Mode (EBM) function – timing
5.8 Disable operation (DISABLE function)
compensation network connected between COMP pin and ground and the COMP voltage starts to increase. implementing the soft-start .
Figure 14. DISABLE function – circuit details HV-startup is intermittently turned on to keep the device supplied between VCC_OFF and VCC_ON. Figure 15. DISABLE function – timing
5.9 Protections
adding extra components and/or circuitry.
5.9.1 AC brown-in (BI function)
detected the internal HV-startup is turned on to bring VCC voltage to the turn-on threshold VCC_ON. de-bounce time is increased to 40 ms.
5.9.2 AC brownout (BO function)
parameter in Table 5. Electrical characteristics), the switching activity is stopped.
5.9.3 Output overvoltage (OVP function)
the error amplifier (VREF = 2.5 V). until it gets back close to it (VFB < VFB_R). De-bounce time TDOVP_DB (50 µs typ.) is provided to avoid false activation of the protection. Figure 16. OVP timing
5.9.4 Overcurrent (OCP1 function)
way, the peak inductor current is limited to a maximum of 0.49/RS.
5.9.5 Inductor saturation detection (OCP2 function)
that immediately stops the converter activity until the current level reaches the zero-current threshold (VCS_ZCD). Figure 17. OCP2 timing
5.9.6 Feedback failure detection
- if the FB pin voltage is lower than the internal V FB_FF/EBM threshold (0.5 V typ.) a failure of the output divider resistor is assumed (e.g. RFB_H resistor not mounted), then the device stops the switching activity and reduces its consumption. – De-bounce time T FF/EBM_DB (1.8 µs typ.) is provided to avoid false triggering.
- if the CS pin voltage is higher than the internal V CSD threshold (200 mV typ.) a failure of the current sensing resistors is assumed (e.g. RTHD_CCM resistor not mounted and/or RS resistor burned), then the device stops the switching activity and reduces its consumption. A recycle of VCC between the turn-off threshold (VCC_OFF) and the turn-on threshold (V.) is needed to restart the converter. – De-bounce time T CSD_DB (10 µs typ.) is provided to avoid false triggering.
5.10 Line feedforward
6 Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark.
6.1 SO-8 package information
Figure 18. SO-8 package dimensions Table 6. SO-8 mechanical data
- Dimensions D does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed
0.15 mm (.006 inch) in total (both side).
Package information
DS13769 - Rev 3 page 20/27
7 Ordering information
Table 7. Order codes
Ordering information
DS13769 - Rev 3 page 21/27
Revision history
Table 8. Document revision history 16-Jul-2021 1 Initial release.