L4877A-E

MAX3540 MAXIM | Alldatasheet

Document overview

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Technical content

Features

♦ Low Power Consumption: 760mW (typ) from a +3.3V Supply Voltage ♦ Integrated Tracking Filters ♦ ATSC A/74 Compliant ♦ 40dB Adjacent Channel Protection Ratio (ACPR) ♦ 4.4dB (typ) Low Noise Figure ♦ Small, 7mm x 7mm, fcLGA Leadless Package ♦ 256-QAM-Compatible Phase-Noise Performance ♦ IF Overload Detector Controls RF Variable-Gain Amplifier ♦ 2-Wire I2C-Compatible Serial Control Interface MAX3540 Complete Single-Conversion Television Tuner GND GND GND GND GND VCC GND IFOUT2- GND GND GND GND IFOVLD VCC GND IFOUT1- IFOUT1+ IFIN+ IFIN- IFAGC IFOUT2+ VCC GND LEXT RFGND3 RFAGC VCC GND VCC VREF XTALP VCC CP ADDR2 ADDR1 MUX VCC LDO V CC VTUNE GND_TUNE XTALN GND VHF_IN RFGND2 VCC UHF_IN R - 29 1716 21201918 22 23 24151413 4445 PD CP 40414243 39 38 37464748 SCL SDA MAX3540 VCO DIVIDER EP SERIAL INTERFACE Pin Configuration

Ordering Information

19-0848; Rev 0; 10/07 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. *EP = Exposed paddle. EVALUATION KIT AVAILABLE PART TEMP RANGE PIN- PACKAGE PKG CODE MAX3540ULM#G42 0°C to +85°C 48 fcLGA-EP* L4877A-E

Complete Single-Conversion Television Tuner ABSOLUTE MAXIMUM RATINGS DC ELECTRICAL CHARACTERISTICS (MAX3540 Evaluation Kit, VCC = +3.1V to +3.5V, no RF signals at RF inputs, default register settings, VRFAGC = VIFAGC = +3V (minimum attenuation), TA = 0°C to +85°C, unless otherwise noted. Typical values are at VCC = +3.3V, TA = +25°C, unless otherwise noted.) Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RFIN, IFIN_, IFOUT1_, IFOUT2_, IFAGC, RFAGC, VTUNE, LDO, MUX, CP, XTAL to GND ..-0.3V to (VCC + 0.3V) Continuous Power Dissipation (T A = +70°C) PARAMETER CONDITIONS MIN TYP MAX UNITS SUPPLY VOLTAGE AND CURRENT Supply Voltage +3.1 +3.5 V Receive mode 240 275Supply Current Shutdown mode 5 mA RF and IF AG C Inp ut Bi as C ur r ent At +0.5V and +3V -50 +50 μA Minimum attenuation +3RF and IF AGC Control Voltage (Note 1) Maximum attenuation +0.5 V Digital Input Logic-Level Low 0.3 x VCC V Digital Input Logic-Level High 0.7 x VCC V SERIAL INTERFACE Input Logic-Level Low 0.3 x VCC V Input Logic-Level High 0.7 x VCC V Input Hysteresis 0.05 x VCC V SDA, SCL Input Current -10 +10 μA Output Logic-Level Low 3mA sink current 0.4 V Output Logic-Level High VCC - 0.5 V CAUTION! ESD SENSITIVE DEVICE

Complete Single-Conversion Television Tuner PARAMETER CONDITIONS MIN TYP MAX UNITS RF INPUT TO IFOUT1_ OUTPUT VHF_IN, LPF enabled, INPT = 00 54 100 VHF_IN, LPF disabled, INPT = 01 100 300Operating Frequency Range (See Table 7) UHF_IN, INPT = 10 300 860 MHz Analog channel PIX carrier 45.75Output Frequency Digital channel center frequency 44 MHz Maximum gain, VRFAGC = 3V, 54MHz to 860MHz 34 Maximum gain, VRFAGC = 3V, broadcast channels 28.0 34 45.5Voltage Gain Source impedance = 75Ω, load impedance = 200Ω M i ni m um g ai n, V R FA GC = 0.5V -11 dB VHF_IN 54 300 Operating Frequency Range Gain specification met across these frequency bands UHF_IN 300 860 MHz Input Return Loss Worst case, selected channel 8 dB Noise Figure Maximum gain, V RFVGC = 3V (Note 1) 4.4 dB Maximum gain, VRFVGC = 3V 15Input IP2 (In-Band and Out-of-Band Tones) At 12.5dB of gain 29 dBm Maximum gain, VRFVGC = 3V -13Input IP3 (In-Band and Out-of-Band Tones) At 12.5dB of gain 5 11 dBm Maximum gain, VRFVGC = 3V -24.5 Input P1dB At 12.5dB of gain, CW tone at fC - 36MHz, tested at Ch 69 in UHF band -3 dBm Beats Within Output 0dBmV PIX carrier level (Note 1) -60 dBc VHF_IN from 150MHz to 960MHz -60 VHF_IN from 960MHz to 1400MHz -40Beats, Converted to Output UHF_IN from 600MHz to 1400MHz -40 dBc Gain Flatness 54MHz to 60MHz 1.5 dB P-P Isolation 5MHz to 50MHz, RF input to IF output, relative to desired channel 60 dBc Port-to-Port Isolation Isolation between RF input ports at 215MHz 30 dB 54MHz to 860MHz 70 Image Rejection Measured at 91.5MHz above desired channel’s center frequency Broadcast channels, TA = +25°C 66 dBc 5MHz to 65MHz -40Spurious Leakage at RF Input 65MHz to 878MHz -40 dBmV 10kHz offset -85 100kHz offset, 1.5kHz loop bandwidth -105Phase Noise (Single-Sideband) 1MHz offset, 1.5kHz loop bandwidth -125 dBc/Hz Output Return Loss Balanced 50 Ω load 9 dB AC ELECTRICAL CHARACTERISTICS (MAX3540 Evaluation Kit, VCC = +3.1V to +3.5V, 75Ω system impedance, default register settings, VRFAGC = VIFAGC = +3V (minimum attenuation), TA = 0°C to +85°C, unless otherwise noted. Typical values are at VCC = +3.3V, TA = +25°C, unless otherwise noted.)

Complete Single-Conversion Television Tuner AC ELECTRICAL CHARACTERISTICS (continued) (MAX3540 Evaluation Kit, VCC = +3.1V to +3.5V, 75Ω system impedance, default register settings, VRFAGC = VIFAGC = +3V (minimum attenuation), TA = 0°C to +85°C, unless otherwise noted. Typical values are at VCC = +3.3V, TA = +25°C, unless otherwise noted.) PARAMETER CONDITIONS MIN TYP MAX UNITS IF VARIABLE-GAIN AMPLIFIER Input Impedance Balanced 2000 Ω Output Impedance Balanced (Note 1) 300 Ω Maximum gain setting, VIFAGC = 3V 54 56 65 Passband Voltage Gain S our ce l oad = 300Ω , outp ut l oad = 300Ω Minimum gain setting, VIFAGC = 0.5V 21 dB Passband Gain Flatness 40MHz to 48MHz (Note 1) 1.2 dB Output Voltage V IFAGC = 3V (Note 1) 2 V P-P AGC Gain Slope V IFAGC = 3V to 0.5V (Note 1) 30 dB/V Equivalent Input Voltage Noise Density At 44MHz, maximum gain, VIFAGC = 3V (Note 1) 7.3 nV/ √Hz Noise Figure Change vs. Attenuation < 0.35 dB/dB IM3 V OUT = 1.5VP-P, 40dB < gain < 60dB (Note 1) -54 dBc IF OVERLOAD DETECTOR (see the IF Overload Detector section) Output Overload Attack Point 0.7 V P-P Attack-Point Accuracy ±1 dB Detector Output Voltage Range Negative polarity, overload reduces VDET (open collector, 0.3mA sink) 0.5 3.0 V Detector Gain 70 V/V FREQUENCY SYNTHESIZER REFERENCE OSCILLATOR Frequency 4 MHz DIVIDERS RF N-Divider Ratio 256 32,767 RF R-Divider Ratio 8 127 LO PHASE DETECTOR AND CHARGE PUMP Comparison Frequency 31.50 250.00 kHz CP = 00 0.5 CP = 01 1 CP = 10 1.5Charge-Pump Current CP = 11 2 mA C har g e- P um p Thr ee- S tate C ur r ent ±5 nA Charge-Pump Current Matching 5% LOCAL OSCILLATOR (OSCILLATOR WITH NARROW BAND LOOP) VCO Tuning Range Tank frequency 2160 4400 MHz VCO Tuning Gain Tank oscillator gain 500 MHz/V 2-WIRE SERIAL INTERFACE Clock Frequency 400 kHz Note 1: Guaranteed by design and characterization.

1 SCL 2-Wire Serial-Clock Interface. Requires a pullup resistor to V CC. 2 SDA 2-Wire Serial-Data Interface. Requires a pullup resistor to V CC. 3, 10, 23, 28, 32, 33, 37, 41, 44 VCC Power-Supply Connections. Bypass each supply pin to ground with a 1000pF capacitor. 4 UHF_IN UHF RF Input. Matched to 75 Ω over the operating band. Requires a DC-blocking capacitor. 5 VHF_IN VHF RF Input. Matched to 75 Ω over the operating band. Requires a DC-blocking capacitor. 6 RFGND2 RF Ground. Bypass to the PCB’s ground plane with a 1000pF capacitor. Do not connect RFGND2 and RFGND3 together. 7 LEXT RF VGA Supply Voltage. Connect through a 270nH pullup inductor to V CC. 8 RFGND3 RF Ground. Bypass to the PCB’s ground plane with a 1000pF capacitor. Do not connect RFGND2 and RFGND3 together. 9R F A G C R F A G C G ai n- C ontr ol V ol tag e. Accep ts a D C vol tag e fr om 0.5V ( m i ni m um g ai n) to 3V ( m axi m um g ai n) . 11–22, 27, 31 GND Ground. Connect to the PCB’s ground plane. 24 IFOUT2- Inver ti ng IF- V G A Outp ut. C onnect to the i np ut of an anti - al i asi ng fi l ter . Req ui r es a D C - b l ocki ng cap aci tor . 25 IFOUT2+ Noninverting IF-VGA Output. Connect to the input of an anti-aliasing filter. Requires a DC-blocking capacitor. 26 IFAGC IF AGC Gain-Control Voltage. Accepts a DC voltage from 0.5V (minimum gain) to 3V (maximum gain). 29 IFIN- Inverting IF-VGA Input. Connect to the output of an IF-SAW filter. 30 IFIN+ Noninverting IF-VGA Input. Connect to the output of an IF-SAW filter. 34 IFOVLD IF Power Detector Open-Collector Output. Requires a 10k Ω pullup resistor to VCC. 35 IFOUT1+ N oni nver ti ng IF- LN A Outp ut. Req ui r es a D C - b l ocki ng cap aci tor . 36 IFOUT1- Inverting IF-LNA Output. Requires a DC-blocking capacitor. 38 LDO VCO LDO Bypass. Bypass to ground with a 0.47μF capacitor. 39 GND_TUNE VTUNE Ground Connection. Connect to the PCB ground plane. All loop filter component GND must be connected to this pin (see the Typical Application Circuit). 40 VTUNE VCO Tuning Input. Connect to the PLL loop filter output. 42 MUX Test Output. Leave this pin unconnected during normal operation. 43 CP Charge-Pump Output. Connect to the PLL loop filter input. 45 XTALN Crystal Oscillator Feedback. See the Typical Application Circuit. 46 XTALP Crystal Input. Requires a DC-blocking capacitor. 47 ADDR1 2-Wire Serial-Interface Address Line 1. This pin along with ADDR2 sets the device address for the I2C-compatible serial interface. 48 ADDR2 2-Wire Serial-Interface Address Line 2. This pin along with ADDR1 sets the device address for the I2C-compatible serial interface. EP EP Exposed Paddle. Solder evenly to the PCB ground plane for proper operation. Complete Single-Conversion Television Tuner

a status register and a ROM table data register. lier than 100μs after power-up. Table 1. Register Configuration RESERVED 7 0 Must be set to 0. integer divider value is N = 4688. N can range from 256 to 32,767. Table 2. N-DIV High Register (Address: 0000b)

RESERVED 7 0 Must be set to 0. is R = 64. R can range from 16 to 127. Table 4. R-DIV Register (Address: 0010b) VCO select. Selects one of three possible VCOs. VCO sub-band select. Selects one of eight possible VCO sub-bands. Table 5. VCO Register (Address: 0011b) integer divider value is N = 4688. N can range from 256 to 32,767. Table 3. N-DIV Low Register (Address: 0001b)

RESERVED 7 0 Must be set to 0. IFO V LD [ 2:0] 6, 5, 4 000 Write content of ROM register OD[2:0] to this location. Selects the typical charge-pump current. Selects the tracking filter band of operation. Table 6. RSSI, Charge Pump, and Filter Select Register (Address: 0100b) RESERVED 7–4 0000 Must be set to 0000. Table 7. Control Register (Address: 0101b)

Frequency synthesizer shutdown. RESERVED 2, 1, 0 000 Must be set to 000. Table 8. Shutdown Register (Address: 0110b) TFS[7:0] 7–0 00000000* Programs series capacitor values in the tracking filter. Table 9. Tracking-Filter Series Cap Register (Address: 0111b) ROM table data readback register. Reserved 6 0 Must be set to 0. TFP[5:0] 5–0 000000* Programs parallel capacitor values in the tracking filter. Table 10. Tracking-Filter Parallel Cap Register (Address: 1000b) Reserved 7–4 0000 Must be set to 0000. TFA[3:0] 3–0 0000* Address bits of the ROM register to be read. Table 11. Tracking-Filter ROM Address Register (Address: 1001b) Reserved 7–0 N/A Reserved. Do not program these bits during normal operation. Table 12. Reserved Register (Address: 1010b) *See the RF Tracking Filter section.

resistors (1kΩ or greater) for proper bus operation. SDA and SCL remain high when the bus is not busy. keep it low during the high period of the clock pulse. TFR[7:0] 7–0 00000000* Tracking-filter data bits read from the device’s ROM table. Table 13. ROM Table Data Readback Register (Address: 1011b) VCO tuning voltage indicators. Table 14. Status Register (Address: 1100b) Table 15. MAX3540 Address Configurations *See the RF Tracking Filter section.

ing capacitor. The input registers select the active inputs. 300MHz, select VHF_IN with LPF disabled (INPT = 01). For 300MHz to 860MHz, select UHF_IN (INPT = 10). Gain Control section for more information. TFP[5:0] bits in the Tracking-Filter Parallel Cap register. on how to calculate the required values. Tracking Filter ROM Address register (Table 11). in the ROM Table Data Readback register (Table 13). Table 16. ROM Table

Complete Single-Conversion Television Tuner Interpolating Tracking Filter Coefficients The TFS[7:0] and TFP[5:0] bits must be reprogrammed for each channel frequency to optimize performance. The optimal settings for each channel can be calculated from the ROM table data using the equations below. VHF LO filter: VHF High filter: UHF filter: Where: f RF = operating frequency in MHz TFS = decimal value of the optimal TFS[7:0] setting (Table 9) for the given operating frequency TFP = decimal value of the optimal TFP[5:0] setting (Table 10) for the given operating frequency LS0, LS1, LP0, LP1, HS0, HS1, HP0, HP1, US0, US1, UP0, and UP1 = the decimal values of the ROM table coefficients (Table 16). IF Overload Detector The MAX3541 includes a broadband IF overload detec- tor, which provides an indication of the total power pre- sent at the RF input. The overload-detector output voltage is compared to a reference voltage and the dif- ference is amplified. This error signal drives an open- collector transistor whose collector is connected to the IFOVLD pin, causing the IFOVLD pin to sink current. The nominal full-scale current sunk by the IFOVLD pin is 300μA. The IFOVLD pin requires a 10kΩ pullup resis- tor to V CC. The IF overload detector is calibrated at the factory to attack at 0.6VP-P at IFOUT1. Upon power-up, the base- band processor must read OD[2:0] from the ROM table and store it in the IFVOLD register. Closed-Loop RF Gain Control Closed-loop RF gain control can be implemented by connecting the IFOVLD output to the RFAGC input. Using a 10k Ω pullup resistor on the IFOVLD pin, as shown in the Typical Application Circuit , results in a nominal 0.5V to 3V control voltage range. VCO and VCO Divider Selection The MAX3540 frequency synthesizer includes three VCOs and eight VCO sub-bands to guarantee a 2160MHz to 4400MHz VCO frequency range. The frequency synthesiz- er also features an additional VCO frequency divider, which must be programmed to either 4, 8, 16, or 32 through the VDIV[1:0] bits in the VCO register based on the channel being received. Table 5 describes how the VDIV[1:0] bits should be programmed for each band of operation. To ensure PLL, lock the proper VCO and VCO sub-band for the channel being received, which must be chosen by iteratively selecting a VCO and VCO sub-band then read- ing the LD[2:0] bits to determine if the PLL is locked. Any reading from 001 to 110 indicates the PLL is locked. If LD[2:0] reads 000, the PLL is unlocked and the selected VCO is at the bottom of its tuning range; a lower VCO sub- band must be selected. If LD[2:0] reads 111, the PLL is unlocked and the selected VCO is at the top of its tuning range; a higher VCO sub-band must be selected. The VCO and VCO sub-bandsettings should be progressively increased or decreased until the LD[2:0] reading falls in the 001 to 110 range. Due to overlap between VCO sub-band frequencies, it is possible that multiple VCO settings can be used to tune to the same channel frequency. System performance at a given channel should be similar between the various pos- sible VCO settings, so it is sufficient to select the first VCO and VCO sub-band that provides lock. Layout Considerations The MAX3540 EV kit can serve as a guide for PCB layout. Keep RF signal lines as short as possible to minimize losses and radiation. Use controlled impedance on all high-frequency traces. The exposed paddle must be sol- dered evenly to the board’s ground plane for proper operation. Use abundant vias beneath the exposed pad- dle for maximum heat dissipation. Use abundant ground vias between RF traces to minimize undesired coupling. TFP INT 10 [(1.6 UP0 256 0.8) UP1 +× + − + (. 14 0.8 ) f 10 ]RF ×× ×⎡ TFS INT 10 [(3 US0 256 ) US1 0.8 ) TFP INT 10 [(1.6 HP0 0.8) HP1 16= ××⎡ TFS INT 10 [(2.8 HS0 0.8) HS1 0.8) f1 0 ]RF TFP INT 10 [(1.6 LP0 0.4) LP1 -3××⎡ TFS 10 (2.4 LS0 0.6) LS1

Complete Single-Conversion Television Tuner GND GND GND GND GND VCC GND IFOUT2- GND GND GND GND IFOVLD VCC GND IFOUT1- *CONNECT TO COMMON GROUND POINT AT PIN 39. IFOUT1+ IFIN+ IFIN- IFAGC IFOUT2+ VCC GND LEXT RFGND3 RFAGC VCC GND VCC VREF XTALP VCC CP ADDR2 ADDR1 MUX VCC LDO VCC VTUNE GND_TUNE XTALN GND VHF_IN RFGND2 VCC UHF_IN R 1716 21201918 22 23 24151413 4445 PD CP 40414243 39 38 37464748 SCL SDA MAX3540 VCO DIVIDER EP SERIAL INTERFACE 100pF 22pF 1000pF 1000pF 470nF 2.7kΩ VIFAGC IFOUT+ IFOVLD IFOUT- 270Ω 2.7Ω 100Ω IFOVLD SDATA SCLK ADDRESS2 ADDRESS1 1.3kΩ 2.7kΩ2.7kΩ 10kΩ 0.033μF 2.2pF 470pF 100pF 1000pF VCC 1000pF VCC VCC 0.1μF 1000pF VCC VCC VCC 1000pF VCC 1000pF 1000pF 47μF 4700pF VCC VCC 1000pF 0.1μF 1000pF 0.1μF VCC 1000pF VCC VCC 1000pF ANTI-ALIASING FILTER 680nH 1000pF 1000pF IF-SAW FILTER SAW DRIVER AMPLIFIER Typical Application Circuit To minimize coupling between different sections of the IC, the ideal power-supply layout is a star configura- tion, which has a large decoupling capacitor at the central V CC node. The VCC traces branch out from this node, with each trace going to separate V CC pins of the MAX3540. Each V CC pin must have a bypass capacitor with a low impedance to ground at the fre- quency of interest. Do not share ground vias among multiple connections to the PCB ground plane.

Complete Single-Conversion Television Tuner

Package Information

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline info rmation go to www.maxim-ic.com/packages.) 48L LGA.EPS

Complete Single-Conversion Television Tuner Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circu it patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 16 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2007 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc. Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline info rmation go to www.maxim-ic.com/packages.)