L2G2IS STMICROELECTRONICS | Alldatasheet
Document overview
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- PDF pages: 26
Technical content
Datasheet sections
- 1 Block diagram and pin description
- 1.1 System block diagram
- 1.2 Pin description
- 2 Terminology & functionality
- 2.1 Sensitivity
- 2.2 Zero-rate level
- 2.3 Data-ready interrupt and synchronous reading
- 2.4 Temperature sensor
- 3 Mechanical and electrical characteristics
- 3.1 Mechanical characteristics
- 3.2 Electrical characteristics
- 3.3 Temperature sensor characteristics
- 3.4 SPI - serial peripheral interface
- 3.5 Absolute maximum ratings
- 4 Application hints
- 5 Digital interfaces
- 5.1 SPI bus interface
- 5.1.1 SPI read
- 5.1.2 SPI write
- 5.1.3 SPI read in 3-wire mode
- 6 Output register mapping
- 7 Register description
- 7.1 WHO_AM_I (00h)
- 7.2 TEMP_OUT_L (01h), TEMP_OUT_H (02h)
- 7.3 OUT_X_L (03h), OUT_X_H (04h)
- 7.4 OUT_Y_L (05h), OUT_Y_H (06h)
- 7.5 STATUS_REG (09h)
Features
±100 dps / ±200 dps full-scale range Wide supply voltage range: 1.71 V to 3.6 V Low-voltage compatible IOs 3- and 4-wire SPI digital interface Embedded temperature sensor Embedded self-test Integrated low- and high-pass filters with user- selectable bandwidth Power-down and sleep modes for smart power saving ECOPACK®, RoHS and “Green” compliant
Applications
Optical image stabilization
Description
The L2G2IS is a two-axis MEMS gyroscope for optical image stabilization applications. It includes a sensing element and an IC interface capable of providing the measured angular rate to the application through an SPI digital interface. The unique sensing element is manufactured using a dedicated micromachining process developed by STMicroelectronics to produce inertial sensors and actuators on silicon wafers. The IC interface is manufactured using a CMOS process that allows a high level of integration to design a dedicated circuit which is trimmed to better match the characteristics of the sensing element. The L2G2IS is available in a plastic land grid array (LGA) package and can operate over a temperature range of -40 °C to +85 °C. /*$ [[PP Table 1. Device summary
1 Block diagram and pin description
1.1 System block diagram
Figure 1. Block diagram
1.2 Pin description
Figure 2. Pin connections
- Leave pin electrically unconnected and soldered to PCB.
Table 2. Pin description
1 Vdd_IO Power supply for I/O pins
2 SCL Clock line for SPI interface
3 SDI/SDO Serial data input (SDI)
4 SDO Serial data output (SDO)
5 CS Chip-select line
6 DRDY Data ready signal
7 Res
- Leave pin electrically unconnected and soldered to PCB.
8 Res Connect to GND
9 Res Connect to GND
10 Res Connect to GND
11 Res Connect to GND
12 GND 0 V power supply
13 Res Connect to GND
14 Cap Capacitance connection pin for internal charge pump
15 Reg Capacitance connection pin for internal regulator
16 Vdd Power supply
Terminology & functionality L2G2IS
2 Terminology & functionality
2.1 Sensitivity
An angular rate gyroscope is a device that produces a positive-going digital output for counterclockwise rotation around the sensitive axis considered. Sensitivity describes the gain of the sensor and can be determined by applying a defined angular velocity to it. This value changes very little over temperature and time.
2.2 Zero-rate level
The zero-rate level describes the actual output signal if there is no angular rate present. The zero-rate level of highly accurate MEMS sensors is, to some extent, a result of stress to the sensor and therefore the zero-rate level can slightly change after mounting the sensor on a printed circuit board or after exposing it to extensive mechanical stress. This value changes very little over temperature and time.
2.3 Data-ready interrupt and synchronous reading
On the L2G2IS the angular rate data can be retrieved using a synchronous read. To perform a synchronous read, CTRL_REG3 (0Dh) (DRDY_EN) has to be set to '1' in order to enable the data-ready interrupt on the DRDY pin (refer to Figure 4). To properly perform a synchronous read, the angular rate data have to be read every time the DRDY pin goes high. The DRDY signal can be latched (default condition) or pulsed if the CTRL_REG1 (0Bh) (P_DRDY) is set to ‘1’. When a latched condition is selected, the interrupt goes low when the high part of one of the output channels is read (OUT_X_H (04h) or OUT_Y_H (06h)) and returns high when new data is generated. When a pulsed condition is selected, the interrupt behavior is independent from the reading operations and remains high for 75 μsec every time new data is generated. The DRDY pin is set by default as push-pull output, but it can be configured as open-drain output by setting CTRL_REG3 (0Dh) (PP_OD) to ‘1’.
2.4 Temperature sensor
The temperature data can be retrieved from the TEMP_OUT_L (01h), TEMP_OUT_H (02h) register, as two’s complement data in 12-bit format left-justified. The output of the temperature sensor is 0 at 25 °C.
3 Mechanical and electrical characteristics
3.1 Mechanical characteristics
Vdd = 2.4 V and T = 25 °C unless otherwise noted(a). a. The product is factory calibrated at 2.4 V. The operational power supply range is specified in Table 4. Table 3. Mechanical characteristics
- Typical specifications are not guaranteed.
- Refer to Figure 9: LPF chain block diagram and Table 24: Low-pass filter cutoff frequency selection.
3.2 Electrical characteristics
@ Vdd = 2.4 V, T = 25 °C unless otherwise noted(b). b. The product is factory calibrated at 2.4 V. Table 4. Electrical characteristics
- Typical specifications are not guaranteed.
- It is possible to remove Vdd maintaining Vdd_IO without blocking the communication busses, in this condition the
measurement chain is powered off.
- Sleep mode introduces a faster turn-on time relative to power-down mode.
3.3 Temperature sensor characteristics
@ AVdd = 2.4 V, T = 25 °C unless otherwise noted(c). c. The product is factory calibrated at 2.4 V. Table 5. Temperature sensor characteristics
- Typical specifications are not guaranteed.
- The output of the temperature sensor is 0 at 25 °C. Refer to Section 2.4: Temperature sensor on how to read the
temperature sensor output data.
3.4 SPI - serial peripheral interface
Subject to general operating conditions for Vdd and Top. Figure 3. SPI slave timing diagram Table 6. SPI slave timing values
- Values are guaranteed at 10 MHz clock frequency for SPI, based on characterization results, not tested in production.
3.5 Absolute maximum ratings
Note: Supply voltage on any pin should never exceed 4.8 V. Table 7. Absolute maximum ratings permanent damage to the part. cause permanent damage to the part.
4 Application hints
Figure 4. L2G2IS electrical connections and external components
- Leave pin electrically unconnected and soldered to PCB.
to the device (common design practice). Table 8. External component values
- This value must guarantee a minimum of 1 nF value under 12 V bias condition.
5 Digital interfaces
5.1 SPI bus interface
The SPI is a bus slave. The SPI allows to write and read the registers of the device. The serial interface connects to applications using 4 wires: CS, SCL, SDI and SDO. falling edge of SCL and should be captured at the rising edge of SCL. from the device is read. In latter case, the chip will drive SDO at the start of bit 8. bit 1-7: address AD(6:0). This is the address field of the indexed register. bit 8-15: data DI(7:0) (write mode). This is the data that is written into the device (MSb first). bit 8-15: data DO(7:0) (read mode). This is the data that is read from the device (MSb first). The function and the behavior of SDI and SDO remain unchanged. Table 9. Serial interface pin description
5.1.1 SPI read
Figure 5. SPI read protocol bit 0: READ bit. The value is 1. bit 2-7: address AD(5:0). This is the address field of the indexed register. A multiple read command is also available.
5.1.2 SPI write
Figure 6. SPI write protocol is performed by adding blocks of 8 clock pulses to the previous one. bit 0: WRITE bit. The value is 0. bit 2 -7: address AD(5:0). This is the address field of the indexed register.
Figure 7. Multiple byte SPI write protocol (2-byte example)
5.1.3 SPI read in 3-wire mode
Figure 8. SPI read protocol in 3-wire mode bit 0: READ bit. The value is 1. bit 2-7: address AD(5:0). This is the address field of the indexed register. A multiple read command is also available in 3-wire mode.
6 Output register mapping
permanent damage to the device. table must not be accessed and the content stored in those registers must not be changed. Table 10. Register address map
7 Register description
write the data through the serial interface.
7.1 WHO_AM_I (00h)
7.2 TEMP_OUT_L (01h), TEMP_OUT_H (02h)
7.3 OUT_X_L (03h), OUT_X_H (04h)
X-axis angular rate data. The value is expressed as two’s complement.
7.4 OUT_Y_L (05h), OUT_Y_H (06h)
Y-axis angular rate data. The value is expressed as two’s complement.
7.5 STATUS_REG (09h)
Table 11. WHO_AM_I register Table 12. TEMP_OUT_L register Table 13. TEMP_OUT_H register Table 14. TEMP_OUT resolution Temp11-Temp0 Temperature data. Table 15. STATUS_REG register
7.6 CTRL_REG1 (0Bh)
Table 16. STATUS_REG description YXDA X-, Y-axis new data available. XDA X-axis new data available. YDA Y-axis new data available. Table 17. CTRL_REG1 register
- This bit must be set to ‘0’ for proper operation of the device.
Table 18. CTRL_REG1 description
- Boot request is executed as soon as internal oscillator is turned-on. It is possible to set this bit while in
power-down mode, in this case it will be served at the next normal mode or sleep mode. (0: 4-wire interface; 1: 3-wire interface). Refer to Table 19: Operating mode selection.
7.7 CTRL_REG2 (0Ch)
7.8 CTRL_REG3 (0Dh)
Table 19. Operating mode selection Table 20. CTRL_REG2 register
- These bits must be set to ‘0’ for proper operation of the device.
Table 21. CTRL_REG2 description (0: 2nd order; 1: 1st order). (1: all the configuration register values are restored to default values). Table 22. CTRL_REG3 register
- These bits must be set to ‘0’ for proper operation of the device.
Table 23. CTRL_REG3 description (1: DRDY on pin). Section 2.3: Data-ready interrupt and synchronous reading. (0: digital low-pass filter disabled; 1: digital low-pass filter enabled).
Figure 9. LPF chain block diagram
7.9 ORIENT_CONFIG (10h)
7.10 OFF_X (11h)
Table 24. Low-pass filter cutoff frequency selection Table 25. ORIENT_CONFIG register
- These bits must be set to ‘0’ for proper operation of the device.
Table 26. ORIENT_CONFIG description Table 27. OFF_X register Table 28. OFF_X description The value is expressed as two’s complement.
7.11 OFF_Y(12h)
7.12 CTRL_REG4 (1Fh)
Table 29. OFF_Y register Table 30. OFF_Y description The value is expressed as two’s complement. Table 31. CTRL_REG4 register
- These bits must be set to ‘0’ for proper operation of the device.
Table 32. CTRL_REG4 description Table 33. High-pass filter cutoff frequency selection
8 Package information
specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark.
8.1 Soldering information
The LGA package is compliant with the ECOPACK®, RoHS and “Green” standard. It is qualified for soldering heat resistance according to JEDEC J-STD-020. Leave “Pin 1 Indicator” unconnected during soldering. Land pattern and soldering recommendations are available at www.st.com/mems.
8.2 LGA-16 package
Figure 10. LGA-16 package outline and dimensions Table 34. LGA-16 package outer dimensions
9 Revision history
Table 35. Document revision history