L123ATQ

SN74LV123A-Q1 TI | Alldatasheet

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/C0083/C0078/C0055/C0052/C0076/C0086/C0049/C0050/C0051/C0065/C0262/C0081/C0049 /C0068/C0085/C0065/C0076 /C0082/C0069/C0084/C0082/C0073/C0071/C0071/C0069/C0082/C0065/C0066/C0076/C0069 /C0077/C0079/C0078/C0079/C0083/C0084/C0065/C0066/C0076/C0069 /C0077/C0085/C0076/C0084/C0073/C0086/C0073/C0066/C0082/C0065/C0084/C0079/C0082 /C0087/C0073/C0084/C0072 /C0083/C0067/C0072/C0077/C0073/C0084/C0084/C0262/C0084/C0082/C0073/C0071/C0071/C0069/C0082 /C0073/C0078/C0080/C0085/C0084/C0083 SCLS467B − FEBRUARY 2003 − REVISED MAY 2004 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C0068Qualification in Accordance With AEC-Q100 † /C0068Qualified for Automotive Applications /C0068Customer-Specific Configuration Control Can Be Supported Along With Major-Change Approval /C0068Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C /C0068Typical VOHV (Output VOH Undershoot) >2.3 V at VCC = 3.3 V, TA = 25°C /C0068Supports Mixed-Mode Voltage Operation on All Ports /C0068Schmitt-Trigger Circuitry on A, B, and CLR Inputs for Slow Input Transition Rates /C0068Edge Triggered From Active-High or Active-Low Gated Logic Inputs /C0068Ioff Supports Partial-Power-Down Mode Operation /C0068Retriggerable for Very Long Output Pulses, Up To 100% Duty Cycle /C0068Overriding Clear Terminates Output Pulse /C0068Glitch-Free Power-Up Reset on Outputs /C0068ESD Protection Exceeds JESD 22 − 2000-V Human-Body Model (A114-A) − 200-V Machine Model (A115-A) − 1000-V Charged-Device Model (C101) † Contact factory for details. Q100 qualification data available on request. description/ordering information The SN74LV123A is a dual retriggerable monostable multivibrator designed for 2-V to 5.5-V VCC operation. This edge-triggered multivibrator features output pulse-duration control by three methods. In the first method, the A input is low, and the B input goes high. In the second method, the B input is high, and the A input goes low. In the third method, the A input is low, the B input is high, and the clear (CLR) input goes high. The output pulse duration is programmable by selecting external resistance and capacitance values. The external timing capacitor must be connected between Cext and Rext/Cext (positive) and an external resistor connected between Rext/Cext and VCC . To obtain variable pulse durations, connect an external variable resistance between Rext/Cext and VCC . The output pulse duration also can be reduced by taking CLR low.

ORDERING INFORMATION

TA PACKAGE ‡ ORDERABLE PART NUMBER TOP-SIDE MARKING −40°C to 105°C TSSOP − PW Tape and reel SN74LV123ATPWRQ1 L123ATQ ‡ Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Copyright  2004, Texas Instruments Incorporated Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PW PACKAGE (TOP VIEW) 1CLR 2C ext 2R ext/Cext GND VCC 1R ext/Cext 1C ext 2CLR /C0080/C0082/C0079/C0068/C0085/C0067/C0084/C0073/C0079/C0078 /C0068/C0065/C0084/C0065 /C0105/C0110/C0102/C0111/C0114/C0109/C0097/C0116/C0105/C0111/C0110 /C0105/C0115 /C0099/C0117/C0114/C0114/C0101/C0110/C0116 /C0097/C0115 /C0111/C0102 /C0112/C0117/C0098/C0108/C0105/C0099/C0097/C0116/C0105/C0111/C0110 /C0100/C0097/C0116/C0101/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0099/C0111/C0110/C0102/C0111/C0114/C0109 /C0116/C0111 /C0115/C0112/C0101/C0099/C0105/C0102/C0105/C0099/C0097/C0116/C0105/C0111/C0110/C0115 /C0112/C0101/C0114 /C0116/C0104/C0101 /C0116/C0101/C0114/C0109/C0115 /C0111/C0102 /C0084/C0101/C0120/C0097/C0115 /C0073/C0110/C0115/C0116/C0114/C0117/C0109/C0101/C0110/C0116/C0115 /C0115/C0116/C0097/C0110/C0100/C0097/C0114/C0100 /C0119/C0097/C0114/C0114/C0097/C0110/C0116/C0121/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0105/C0111/C0110 /C0112/C0114/C0111/C0099/C0101/C0115/C0115/C0105/C0110/C0103 /C0100/C0111/C0101/C0115 /C0110/C0111/C0116 /C0110/C0101/C0099/C0101/C0115/C0115/C0097/C0114/C0105/C0108/C0121 /C0105/C0110/C0099/C0108/C0117/C0100/C0101 /C0116/C0101/C0115/C0116/C0105/C0110/C0103 /C0111/C0102 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115/C0046

/C0083/C0078/C0055/C0052/C0076/C0086/C0049/C0050/C0051/C0065/C0262/C0081/C0049 /C0068/C0085/C0065/C0076 /C0082/C0069/C0084/C0082/C0073/C0071/C0071/C0069/C0082/C0065/C0066/C0076/C0069 /C0077/C0079/C0078/C0079/C0083/C0084/C0065/C0066/C0076/C0069 /C0077/C0085/C0076/C0084/C0073/C0086/C0073/C0066/C0082/C0065/C0084/C0079/C0082 /C0087/C0073/C0084/C0072 /C0083/C0067/C0072/C0077/C0073/C0084/C0084/C0262/C0084/C0082/C0073/C0071/C0071/C0069/C0082 /C0073/C0078/C0080/C0085/C0084/C0083 SCLS467B − FEBRUARY 2003 − REVISED MAY 2004

2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

description/ordering information (continued) Pulse triggering occurs at a particular voltage level and is not directly related to the transition time of the input pulse. The A, B, and CLR inputs have Schmitt triggers with sufficient hysteresis to handle slow input transition rates with jitter-free triggering at the outputs. Once triggered, the basic pulse duration can be extended by retriggering the gated low-level-active (A) or high-level-active (B) input. Pulse duration can be reduced by taking CLR low. The input/output timing diagram illustrates pulse control by retriggering the inputs and early clearing. During power up, Q outputs are in the low state, and Q outputs are in the high state. The outputs are glitch free, without applying a reset pulse. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. FUNCTION TABLE (each multivibrator) INPUTS OUTPUTS CLR A B Q Q L X X L H X HX L † H † X XL L † H † H L ↑ H ↓ H ↑ L H † These outputs are based on the assumption that the indicated steady-state conditions at the A and B inputs have been set up long enough to complete any pulse started before the setup. logic diagram, each multivibrator (positive logic) CLR C ext R ext/Cext R B A Q Q

/C0083/C0078/C0055/C0052/C0076/C0086/C0049/C0050/C0051/C0065/C0262/C0081/C0049 /C0068/C0085/C0065/C0076 /C0082/C0069/C0084/C0082/C0073/C0071/C0071/C0069/C0082/C0065/C0066/C0076/C0069 /C0077/C0079/C0078/C0079/C0083/C0084/C0065/C0066/C0076/C0069 /C0077/C0085/C0076/C0084/C0073/C0086/C0073/C0066/C0082/C0065/C0084/C0079/C0082 /C0087/C0073/C0084/C0072 /C0083/C0067/C0072/C0077/C0073/C0084/C0084/C0262/C0084/C0082/C0073/C0071/C0071/C0069/C0082 /C0073/C0078/C0080/C0085/C0084/C0083 SCLS467B − FEBRUARY 2003 − REVISED MAY 2004 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 input/output timing diagram A B CLR Q Q tw tw tw + trr trr R ext/Cext absolute maximum ratings over operating free-air temperature (unless otherwise noted)† Voltage range applied to any output in the high-impedance † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. 2. This value is limited to 5.5 V maximum. 3. The package thermal impedance is calculated in accordance with JESD 51-7.

/C0083/C0078/C0055/C0052/C0076/C0086/C0049/C0050/C0051/C0065/C0262/C0081/C0049 /C0068/C0085/C0065/C0076 /C0082/C0069/C0084/C0082/C0073/C0071/C0071/C0069/C0082/C0065/C0066/C0076/C0069 /C0077/C0079/C0078/C0079/C0083/C0084/C0065/C0066/C0076/C0069 /C0077/C0085/C0076/C0084/C0073/C0086/C0073/C0066/C0082/C0065/C0084/C0079/C0082 /C0087/C0073/C0084/C0072 /C0083/C0067/C0072/C0077/C0073/C0084/C0084/C0262/C0084/C0082/C0073/C0071/C0071/C0069/C0082 /C0073/C0078/C0080/C0085/C0084/C0083 SCLS467B − FEBRUARY 2003 − REVISED MAY 2004

4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

recommended operating conditions (see Note 4) MIN MAX UNIT VCC Supply voltage 2 5.5 V VCC = 2 V 1.5 VIH High-level input voltage VCC = 2.3 V to 2.7 V VCC × 0.7 VVIH High-level input voltage VCC = 3 V to 3.6 V VCC × 0.7 V VCC = 4.5 V to 5.5 V VCC × 0.7 VCC = 2 V 0.5 VIL Low-level input voltage VCC = 2.3 V to 2.7 V VCC × 0.3 VVIL Low-level input voltage VCC = 3 V to 3.6 V VCC × 0.3 V VCC = 4.5 V to 5.5 V VCC × 0.3 VI Input voltage 0 5.5 V VO Output voltage 0 VCC V VCC = 2 V −50 µA IOH High-level output current VCC = 2.3 V to 2.7 V −2 IOH High-level output current VCC = 3 V to 3.6 V −6 mA VCC = 4.5 V to 5.5 V −12 mA VCC = 2 V 50 µA IOL Low-level output current VCC = 2.3 V to 2.7 V 2 IOL Low-level output current VCC = 3 V to 3.6 V 6 mA VCC = 4.5 V to 5.5 V 12 mA R ext External timing resistance VCC = 2 V 5 kΩR ext External timing resistance VCC ≥ 3 V 1 kΩ C ext External timing capacitance No restriction pF ∆t/∆VCC Power-up ramp rate 1 ms/V TA Operating free-air temperature −40 105 °C NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

/C0083/C0078/C0055/C0052/C0076/C0086/C0049/C0050/C0051/C0065/C0262/C0081/C0049 /C0068/C0085/C0065/C0076 /C0082/C0069/C0084/C0082/C0073/C0071/C0071/C0069/C0082/C0065/C0066/C0076/C0069 /C0077/C0079/C0078/C0079/C0083/C0084/C0065/C0066/C0076/C0069 /C0077/C0085/C0076/C0084/C0073/C0086/C0073/C0066/C0082/C0065/C0084/C0079/C0082 /C0087/C0073/C0084/C0072 /C0083/C0067/C0072/C0077/C0073/C0084/C0084/C0262/C0084/C0082/C0073/C0071/C0071/C0069/C0082 /C0073/C0078/C0080/C0085/C0084/C0083 SCLS467B − FEBRUARY 2003 − REVISED MAY 2004 5POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT IOH = −50 µA 2 V to 5.5 VVCC −0.1 VOH IOH = −2 mA 2.3 V 2 VVOH IOH = −6 mA 3 V 2.48 V IOH = −12 mA 4.5 V 3.8 IOL = 50 µA 2 V to 5.5 V 0.1 VOL IOL = 2 mA 2.3 V 0.4 VVOL IOL = 6 mA 3 V 0.44 V IOL = 12 mA 4.5 V 0.55 R ext/Cext† VI = 5.5 V or GND 2 V to 5.5 V ±2.5 II A, B, and CLRVI = 5.5 V or GND 0 ±1 µAII A, B, and CLRVI = 5.5 V or GND 0 to 5.5 V ±1 µA ICC Quiescent VI = VCC or GND, IO = 0 5.5 V 20 µA Active state VI = VCC or GND,

3 V 280

(per circuit) VI = VCC or GND, R ext/Cext = 0.5 VCC 4.5 V 650 µAICC (per circuit) R ext/Cext = 0.5 VCC 5.5 V 975 µA Ioff VI or VO = 0 to 5.5 V 0 5 µA C i VI = VCC or GND 3.3 V 1.9 pFC i VI = VCC or GND 5 V 1.9 pF † This test is performed with the terminal in the off-state condition. timing requirements over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) TEST CONDITIONS TA = 25°C MIN MAX UNITTEST CONDITIONS MIN TYP MAX MIN MAX UNIT tw Pulse CLR 5 5 nstw Pulse duration A or B trigger 5 5 ns trr Pulse retrigger time R ext = 1 kΩ C ext = 100 pF ‡ 76 ‡ ns trr Pulse retrigger time R ext = 1 kΩ C ext = 0.01 µF ‡ 1.8 ‡ µs ‡ See retriggering data in the application information section. timing requirements over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) TEST CONDITIONS TA = 25°C MIN MAX UNITTEST CONDITIONS MIN TYP MAX MIN MAX UNIT tw Pulse CLR 5 5 nstw Pulse duration A or B trigger 5 5 ns trr Pulse retrigger time R ext = 1 kΩ C ext = 100 pF ‡ 59 ‡ ns trr Pulse retrigger time R ext = 1 kΩ C ext = 0.01 µF ‡ 1.5 ‡ µs ‡ See retriggering data in the application information section.

/C0083/C0078/C0055/C0052/C0076/C0086/C0049/C0050/C0051/C0065/C0262/C0081/C0049 /C0068/C0085/C0065/C0076 /C0082/C0069/C0084/C0082/C0073/C0071/C0071/C0069/C0082/C0065/C0066/C0076/C0069 /C0077/C0079/C0078/C0079/C0083/C0084/C0065/C0066/C0076/C0069 /C0077/C0085/C0076/C0084/C0073/C0086/C0073/C0066/C0082/C0065/C0084/C0079/C0082 /C0087/C0073/C0084/C0072 /C0083/C0067/C0072/C0077/C0073/C0084/C0084/C0262/C0084/C0082/C0073/C0071/C0071/C0069/C0082 /C0073/C0078/C0080/C0085/C0084/C0083 SCLS467B − FEBRUARY 2003 − REVISED MAY 2004

6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

switching characteristics over recommended operating free-air temperature range, VCC = 3.3 V± 0.3 V (unless otherwise noted) (see Figure 1) PARAMETER FROM TO TEST TA = 25°C MIN MAX UNITPARAMETER FROM (INPUT) TO (OUTPUT) TEST CONDITIONS MIN TYP MAX MIN MAX UNIT A or B Q or Q 11.8 24.1 1 27.5 tpd CLR Q or Q C L = 50 pF 10.5 19.3 1 22 nstpd CLR trigger Q or Q C L = 50 pF 12.3 25.9 1 29.5 ns C L = 50 pF, C ext = 28 pF, R ext = 2 kΩ 182 240 300 ns tw † Q or Q C L = 50 pF, C ext = 0.01 µF, R ext = 10 kΩ 90 100 110 90 110 µs C L = 50 pF, C ext = 0.1 µF, R ext = 10 kΩ 0.9 1 1.1 0.9 1.1 ms ∆tw ‡ C L = 50 pF ±1 % † tw = Duration of pulse at Q and Q outputs ‡ ∆tw = Output pulse-duration variation (Q and Q) between circuits in same package switching characteristics over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) PARAMETER FROM TO TEST TA = 25°C MIN MAX UNITPARAMETER FROM (INPUT) TO (OUTPUT) TEST CONDITIONS MIN TYP MAX MIN MAX UNIT A or B Q or Q 8.3 14 1 16 tpd CLR Q or Q C L = 50 pF 7.4 11.4 1 13 nstpd CLR trigger Q or Q C L = 50 pF 8.7 14.9 1 17 ns C L = 50 pF, C ext = 28 pF, R ext = 2 kΩ 167 200 240 ns tw † Q or Q C L = 50 pF, C ext = 0.01 µF, R ext = 10 kΩ 90 100 110 90 110 µs C L = 50 pF, C ext = 0.1 µF, R ext = 10 kΩ 0.9 1 1.1 0.9 1.1 ms ∆tw ‡ ±1 % † tw = Duration of pulse at Q and Q outputs ‡ ∆tw = Output pulse-duration variation (Q and Q) between circuits in same package operating characteristics, TA = 25°C PARAMETER TEST CONDITIONS VCC TYP UNIT C pd Power dissipation capacitance C L = 50 pF, f = 10 MHz

3.3 V 44

pFC pd Power dissipation capacitance C L = 50 pF, f = 10 MHz 5 V 49 pF

NOTES: A. C L includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr /C00433 ns, tf /C0043 3 ns. C. The outputs are measured one at a time, with one input transition per measurement. Figure 1. Load Circuit and Voltage Waveforms

/C0083/C0078/C0055/C0052/C0076/C0086/C0049/C0050/C0051/C0065/C0262/C0081/C0049 /C0068/C0085/C0065/C0076 /C0082/C0069/C0084/C0082/C0073/C0071/C0071/C0069/C0082/C0065/C0066/C0076/C0069 /C0077/C0079/C0078/C0079/C0083/C0084/C0065/C0066/C0076/C0069 /C0077/C0085/C0076/C0084/C0073/C0086/C0073/C0066/C0082/C0065/C0084/C0079/C0082 /C0087/C0073/C0084/C0072 /C0083/C0067/C0072/C0077/C0073/C0084/C0084/C0262/C0084/C0082/C0073/C0071/C0071/C0069/C0082 /C0073/C0078/C0080/C0085/C0084/C0083 SCLS467B − FEBRUARY 2003 − REVISED MAY 2004

8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION † Figure 2 OUTPUT PULSE DURATION vs EXTERNAL TIMING CAPACITANCE 1.00E+07 tw − Output Pulse Duration − ns 1.00E+06 1.00E+05 1.00E+04 1.00E+03 1.00E+02 C T − External Timing Capacitance − pF 101 102 103 104 105 VCC = 3 V TA = 25°C R T = 1 MΩ R T = 100 kΩ R T = 10 kΩ R T = 1 kΩ Figure 3 OUTPUT PULSE DURATION vs EXTERNAL TIMING CAPACITANCE 1.00E+07 tw − Output Pulse Duration − ns 1.00E+06 1.00E+05 1.00E+04 1.00E+03 1.00E+02 C T − External Timing Capacitance − pF 101 102 103 104 105 R T = 1 MΩ R T = 100 kΩ R T = 10 kΩ R T = 1 kΩ VCC = 4.5 V TA = 25°C Figure 4 MINIMUM TRIGGER TIME vs VCC CHARACTERISTICS R T = 1 kΩ TA = 25°C 10.00 1.00 0.10 0.01 12 3 456 C T = 0.01 µF C T = 1000 pF C T = 100 pF VCC − Supply Voltage − V Minimum Retrigger Time − µsrr− t Figure 5 1.20 1.15 1.10 1.05 1.00 0.95 0.90 R T = 10 kΩ TA = 25°C tw = K × C T × R T VCC − Supply Voltage − V OUTPUT PULSE-DURATION CONSTANT vs SUPPLY VOLTAGE Output Pulse Duration Constant − K C T = 1000 pF C T = 0.01 µF C T = 1 µF, CT = 0.1 µF † Operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied.

MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0,65 M0,10 0,10 0,25 0,50 0,75 0,15 NOM Gage Plane 9,80 9,60 7,90 7,70 2016 6,60 6,40 4040064/F 01/97 0,30 6,60 6,20 0,19 4,30 4,50 0,15 A 1,20 MAX 5,10 4,90 3,10 2,90 A MAX A MIN DIM PINS ** 0,05 4,90 5,10 Seating Plane 0°–8° NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-153

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