KW47B42ZBXAFTBX

NXP Semiconductors

KW47 Product Family Rev. 4- 18 December 2025

Manufacturer: NXP Semiconductors

Document: 80 Pages / 1Mb

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PDF pages: 80

Technical content

Datasheet sections

1 Ratings
1.1 Thermal handling ratings
1.2 Moisture handling ratings
1.3 ESD and Latch-Up ratings
1.4 Voltage and current maximum ratings
1.5 Required Power-On-Reset (POR) sequencing
1.6 Power sequence
2 General
2.1 AC electrical characteristics
2.2 Nonswitching electrical specifications
2.2.1 Voltage and current operating requirements
2.2.3 Voltage and current operating behaviors
2.2.4 On-chip regulator electrical specifications
2.2.4.1 DCDC converter specifications
2.2.4.2 LDO_SYS electrical specifications
2.2.4.3 LDO_CORE electrical specifications
2.2.5 Smart power switch
2.2.6 Power mode transition operating behaviors
2.2.7 Power consumption operating behaviors
2.2.7.1 Power consumption operating behaviors
2.2.9 Designing with radiated emissions in mind
2.2.10 Capacitance attributes
2.3 Switching specifications
2.3.1 Device clock specifications
2.3.2 General switching specifications
2.4 Thermal specifications
2.4.1 Thermal operating requirements
2.4.2 Thermal attributes
3 Peripheral operating requirements and behaviors
3.1 Localization Compute Engine (LCE)
3.2 Core modules
3.2.1 SWD electricals
3.3 Clock modules
3.3.1 Reference oscillator specification
3.3.3 Free-running oscillator FRO-192M specifications
3.3.4 Free-running oscillator FRO-32K specifications30
3.3.5 Free-running oscillator FRO-16K specifications30
3.4 Memories and memory interfaces
3.4.1 Flash electrical specifications
3.4.1.1 Flash timing specifications
3.4.1.2 Flash high voltage current behavior
3.4.1.3 Flash reliability specifications
3.5 Radio modules
3.5.2 Receiver feature summary
3.5.3 Channel sounding summary
3.5.4 Transmit and PLL feature summary
3.6 Analog
3.6.1 ADC electrical specifications
3.6.2 CMP and 8-bit DAC electrical specifications
3.6.3 Voltage reference electrical specifications
3.7 Timers
3.8 Communication interfaces
3.8.1 LPUART
3.8.2 LPSPI switching specifications
3.8.3 Inter-Integrated circuit interface (I2C)
3.8.4 Improved Inter-Integrated Circuit Interface (MIPI-
3.8.5 CAN switching specifications
3.9 Human Machine Interface (HMI) modules
3.9.1 General Purpose Input/Output (GPIO)
3.9.2 Flexible IO controller (FlexIO)
4 Package dimensions
4.1 Obtaining package dimensions
5 Pinout
5.1 Pinout table
5.2 Recommended connection for unused analog and
5.3 Pinouts diagram
6 Ordering parts
6.1 Determining valid orderable parts
7 Part identification
7.1 Part number format
7.2 Example
7.3 Package marking information
8 Terminology and guidelines
8.1 Definitions
8.2 Examples
8.3 Typical-value conditions
8.4 Relationship between ratings and operating
8.5 Guidelines for ratings and operating
9 Abbreviations and acronyms
10 Revision history

Features

The KW47 product family is a low-power, highly secure, single-chip wireless MCU that integrates a high performance Bluetooth Low Energy version 6.0 radio and CAN FD for Automotive and Industrial applications.
The family integrates a state-of-the-art, scalable security architecture including Arm TrustZone -M, a resource domain controller, and an isolated EdgeLock™ Secure Enclave supporting hardware cryptographic accelerators, random number generators and key generation, storage and management and secure debug. Flash memory contents can optionally be stored as encrypted data and then decrypted on-the-fly enabling protection of sensitive data and algorithms.
For automotive applications, two integrated FlexCAN supporting CAN and CAN FD compliant with the ISO 11898-1 standard. The on-chip, low-power UARTs have LIN capabilities. The family is AEC-Q100 Grade 2 automotive qualified, with an extended ambient operating temperature range up to +105 °C.
The family integrates a Localization Compute Engine (LCE) featuring a digital signal processing (DSP) unit with a 64-bit SIMD data path for accelerating advanced Bluetooth® Channel Sounding algorithms via a high-performance vector and matrix operation library, including FFT, Eigenvalue Decomposition (EVD), and Hermitian matrix inverse. Application core
Up to 96 MHz Arm Cortex®-M33 core
Up to 2 MB flash memory
264 KB SRAM
TrustZone-M, IEEE 754 FPU, DSP, MPU, NVIC, SysTick
16 KB Code Cache to improve performance and efficiency
Secure Boot ROM Low-power consumption (DCDC 3.3 V, 25 ºC)
Transceiver current — Typical RX: 5.2 mA — Typical TX at 0 dBm: 5.38 mA and 15.75 mA at 10 dBm
Less than 4 μA in power-down mode with real-time clock (RTC) active and 48 KB SRAM retention
Less than 1.5 μA in Deep Power-Down mode with RTC active
Multiple power-down modes supporting currents as low as 300 nA
Ultra-low leakage Smart Power Switch with less than 130 nA sleep current with exit from internal timer or GPIO. KW47B42ZBxAFTBx KW47B42Z9xAFTBx KW47B42Z8xAFTBx KW47Z420BxAFTBx KW47Z4209xAFTBx KW47Z4208xAFTBx

48 HVQFN

7 x 7 x 0.85 mm Pitch 0.5 mm Wettable Flanks KW47 KW47 Product Family Rev. 4 — 18 December 2025 Product data sheet

Input supply voltage options:

Integrated DCDC regulator 1.86–3.6 V providing power to Core_LDO regulator, SYS_LDO regulators, and Radio
Integrated Core_LDO regulator 1.25 V–3.6 V powering the core digital domain
Integrated SYS_LDO regulator 1.86 V to 3.6 V powering the SYS domain Human Machine Interface modules
29 General-purpose input/output (GPIO) Operating characteristics
Temperature range (ambient): –40 °C to 105 °C
Temperature range (junction): –40 °C to 125 °C
DC/DC voltage range: 1.86 V to 3.6 V
LDO mode voltage range: 1.86 V to 3.6 V
Qualification: AEC-Q100 Grade 2 EdgeLock Secure Enclave
Secure boot and debug
Trusted Resource Domain Controller (TRDC) providing programmable control mechanisms for independent processing domains including embedded memory and peripherals — Privilege/user — Data only — Execute only — Read-only access — Secure/Non-secure Advanced flash access protection — Write/Erase protection, Execute only, Data only access control — Optional encryption and on-the-fly decryption using a PRINCE XEX block cipher mode
Hardware encryption and decryption — Symmetric Key Encryption ◦ AES-128/192/256 ◦ ECB, CBC, CTR, GCM, CMAC, and CCM Modes — Asymmetric Key Encryption ◦ ECC NIST P–192/224/256/384/521 ◦ Curve25519 — Key Exchange Algorithms ◦ ECDH(E) ◦ SPAKE2+ ◦ JPAKE — Digital Signature Algorithms ◦ ECDSA ◦ Ed25519 NXP Semiconductors KW47 KW47 Product Family KW47 All information provided in this document is subject to legal disclaimers. © 2025 NXP B.V. All rights reserved. Product data sheet Rev. 4 — 18 December 2025 Document feedback

— Hash Algorithms ◦ SHA2-224/256/384/512 ◦ Poly1305

Secure key generation, storage, and management
Pseudo (PRNG) and True Random Number Generator (TRNG) with 512-bits entropy supporting NIST SP 800-90A and SP 800-90B
Support for secure over-the-air (OTA) firmware updates
Four digital tamper pins with optional interrupt and seconds timestamp upon trigger
Universally Unique ID (UUID) programmed by NXP during factory programming
Factory Root of Trust programming Communication interfaces
Two FlexCAN with CAN and CAN FD supporting the full implementation of the CAN Specification Version 2.0, Part B. FD Support.
Two Low Power UART (LPUART) modules with LIN support
Two Low Power SPI modules and one MIPI-I3C module
Two Low Power I2C (LPI2C) modules supporting the System Management Bus (SMBus) Specification, version 2
One programmable FlexIO module supporting emulation of UART, I2C, SPI, Camera IF, LCD RGB, PWM/Waveform generation Clocks
32 MHz RF crystal oscillator
32.768 kHz crystal oscillator
Internal 192 MHz high frequency free running oscillator providing 48/64/96 MHz clock
Internal low power free running oscillator providing 32 kHz clock System peripherals
DC/DC converter supporting buck and bypass operating modes
Asynchronous DMA controller with per channel access permissions (secure/non-secure)
Two internal and one external watchdog monitors
Nested vectored interrupt controller
Wake-up unit for power-down modes Timers
Two 6-channel 32-bit timers (TPM) with PWM capability and DMA support
Three 32-bit low-power timers (LPTMR) or pulse counters with compare features
4-channel 32-bit low-power periodic interrupt timer (LPIT) with DMA support
32-bit seconds real time counter (RTC) with 32-bit alarm and independent power supply
Signal frequency analyzer (SFA) provides facilities for measurement of clock period/frequency as well as time between triggers Safety
Memory Protection Unit (MPU)
Register write protection NXP Semiconductors KW47 KW47 Product Family KW47 All information provided in this document is subject to legal disclaimers. © 2025 NXP B.V. All rights reserved. Product data sheet Rev. 4 — 18 December 2025 Document feedback

Illegal memory access
Flash area protection
SRAM Error Correction Code (ECC)
Clock Frequency Accuracy Measurement Circuit (CAC) using Signal Frequency Analyzer (SFA) module
Cyclic Redundancy Check (CRC) calculator
Two internal, independent and one external watchdog timer
Clock loss detection
Main oscillator stop detection (Loss of lock detection)
Low voltage / high voltage detection Bluetooth Low Energy radio core
Factory-programmed IEEE MAC address
Dedicated CM33 core running at up to 64 MHz
512 kB Flash supporting upgradable software radio
171 KB SRAM optimized for link layer support
Up to 24 simultaneous connections
–106 dBm 125 kbps Long Range Receive Sensitivity
–102 dBm 500 kbps Long Range Receive Sensitivity
–97.5 dBm 1 Mbps Receive Sensitivity
–95 dBm 2 Mbps Receiver Sensitivity
Programmable Transmit Output Power up to +10 dBm
Data Rates: 125 kbps, 500 kbps, 1 Mbps, and 2 Mbps
Modulation Types: 2 Level FSK, GFSK, MSK, GMSK
Integrated memories in radio containing Bluetooth LE Controller Stack and radio drivers
On-chip balun with single ended bidirectional RF port
Low external component counts for low cost, small form-factor designs Channel Sounding capabilities
CS Step for time and frequency synchronization – Mode 0 - supported
RTT packet exchange – Mode 1 - supported
Tone exchange (Phase Based Ranging) – Mode 2 - supported
RTT and tone exchange – Mode 3 - supported
Number of antenna paths - N_AP - 1, 2, 4
Antenna Configurations - 1x1, 1x2, 1x4, 2x1, 4x1, 2x2
Channel map specifies which channels are used or excluded - Channel_Map - supported
Channel Sounding Initiator - CS Initiator - supported
Channel Sounding Reflector - CS Reflector - supported
Modulation supported in mode 0, mode 1 and mode 3 packets 1 Mbps, 2 Mbps - CS SYNC PHY - supported
CS SYNC packet payload (HW support) – RTT_TYPE - Access Address only Random Sequence 32, 64, 96 and 128 bit NXP Semiconductors KW47 KW47 Product Family KW47 All information provided in this document is subject to legal disclaimers. © 2025 NXP B.V. All rights reserved. Product data sheet Rev. 4 — 18 December 2025 Document feedback

RTT_AA_Only_N, RTT_Random_Payload_N - 10 ns time-of-flight precision requirement - RTT_Capability - supported Channel Sounding security up to level 4
Channel selection algorithm for mode 0 steps - #3A
Channel selection algorithm for non-mode 0 steps - #3B, #3C
Tone quality indicator – TQI – low and high supported
Normalized Attack Detection Metric (phase-based) – NADM - supported
Bluetooth LE specification allows repeating the procedure multiple times in a controlled way - Procedure Repeat - supported
Frequency Actuation Error bit indicates whether the device supports mode-0 FAE tables - No_FAE - supported
Time allocated to swap channel – T_FCS – 50, 80, 150 μs
Interlude time allocated between RTT packets from initiator device and reflector device – T_IP1 - 40, 80, 145 μs
Interlude time allocated between tone TX from initiator device and reflector device – T_IP2 - 40, 80, 145 μs
Phase measurement time – T_PM – 20, 40 μs
Time allocated for Power Amplifier ramp-down – T_RD – 5 μs
Guard time between tone and packet transmission, in mode 0 and mode 3 steps – T_GD – 10 μs
Antenna switching time – T_SW – 2, 4, 10 μs
Frequency measurement time in mode 0 step – T_FM – 80 μs
CS SYNC packet (Access Address) duration – T_SY - 44 μs(1M CS SYNC PHY), 26 μs(2M CS SYNC PHY) Analog modules
16-bit single ended SAR Analog-to-Digital Converter (ADC) up to 2 Msps
Two high-speed Analog Comparators (CMP) with 8-bit Digital-to-Analog Converter (DAC)
1.0 V to 2.1 V Voltage Reference (Vref) Target applications
Automotive — Secure Car Access — Keyless Entry — Passive Entry/Passive Start (PEPS) Systems — Wireless Battery Management Systems (WBMS)
Industrial/IoT — Positioning/Localization — Building Control and Monitoring — Process/Factory Automation — Access Control NXP Semiconductors KW47 KW47 Product Family KW47 All information provided in this document is subject to legal disclaimers. © 2025 NXP B.V. All rights reserved. Product data sheet Rev. 4 — 18 December 2025 Document feedback

Table 1. Ordering information of radio parts [1],[2]

2 MB +

264 KB +

1 MB +

136 KB +

[1] To confirm current availability of orderable part numbers, go to http://www.nxp.com and perform a part number search. KW47 All information provided in this document is subject to legal disclaimers. © 2025 NXP B.V. All rights reserved.

[2] Devices with prefix "P" are pre-qualification devices. Fully qualified general market flow devices will not include this "P" prefix. Table 2. Ordering information of non-radio parts [1],[2] [1] To confirm current availability of orderable part numbers, go to http://www.nxp.com and perform a part number search. [2] Devices with prefix "P" are pre-qualification devices. Fully qualified general market flow devices will not include this "P" prefix.

In case of Tray 7x7 48-pin HVQFN "Wettable" - Minimum Package Quantity is 260 pcs
In case of Tape and Reel 7x7 48-pin HVQFN "Wettable" - Minimum Package Quantity is 2 kpcs

Table 3. Device revision number Table 4. Related resources structure and function (operation) of a device. description of the security architecture and function of a device. for a particular device mask set. Table continues on the next page... KW47 All information provided in this document is subject to legal disclaimers. © 2025 NXP B.V. All rights reserved.

Table 4. Related resources ...continued

171 K B SRAM

64 KB SRAM

1 Ratings

1.1 Thermal handling ratings

Table 5. Thermal handling ratings [1] Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life. [2] Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices.

1.2 Moisture handling ratings

Table 6. Moisture handling ratings [1] Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices.

1.3 ESD and Latch-Up ratings

Table 7. ESD and Latch-Up ratings [2] Determined according to JEDEC Standard JS-002-2022, For Electrostatic Discharge (ESD) Sensitivity Testing, Charged-Device Model (CDM) - Device Level . [3] Determined according to JEDEC Standard JESD78F, IC Latch-Up Test.

1.4 Voltage and current maximum ratings

Table 8. Voltage and current maximum ratings Table continues on the next page... KW47 All information provided in this document is subject to legal disclaimers. © 2025 NXP B.V. All rights reserved.

Table 8. Voltage and current maximum ratings...continued [1] The part supports 2.75 V for up to 20 s over lifetime to allow fuse programming. [2] The Max. of the VIN cannot be greater than the voltage applied to the VDD_IO_x. [3] Current loading is less than 40 mA.

1.5 Required Power-On-Reset (POR) sequencing

inputs on power-up must not exceed VDD voltage maximums. Figure 2. VDD_CORE/VDD_IO_ABC Powering Sequence KW47 All information provided in this document is subject to legal disclaimers. © 2025 NXP B.V. All rights reserved.

1.6 Power sequence

Table 9. Power sequence [1] All domains can be powered at the same time. If external sources are used, make sure they start at the same time or they follow the order in the sequence.

2 General

2.1 AC electrical characteristics

20% and 80% points, as shown in the following figure. Figure 3. Input signal measurement reference

2.2 Nonswitching electrical specifications

2.2.1 Voltage and current operating requirements

Table 10. Voltage and current operating requirements Table continues on the next page... KW47 All information provided in this document is subject to legal disclaimers. © 2025 NXP B.V. All rights reserved.

Table 10. Voltage and current operating requirements...continued

Normal mode
Fuse Programming 1.71 2.25 1.98 2.75 V — VDD_DCDC Supply voltage DCDC regulator 1.86 3.6 V — VDD_IO_D Supply voltage for LDO_SYS regulator, PortD 1.86 3.6 V — VDD_LDO_ CORE Supply voltage for LDO_CORE regulator 1.25 3.6 V — VDD_RF Supply voltage for OSC and radio analog 1.187 3.6 V — VPA_2P4GH z Supply voltage for 2.4 GHz radio power amplifier 0.9 2.4 V — VDD_IO_AB C Supply voltage for PortA, PortB, Port C, and CMPs 1.71 3.6 V [1] VDD_ANA Supply voltage for ADC, DAC, and VREF 1.71 3.6 V — VSS - VSS_ANA VSS-to-VSS_ANA differential voltage –0.1 0.1 V — VIH Input high voltage
1.71 V ≤ VDD_IO_ABC ≤ 3.6 V
1.86 V ≤ VDD_IO_D ≤ 3.6 V 0.7 × VDD_I O_ABC 0.7 × VDD_I O_D V [2] VIL Input low voltage
1.71 V ≤ VDD_IO_ABC ≤ 3.6 V
1.86 V ≤ VDD_IO_D ≤ 3.6 V 0.3 × VDD_I O_ABC 0.3 × VDD_I O_D V [2] VHYS Input hysteresis 0.1 × VDD_I O_X — V — IICIO IO pin DC injection current — single pin
VIN < VSS – 0.3 V (negative current injection)
VIN > VDD + 0.3 V (positive current injection) mA [3], [4] VODPU Open drain pullup voltage level VDD_IO_X VDD_IO_X V [5] [1] If none of the PortA, PortB, and PortC pins are being used, then the VDD_IO_ABC can be left floating. [2] VIH and VIL for PTD0 are based of VDD_SYS instead of VDD_IO_D. [3] All I/O pins are internally clamped to VSS and VDD_IO_x through an ESD protection diode. If VIN is greater than VDD_IO_x_MIN(= VSS – 0.3 V) or is less than VDD_IO_x_MAX(= VDD + 0.3 V), then there is no need to provide current limiting resistors at the pads. If this limit cannot be observed, then a current limiting resistor is required. [4] This device does not allow pin injection current. User must ensure that VIN is kept within the Voltage Maximum Ratings. [5] Open drain outputs must be pulled to whichever supply voltage corresponds to that IO, VDD_IO_X as appropriate. NXP Semiconductors KW47 KW47 Product Family KW47 All information provided in this document is subject to legal disclaimers. © 2025 NXP B.V. All rights reserved. Product data sheet Rev. 4 — 18 December 2025 Document feedback

2.2.2 HVD, LVD, and POR operating requirements

VDD_IO_ABC
VDD_CORE
VDD_SYS For VDD_SYS, it has Power-On-Reset (POR) power supervisor circuits.

Table 11. VDD_IO_ABC supply HVD, LVD, and POR Operating Ratings Table 12. VDD_CORE supply HVD and LVD Operating Ratings Table continues on the next page... KW47 All information provided in this document is subject to legal disclaimers. © 2025 NXP B.V. All rights reserved.

Table 12. VDD_CORE supply HVD and LVD Operating Ratings...continued [1] Same value applies to all conditions. Table 13. VDD_SYS supply HVD and LVD Operating Ratings

2.2.3 Voltage and current operating behaviors

Table 14. Voltage and current operating behaviors

2.7 V ≤ VDD_IO_X ≤ 3.6 V, IOH = 3.5 mA
1.71 V ≤ VDD_IO_ABC < 2.7 V, IOH = 2 mA
1.86 V ≤ VDD_IO_D < 2.7 V, IOH = 2 mA VDD_IO_X – 0.5 VDD_IO_X – 0.5 VDD_IO_X – 0.5 V [1] VOH Output high voltage — High drive strength
2.7 V ≤ VDD_IO_X ≤ 3.6 V, IOH = 5.5 mA
1.71 V ≤ VDD_IO_ABC < 2.7 V, IOH = 3.25 mA
1.86 V ≤ VDD_IO_D < 2.7 V, IOH = 3.25 mA VDD_IO_X – 0.5 VDD_IO_X – 0.5 V [1],[2] Table continues on the next page... NXP Semiconductors KW47 KW47 Product Family KW47 All information provided in this document is subject to legal disclaimers. © 2025 NXP B.V. All rights reserved. Product data sheet Rev. 4 — 18 December 2025 Document feedback

Table 14. Voltage and current operating behaviors...continued

2.7 V ≤ VDD_IO_X ≤ 3.6 V, IOL = 4 mA
1.71 V ≤ VDD_IO_ABC < 2.7 V, IOL = 2.5 mA
1.86 V ≤ VDD_IO_D < 2.7 V, IOL = 2.5 mA 0.5 0.5 0.5 V [1],[3] VOL Output low voltage — High drive strength
2.7 V ≤ VDD_IO_X ≤ 3.6 V, IOL = 6 mA
1.71 V ≤ VDD_IO_ABC < 2.7 V, IOL = 3.75 mA
1.86 V ≤ VDD_IO_D < 2.7 V, IOL = 3.75 mA 0.5 0.5 0.5 V [1],[3],[2] IOLT Output low current total for all ports — — 100 mA — IIN Input leakage current (per pin) for full temperature range — — 1 μA [4] IIN Input leakage current (per pin) at 25 °C — — 0.025 μA [4] IIN Input leakage current (total all pins) for full temperature range — — 41 μA [4] IOZ Hi-Z (off-state) leakage current (per pin) — — 1 μA — RPU Internal pullup resistors 33 50 75 kΩ — RPU (I3C) Internal pullup resistors 1.1 2 2.833 kΩ [5] RPD Internal pulldown resistors 33 50 75 kΩ — RHPU High-resistance pullup option (PORTx_PCRy[PV] = 1) 0.67 — 1.5 MΩ [6] RHPD High-resistance pulldown option (PORTx_PCRy[PV] = 1) 0.67 — 1.5 MΩ [6] [1] When setting DSE1=1, the same VOH / VOL is met with IOH / IOL at 4x. [2] RTC signals are always configured in high drive mode. [3] Open drain outputs must be pulled to VDD_IO_X. [4] Measured at VDD_IO_X = 3.6 V. [5] Only I3C pins support this option. [6] Only Port D pins support this option.

2.2.4 On-chip regulator electrical specifications

2.2.4.1 DCDC converter specifications

Table 15. DCDC Converter Specifications

Normal drive strength
Low drive strength
SPC_DCD_CFG[FREQ_CNTRL_ON ]=1 105 mA mA mA [1], [3] LX DCDC inductor value 0.8 1,1.5,2.2 2.65 µH [4] ESR External inductor equivalent series resistance — 110 — mΩ [5] COUT DCDC capacitance value 6 22 30 µF [6], [7] VRIPPLE DCDC voltage ripple
In normal drive strength
In low drive strength mV fburst DCDC burst frequency 3 5 8 MHz [8] fburst_acc DCDC burst frequency accuracy — 10 — % [8] [1] The system DCDC converter generates 1.8 V at DCDC_LX by default. The DCDC can be used to power VDD_RF, VDD_LDO_CORE, and external components as long as the max ILOAD is not exceeded. [2] The VDD_DCDC input supply to DCDC must be at least 500 mV higher than the desired output at DCDC_LX. [3] The maximum load current during boot up shall not exceed 60 mA. [4] Recommended inductor value is 1 µH to 1.5 µH. If the inductor is < 1 µH, the DCDC efficiency is not guaranteed. [5] The maximum recommended ESR is 250 mΩ (not a hard limit). [6] The variation in capacitance of the capacitor at DCDC_LX due to aging, temperature, and voltage degradation must not exceed the Min./Max. values. [7] Cout DCDC capacitance value parameter represents the total capacitance reflected on the DCDC low pass filter. In some configurations, the DCDC output supplies other power rails like VDD_RF, VDD_LDO_CORE and external components. The sum of all parallel capacitances of power rails, external components, and the DCDC low pass filter capacitor itself are included as part of Cout specification. [8] FREQ_CNTRL_ON = 1.

2.2.4.2 LDO_SYS electrical specifications

Table 16. LDO_SYS electrical specifications...continued

LDO_SYS input supply voltage (Regulation mode)
LDO_SYS input supply voltage (Bypass mode)
Fuse programming mode 1.86 1.8 2.75 3.6 1.98 3.6 VOUT_SYS LDO_SYS regulator output voltage
Normal drive mode
Fuse Programming mode 1.71 2.25 1.8 2.5 1.98 2.75 V [2],[3],[4],[5] ILOAD LDO_SYS maximum load current
Normal drive mode
Low drive mode
Fuse programming mode mA mA mA IDD LDO_SYS power consumption
Normal drive mode
Low drive mode 100 μA nA [6] COUT External output capacitor — 1.5 10 μF — CDEC External output decoupling capacitor — 0.1 — μF — ESR External output capacitor equivalent series resistance — 30 — mΩ — IINRUSH LDO_SYS inrush current — — 120 mA [7] [1] Regulator will automatically switch to passthrough (means the regulator driver is fully ON) with the supply is below 1.95 V. [2] The LDO_SYS converter generates 1.8 V by default at VOUT_SYS. VOUT_SYS can be used to power VDD_SYS, VDD_RF, VDD_IO_X, VDD_ANA, and external components as long as the max ILOAD is not exceeded. [3] VOUT_SYS and VDD_SYS are connected together. [4] VDD_IO_D must be at least 150 mV higher than the desired VOUT_SYS. [5] LDO_SYS can be used to program efuse and in this configuration the output voltage can range between 2.25 V and 2.75 V. [6] In normal drive strength, LDO_SYS draws ~100 μA for every 20 mA of load current. [7] This is for 1.5 μF external output capacitor. If the capacitor has 10 μF value, this value should be 300 mA instead.

2.2.4.3 LDO_CORE electrical specifications

Table 17. LDO_CORE electrical specifications Table continues on the next page... KW47 All information provided in this document is subject to legal disclaimers. © 2025 NXP B.V. All rights reserved.

Table 17. LDO_CORE electrical specifications...continued

Mid voltage 1.0 1.05 1.1 V
Normal voltage 1.045 1.1 1.15 V Low drive strength — — — —
Mid Voltage 1.0 1.05 1.1 V
Normal Voltage 1.045 1.1 1.15 V VDROP_OUT Drop out voltage Tj = 25C — 0.20 — V [3] ILOAD LDO_CORE max load current — — — —
Normal drive strength

0.20 V <

Low drive strength

[1] To bypass LDO_CORE, tie VDD_LDO_CORE to VDD_CORE. [2] VOUT_CORE and VDD_CORE are connected together in package . [4] This value is for 4.7 uF external output capacitor. This value would increase with higher load capacitor. Table 18. LDO_CORE external device electrical specifications

2.2.5 Smart power switch

Table 19. Smart power switch

2.2.6 Power mode transition operating behaviors

Table 20. Power mode transition operating behaviors temperature range of the chip. [1] Boot Configuration at 96 Mhz. [2] Based on characterization. Not tested in production. [3] ROM configured for low power wake up path. [4] WFE used for low power entry.

2.2.7 Power consumption operating behaviors

output is connected to VDD_LDO_CORE and VDD_RF power rails.

Specifications below only include power for the MCU itself
On top of the device’s IDD current consumption, external loads applied to pins of the device need to be considered
Efficiency of regulators (on-chip or off-chip) used to generate supply voltages should be considered NXP Semiconductors KW47 KW47 Product Family KW47 All information provided in this document is subject to legal disclaimers. © 2025 NXP B.V. All rights reserved. Product data sheet Rev. 4 — 18 December 2025 Document feedback

2.2.7.1 Power consumption operating behaviors

Table 21. LDO mode configuration power consumption table NBU Core from Flash; Cache enabled. RAM retained. Core voltage at 1.0 V. Table continues on the next page... KW47 All information provided in this document is subject to legal disclaimers. © 2025 NXP B.V. All rights reserved.

Table 21. LDO mode configuration power consumption table...continued Deep Sleep, Core_Radio in Deep Sleep. All RAM retained. Core voltage at 1.0 V. Power Down, Core_Radio in Deep Sleep. No RAM retained. Core voltage at 1.0 V. RAM retained. Core voltage at 1.0 V. RAM retained. Core voltage at 1.0 V. [1] Based on characterization of typical units. Not tested in production. [2] In order to reach App Core frequency of 96 MHz, CORELDO_VDD_LVL must be programmed to 1.1 V. Otherwise, CORELDO_VDD_LVL is 1.05 V. Note: Refer to Thermal specifications for formula to calculate Ta from Tj. Table 22. DCDC mode configuration power consumption table 64 MHz. All peripheral clocks enabled. 32 MHz. All peripheral clocks disabled. Table continues on the next page... KW47 All information provided in this document is subject to legal disclaimers. © 2025 NXP B.V. All rights reserved.

Table 22. DCDC mode configuration power consumption table...continued retained. Core voltage at 1.0 V. RAM retained. Core voltage at 1.0 V. Power Down, Core_Radio in Deep Sleep. No RAM retained. Core voltage at 1.0 V. RAM retained. Core voltage at 1.0 V. retained. Core voltage at 1.0 V. [1] Based on characterization of typical units. Not tested in production. [2] In order to reach App Core frequency of 96 MHz, CORELDO_VDD_LVL must be programmed to 1.1 V. Otherwise, CORELDO_VDD_LVL is 1.05 V. [4] DCDC output configured at 1.25 V. Note: Refer to Thermal specifications for formula to calculate Ta from Tj. KW47 All information provided in this document is subject to legal disclaimers. © 2025 NXP B.V. All rights reserved.

Table 23. Smart power switch [1] Based on characterization of typical units. Not tested in production. Note: Refer to Thermal specifications for formula to calculate Ta from Tj.

2.2.8 EMC radiated emissions operating behaviors

EMC measurements to IC-level IEC standards are available from NXP on request.

2.2.9 Designing with radiated emissions in mind

Go to https://www.nxp.com/.
Perform a keyword search for “EMC design”.

2.2.10 Capacitance attributes

Table 24. Capacitance attributes

2.3 Switching specifications

2.3.1 Device clock specifications

Table 25. Device clock specifications Note: By default, VDD_CORE = 1.0 V, fCPU_CLK/fBUS_CLK = 32 MHz, fSLOW_CLK = 16 MHz. KW47 All information provided in this document is subject to legal disclaimers. © 2025 NXP B.V. All rights reserved.

2.3.2 General switching specifications

Table 26. General switching specifications

1.5 AHB clock

1.71 ≤ VDD_IO_x < 2.7 V — Fast slew rate (SRE = 0; DSE = 1) — Slow slew rate (SRE = 1; DSE = 1) 2.5 4.6 1.6 4.3 ns ns ns ns [5],[6] Fast I/O pins — Normal drive, fast slew rate (SRE = 0; DSE = 0) — Normal drive, slow slew rate (SRE = 1; DSE = 0)
1.71 ≤ VDD_IO_x < 2.7 V — Normal drive, fast slew rate (SRE = 0; DSE = 1) — Normal drive, slow slew rate (SRE = 1; DSE = 1) 0.8 0.9 0.5 0.6 2.5 2.5 ns ns ns ns [7], [8] AOI pins
1.71 ≤ VDD_IO_x < 2.7 V 3.6 ns ns [6] [1] This is the shortest pulse that is guaranteed to be recognized. [2] Synchronous path is used in active and sleep mode for pin functions other than WUU. Pins configured as WUU use asynchronous path in all power modes. [3] Asynchronous path is used deep sleep, power down, and deep power down modes [4] Passive filter is always enabled for RESET_PIN NXP Semiconductors KW47 KW47 Product Family KW47 All information provided in this document is subject to legal disclaimers. © 2025 NXP B.V. All rights reserved. Product data sheet Rev. 4 — 18 December 2025 Document feedback

PORTx_PCRn[DSE], and PORTx_PCRn[SRE]. [7] Assumes default values in CALIB1 and CALIB0.

2.4 Thermal specifications

2.4.1 Thermal operating requirements

Table 27. Thermal operating requirements [2] The device operating specification is not guaranteed beyond 125 °C TJ. [3] The maximum operating requirement applies to all chapters unless otherwise specifically stated. [4] Operating at maximum conditions for extended periods may affect device reliability. [5] The radio performances are guaranteed up to 105 °C. Above this temperature, parameters will gradually change.

2.4.2 Thermal attributes

Table 28. Thermal attributes [1] Thermal test board meets JEDEC specification for this package (JESD51-7). [2] Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions—Natural Convection (Still Air). temperature at the package bottom side dead centre.

3 Peripheral operating requirements and behaviors

3.1 Localization Compute Engine (LCE)

data path optimized for high-throughput integer and floating-point operations, with native support for complex number arithmetic. consumption for CS applications. KW47 All information provided in this document is subject to legal disclaimers. © 2025 NXP B.V. All rights reserved.

buffers and orchestrates the execution of these LCE APIs to perform the complete Channel Sounding processing chain.

3.2 Core modules

3.2.1 SWD electricals

Figure 5. Serial wire data timing

3.3 Clock modules

3.3.1 Reference oscillator specification

temperature, mechanical, and aging excursions. The table below shows typical specifications for the Crystal Oscillator. Table 30. Reference Crystal Specification Table continues on the next page... KW47 All information provided in this document is subject to legal disclaimers. © 2025 NXP B.V. All rights reserved.

Table 30. Reference Crystal Specification...continued [1] Full temperature range of this device. A reduced range can be chosen to meet application needs. [2] Recommended crystal specification. [3] Combination of frequency stability variation over desired temperature range and frequency variation due to aging over desired lifetime of system. [4] Variation due to temperature, process, and aging of MCU. [6] Typical is target. 30% tolerances shown. [8] Time from oscillator enables to clock ready. Dependent on the complete hardware configuration of the oscillator. Figure 6. Crystal electrical block diagram KW47 All information provided in this document is subject to legal disclaimers. © 2025 NXP B.V. All rights reserved.

Table 31. 32 kHz oscillator electrical specifications

Normal/Start up mode
Low power mode — ±100 ±150 — ppm — Jitosc Jitter
Period jitter (RMS)
Accumulated jitter over 1 ms (RMS) 12000 8000 ns — ESR Crystal equivalent series resistance
Normal mode
Low power mode 100 kΩ [1] Cpara Parasitic capacitance of EXTAL32 and XTAL32 — 2.5 — pF — tstart Crystal start-up time
Normal/Start up mode
Low power mode 1000 8000 ms [2] IOSC_32k Current consumption
ON mode — Normal mode — Low power mode
OFF mode 220 110 0.5 — nA Vpp Peak-to-peak amplitude of oscillation
Normal mode
Low power mode 0.2 0.1 V [3] fec_extal32 Externally provided input clock frequency — 32.768 — kHz [4] vec_extal32 Externally provided input clock amplitude Refer to Voltage and Current operating requirements for VIH and VIL levels mV [4], [5] Cextal/xtal EXTAL, XTAL Load Capacitance 0 — 30 pF [6] [1] Maximum value is 80 kΩhms for parasitic capacitances higher than 1 pF, and 150 kOhms for parasitic capacitances around 1 pF. [2] Proper PC board layout procedures must be followed to achieve specifications. [3] When a crystal is being used with the 32 kHz oscillator, the EXTAL32 and XTAL32 pins should only be connected to required oscillator components and must not be connected to any other devices. [4] This specification is for an externally supplied clock driven to EXTAL32 and does not apply to any other clock input. The oscillator remains enabled and XTAL32 must be left unconnected. [5] The parameter specified is a peak-to-peak value and VIH and VIL specifications do not apply. The voltage of the applied clock must be within the range of VSS to VDD_IO_D. [6] With 2 pF steps. Note: It is recommended that the oscillator margin be measured on the actual application PCB with the target crystal. NXP Semiconductors KW47 KW47 Product Family KW47 All information provided in this document is subject to legal disclaimers. © 2025 NXP B.V. All rights reserved. Product data sheet Rev. 4 — 18 December 2025 Document feedback

3.3.3 Free-running oscillator FRO-192M specifications

Table 32. FRO-192M specifications

Open loop
Closed loop (using accurate clock source as reference) ±0.25 tstartup Start-up time
Oscillation time with initial accuracy of ±20 % to ±2 % of enable signal assertion
Oscillation time within ±2 % from enable signal assertion μs μs fos Frequency overshoot during startup — — 2 % — jitper • Period jitter RMS [1]
Accumulated jitter over 1 μs 375 ps — jitcyc Cycle to Cycle jitter RMS — 60 — ps — Ifro192m Current consumption — 40 100 μA — [1] Reference clock = 192 MHz.

3.3.4 Free-running oscillator FRO-32K specifications

Table 33. FRO-32K specifications

open loop — — ±2 TRIMstep Trimming step — 0.05 — % — tstartup Start-up time — — 50 μs — fos Frequency overshoot during startup
Trimmed — — — % — Ifro32k Current consumption — 220 — nA —

3.3.5 Free-running oscillator FRO-16K specifications

Table 34. FRO-16K specifications...continued

Over –40 °C~125 °C temperature range — — ±6 % TRIMstep Frequency trimming step — 1.5 — % — Ifro16k Current consumption — 50 — nA [2] Ipor Current consumption — 26 — nA — [1] FRO-16K is in Power Switch block, which is powered by min 1.9 V VDD_SWITCH [2] The Typical value (50 nA) of current consumption includes 26 nA POR current consumption in stable running period.

3.4 Memories and memory interfaces

3.4.1 Flash electrical specifications

This section describes the electrical characteristics of the flash memory module.

3.4.1.1 Flash timing specifications

a command is not included in the following table. Table 35. Flash command time specifications Table continues on the next page... KW47 All information provided in this document is subject to legal disclaimers. © 2025 NXP B.V. All rights reserved.

Table 35. Flash command time specifications...continued [1] Time to abort the command may significantly impact the time to execute the command. [2] Measured from the time PERDY is cleared.

3.4.1.2 Flash high voltage current behavior

Table 36. Flash high voltage current behavior [1] See the Power Management chapter in the reference manual for the specific VDD_IO_x voltage supply powering the flash array.

3.4.1.3 Flash reliability specifications

Table 37. Flash reliability specifications

100 K 500 K — cycles [3]

[1] Typical data retention values are based on measured response accelerated at high temperature and derated to a constant 25 °C use profile. [2] Sector cycling endurance represents the number of Program/Erase cycles on a single sector at -40 °C ≤ Tj ≤ 125 °C. be located within the last 256 KB of each flash main memory.

3.5 Radio modules

Table 38. 2.4 GHz radio transceiver specifications [1] Voltage required at this rail depends on the desired output power. See Transmit and PLL feature summary for the required voltages. VPA_2P4GHZ from going above 2.4 V when powered through the VDD_RF pin.

3.5.2 Receiver feature summary

Table 39. Top-level receiver specifications (TA = 25 °C, nominal process unless otherwise noted) Table continues on the next page... KW47 All information provided in this document is subject to legal disclaimers. © 2025 NXP B.V. All rights reserved.

Table 39. Top-level receiver specifications (TA = 25 °C, nominal process unless otherwise noted)...continued Table continues on the next page... KW47 All information provided in this document is subject to legal disclaimers. © 2025 NXP B.V. All rights reserved.

±10 MHz – Wanted signal at –64 dBm, BER < 0.1 %. MHz to 12750 MHz (Wanted signal at –67 dBm, BER < 0. Table continues on the next page... KW47 All information provided in this document is subject to legal disclaimers. © 2025 NXP B.V. All rights reserved.

±12 MHz -- Wanted signal at –64 dBm, BER < 0.1 %. [1] All the RX parameters are measured at the RF pin. [2] Transceiver power consumption. [3] Variation across temperature (-40 °C to 125 °C) is up to 3 dB. [6] With RSSI_CTRL_0.RSSI_ADJ field calibrated to account for antenna to RF input losses. [7] With one point calibration over frequency and temperature. [8] Exceptions allowed for twice the reference clock frequency(fref) multiples. [9] Measured at 0.1 % BER using 37 bytes payload long packets in maximum gain mode and nominal conditions. [11] Bluetooth LE adjacent and alternate selectivity performance is measured with modulated interference signals. [13] Exceptions allowed for carrier frequency sub harmonics. [14] Exceptions allowed for carrier frequency harmonics. KW47 All information provided in this document is subject to legal disclaimers. © 2025 NXP B.V. All rights reserved.

Table 40. Receiver Specifications with Generic FSK Modulations [1] Selectivity measured with an unmodulated blocker. [3] Variation across temperature (-40 °C to 125 °C) is up to 3 dB.

3.5.3 Channel sounding summary

Table 41. Channel sounding mode capabilities Table continues on the next page... KW47 All information provided in this document is subject to legal disclaimers. © 2025 NXP B.V. All rights reserved.

Table 41. Channel sounding mode capabilities...continued Table 42. Channel sounding supported capabilities

3.5.4 Transmit and PLL feature summary

Supports constant envelope modulation of 2.4 GHz ISM frequency band.
Fast PLL Lock time: < 25 µs
Reference Frequency: — 32 MHz crystals supported for Bluetooth LE and Generic FSK modes NXP Semiconductors KW47 KW47 Product Family KW47 All information provided in this document is subject to legal disclaimers. © 2025 NXP B.V. All rights reserved. Product data sheet Rev. 4 — 18 December 2025 Document feedback

Table 43. Top-level transmitter specifications (TA = 25 °C, nominal process unless otherwise noted)

1.12 V) [2]

1.69 V) [2]

1.67 V) [2]

2.32 V)[2]

Table 43. Top-level transmitter specifications (TA = 25 °C, nominal process unless otherwise noted)...continued [1] All the TX parameters are measured at test hardware SMA connector. [2] Transceiver power consumption. NBU running at 16 MHz. [3] Measured at RF pins, with VPA_2P4GHz = 2.4 V. [4] Variation across temperature (-40 °C to 125 °C) is up to 3 dB. [6] Maximum drift of carrier frequency of the PLL during a Bluetooth LE packet with a nominal 32 MHz reference crystal. components. Additional harmonic margin using a 3rd matching component (1x shunt capacitor) is possible. [8] Measured at Pout > 5 dBm and recommended high-power TX match.

3.6 Analog

3.6.1 ADC electrical specifications

Table 44. 16-bit ADC operating conditions

Low-power mode (PWRSEL=00)
High-speed 16b mode (PWRSEL = 10)
High-speed 12b mode (PWRSEL = 10) MHz MHz MHz CADIN Input capacitance — 3.7 4.63 pF — Cp Parasitic Cap of pad /package — 2 3 pF — RAS Analog source resistance (external) — — 5 kΩ [6] RADIN • High-speed dedicated input channel (CH0:3) — VDD_ANA ≥ 1.71 V — VDD_ANA ≥ 2.1 V — VDD_ANA ≥ 2.5 V
Standard external input channel (Ch4:7) — VDD_ANA ≥ 1.71 V — VDD_ANA ≥ 2.1 V — VDD_ANA ≥ 2.5 V
Standard muxed input channel (Ch4:11) — VDD_ANA ≥ 1.71 V — VDD_ANA ≥ 2.1 V — VDD_ANA ≥ 2.5 V 0.95 0.95 0.95 1.35 1.35 1.35 1.65 1.65 1.65 1.7 1.6 1.4 3.25 2.15 1.75 7.25 3.05 2.35 kΩ [7],[8] [1] Typical values assume VDD_ANA= 3.0 V, Temp = 25 °C, fADCK = 24 MHz, unless otherwise stated. Typical values are for reference only, and are not tested in production. [2] DC potential difference. [3] For devices that do not have a dedicated VREFL and VSS_ANA pins, VREFL and VSS_ANA are tied to VSS internally. [4] If VREFH is less than VDD_ANA, then voltage inputs greater than VREFH but less than VDD_ANA are allowed but result in a full scale conversion result [5] ADC selected inputs and unselected dedicated inputs must not exceed VDD_ANA during an ADC conversion. Unselected muxed inputs may exceed VDD_ANA but must not exceed the IO supply associated with the inputs (VDD_IO_X) when a conversion is in progress. If an ADC input may exceed these levels, then a minimum of 1 K series resistance must be used between the source and the ADC input pin. [6] This resistance is external to MCU. To achieve the best results, the analog source resistance must be kept as low as possible. [7] There are several types of ADC inputs. To see which channels correspond to which type of ADC inputs, see channel index map in reference manual [8] If the input come through a mux in the IO pad, add the IO Mux Resistance Adder value to the resistance for the channel type NXP Semiconductors KW47 KW47 Product Family KW47 All information provided in this document is subject to legal disclaimers. © 2025 NXP B.V. All rights reserved. Product data sheet Rev. 4 — 18 December 2025 Document feedback

Figure 7. ADC input impedance equivalency diagram Table 45. 16-bit ADC characteristics (VREFH = VDD_ANA, VREFL = VSS_ANA)

PWREN=0, Conversions triggered at 1 kS/s
PWREN=1, No Conversions
Low-power, single-ended mode, 6 MHz
Low-power, or dual-SE mode, 6 MHz
Low-power, single-ended mode, 24 MHz
Low-power, or dual-SE mode, 24 MHz
High-speed, single-ended mode, 48 MHz
High-speed, or dual-SE mode, 48 MHz 2.2 160 340 500 415 580 940 1500 215 440 640 530 750 1200 1950 μA μA μA μA μA μA μA μA [2] ITS Temp Sensor Current Adder — 40 50 μA — CSMP ADC Sample cycles 3.5 — 131.5 cycles [3] CCONV ADC conversion cycles 24 — 152 cycles — CRATE ADC conversion rate — — 0.857 MS/s [4] Table continues on the next page... NXP Semiconductors KW47 KW47 Product Family KW47 All information provided in this document is subject to legal disclaimers. © 2025 NXP B.V. All rights reserved. Product data sheet Rev. 4 — 18 December 2025 Document feedback

Table 45. 16-bit ADC characteristics (VREFH = VDD_ANA, VREFL = VSS_ANA)...continued

Low-power mode
High-speed mode (16-bits)
High-speed mode (12-bits) 3.16 TSMP_REQ Required Sample Time See equation — — ns [5] TAZ_REQ Required Auto-zero Time
Low-power mode
High-power mode (16-bits)
High-power mode (12-bits) 291.7 72.9 58.3 ns [5] TSMP Sample Time External inputs See equation — — ns [5] TSMP_INT Internal channel sample time 1.5 — — μs [6] DNL Differential non-linearity — ±0.7 +1.4/–0.95 LSB[7] [8] INL Integral non-linearity — ±2.0 +4.0/–2.0 LSB[7] [8] ZSE Zero-scale error (VADIN = VREFL) — ±1.0 ±2.0 LSB[7] [8] FSE Full-scale error (VADIN=V REFH) — ±2.0 +2.0/–8.0 LSB[7] [8] TUE Total unadjusted error — ±4.0 ±10.0 LSB[7] [8] ENOB Effective number of bits
Differential mode — 0.5 MS/s — 2 MS/s
Single-ended mode — 0.5 MS/s — 2 MS/s 12.7 12.0 12.4 11.5 13.5 12.7 13.1 12.2 bits [8],[9] SINAD Signal-to-noise plus distortion
Differential mode — 0.5 MS/s — 2 MS/s
Single-ended mode — 0.5 MS/s — 2 MS/s dB [8],[9] THD Total harmonic distortion 85 92 — dB [8],[10] SFDR Spurious free dynamic range 86 94 — dB [8],[10] Table continues on the next page... NXP Semiconductors KW47 KW47 Product Family KW47 All information provided in this document is subject to legal disclaimers. © 2025 NXP B.V. All rights reserved. Product data sheet Rev. 4 — 18 December 2025 Document feedback

T=–40 °C to 105 °C
T=–40 °C to 125 °C ±1.5 °C [13] [1] Typical values assume VDD_ANA = 3.0 V, Temp = 25 °C, fADCK = 24 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. [2] The ADC supply current depends on the ADC conversion clock speed, conversion rate and power mode. Typical value show is at 6 MHz, 24 MHz, and 48 MHz. For lowest power operation, PWRSEL should be set to 00. [3] Must meet minimum TSMP requirement. [4] Maximum conversion rate for high-speed mode is with FADCK = 48 MHz. Maximum conversion rate for low-power mode is FADCK = 24 MHz and 7.5 sample cycles (to meet the minimum auto-zero time requirement). [5] Required sample time is dictated by external components RAS, CAS, internal components RADIN, CADIN, CP, and desired sample accuracy in bits. Calculated it with formula: T SMP_REQ = B*IN(2)*[RAS*(CAS*CP)+ (RAS + R ADIN)* CADIN(typ). Required auto-zero time is for ADC comparator offset cancellation. The chosen sample time should be no less than maximum of the two: TSMP = max(TSMP_REQ,TAZ_REQ). [6] Internal channel inputs are those that do not come from external source (temperature sensor, bandgap). [7] 1 LSB = (VREFH - VREFL)/2N (N=14 bits), for 16-bit specifications, multiply by 4. [8] All accuracy numbers assume the ADC is calibrated with VREFH=VDD_ANA and using a high-speed dedicated input channel. [9] Dynamic results assume Fin = 1 kHz sinewave, AVGS = 0 for 2 MS/s, AVGS = 4 for 0.5 MS/s. [10] Dynamic results assume Fin = 1 kHz sinewave, no averaging. [11] Set the power up delay (PUDLY) according to the ADC start-up time if PWREN=0. [12] Ilkg = leakage current (Refer to pin leakage specification in the packaged device's voltage and current operating ratings). [13] The temperature sensor can be calibrated to a ± 0.5% precision after board assembly by using a 3 temperature calibration flow with accurate ± 0.15 % temperature chamber.

3.6.2 CMP and 8-bit DAC electrical specifications

Table 46. Comparator and 8-bit DAC electrical specifications

High-speed mode (EN=1, HPMD=1, NPMD=0)
Normal mode (EN=1, HPMD=0, NPMD=0)
Nano mode (EN=1, HPMD=0, NPMD=1) 200 400 μA μA nA VAIN Analog input voltage VSS_ANA — VDD_ANA V [1] VAIO Analog input offset voltage
High-speed mode
Normal mode
Nano mode mV mV mV VH Analog comparator hysteresis — 0 — mV [2] Table continues on the next page... NXP Semiconductors KW47 KW47 Product Family KW47 All information provided in this document is subject to legal disclaimers. © 2025 NXP B.V. All rights reserved. Product data sheet Rev. 4 — 18 December 2025 Document feedback

Table 46. Comparator and 8-bit DAC electrical specifications...continued

CR0[HYSTCTR] = 00
CR0[HYSTCTR] = 01
CR0[HYSTCTR] = 10
CR0[HYSTCTR] = 11 mV mV mV tD Propagation delay
High-speed mode, 100 mV overdrive, power > 1.71 V
High-speed mode, 30 mV overdrive, power > 1.71 V
Normal mode, 30 mV overdrive, power > 1.71 V
Nano mode, 30 mV overdrive, power > 1.71 V 600 ns ns ns μs [3] tinit Analog comparator initialization delay — — 40 μs [4] IDAC8b 8-bit DAC current adder (enabled)
High-power mode (EN=1, PMODE=1)
Low-power mode (EN=1, PMODE=0) μA μA INL 8-bit DAC integral non-linearity
Low/High power mode, supply power > 1.71 V –1.0 — +1.0 LSB [5] DNL 8-bit DAC differential non-linearity
Low/High power mode, power > 1.71 V –1.0 — +1.0 LSB [5] [1] For devices that do not have a dedicated VSS_ANA pin, VSS_ANA is tied to VSS internally. [2] Typical hysteresis is measured with input voltage range limited to 0.6 to VDD_ANA–0.6 V. [3] Overdrive does not include input offset voltage or hysteresis. [4] Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to CMP_DACCR[DACEN], CMP_DACCR[VRSEL], CMP_DACCR[VOSEL], CMP_MUXCR[PSEL], and CMP_MUXCR[MSEL]), and the comparator output settling to a stable level. [5] 1 LSB = Vreference/256. Typical hysteresis NXP Semiconductors KW47 KW47 Product Family KW47 All information provided in this document is subject to legal disclaimers. © 2025 NXP B.V. All rights reserved. Product data sheet Rev. 4 — 18 December 2025 Document feedback

Figure 10. Typical hysteresis vs. Vin level (VDD = 3.3 V, HPMD = 0, NPMD = 1)

3.6.3 Voltage reference electrical specifications

Table 47. VREF operating requirements [1] VDD_ANA must be at least 600 mV greater than the selected VREFO output voltage. [2] CL must be connected to VREFO if the VREFO functionality is being used for either an internal or external reference. [3] The minimum CL capacitance must take into account the variation in capacitance of the chosen capacitor due to voltage, temperature and aging. Table 48. VREF operating behaviors

1.0 V low-power reference voltage

Table 48. VREF operating behaviors...continued [1] See the chip's Reference Manual for the appropriate settings of the VREF Status and Control register. [2] Vvrefo max is also ≤ VDD_ANA - 600 mV. [3] Load regulation voltage is the difference between the VREFO voltage with no load vs. voltage with defined load.

3.7 Timers

See General switching specifications.

3.8 Communication interfaces

3.8.1 LPUART

See General switching specifications.

3.8.2 LPSPI switching specifications

The Low Power Serial Peripheral Interface (LPSPI) provides a synchronous serial bus with controller and peripheral operations. Many of the transfer attributes are programmable. The following tables provide timing characteristics for classic SPI timing modes. Table 49. LPSPI controller mode timing

LPSPI0
LPSPI1 MHz MHz [1][2] LP2 SCK period 2 x tperiph 2048 x tperiph ns [3] LP3 Enable lead time 1/2 — tperiph [3] LP4 Enable lag time 1/2 — tperiph [3] LP5 Clock (SCK) high or low time tSCK/2 - 3 tSCK/2 ns — LP6 Data setup time (inputs)
LPSPI0, LPSPI1 at 24 MHz
LPSPI1 at 48 MHz 14.4 7.2 — ns — LP7 Data hold time (inputs) 0 — ns — Table continues on the next page... NXP Semiconductors KW47 KW47 Product Family KW47 All information provided in this document is subject to legal disclaimers. © 2025 NXP B.V. All rights reserved. Product data sheet Rev. 4 — 18 December 2025 Document feedback

Table 49. LPSPI controller mode timing...continued

LPSPI0, LPSPI1 at 24 MHz
LPSPI1 at 48 MHz 14.4 7.2 ns — LP9 Data hold time (outputs) -1 — ns — [1] The frequency of operation is also limited to a minimum of fperiph/2048 and a max of fperiph/2, where fperiph is the LPSPI peripheral functional clock. [2] 48 MHz is only possible for PTB port. If PTC port is used, maximum allowed is 12 MHz. [3] tperiph = 1/fperiph. (OUTPUT) LP2 LP8 LP6 LP7 MSB IN 2 LSB IN MSB OUT 2 LSB OUT LP9 LP5 LP5 LP3 (CPOL=0) LP4 SCK SCK (CPOL=1) 1. If configured as an output. PCS 1 (OUTPUT) (OUTPUT) SOUT (OUTPUT) SIN (INPUT) BIT 6 . . . 1 BIT 6 . . . 1

Figure 12. LPSPI controller mode timing (CPHA = 1) Table 50. LPSPI target mode timing

target TX in SD mode — LPSPI0 — LPSPI1 on PTB — LPSPI1 (not PTB pins)
target RX in SD mode — LPSPI0 — LPSPI1 on PTB — LPSPI1 (not PTB pins) — 12 MHz [1] LP2 SCK period 2 x tperiph 2048 x tperiph ns [2] LP3 Enable lead time 1 — tperiph [2] LP4 Enable lag time 1 — tperiph [2] LP5 Clock (SCK) high or low time tSCK/2 - 5 tSCK/2 ns — LP6 Data setup time (inputs)
LPSPI0, LPSPI1 at 24 MHz
LPSPI1 at 48 MHz 14.4 3.6 — ns [3] LP7 Data hold time (inputs) 0 — ns — LP8 target access time — tperiph ns [2][4],[3] Table continues on the next page... NXP Semiconductors KW47 KW47 Product Family KW47 All information provided in this document is subject to legal disclaimers. © 2025 NXP B.V. All rights reserved. Product data sheet Rev. 4 — 18 December 2025 Document feedback

Table 50. LPSPI target mode timing...continued

LPSPI0, LPSPI1 at 12 MHz
LPSPI1 at 24 MHz 31.2 16.25 ns [2] LP11 Data hold time (outputs) 2 — ns — [1] The frequency of operation is also limited to a minimum of fperiph/2048 and a max of fperiph/2, where fperiph is the LPSPI peripheral functional clock. [2] tperiph = 1/fperiph. [3] 48 MHz is only possible for PTB port in normal voltage (VDD_CORE=1.1 V) with SAMPLE=1. If PTC port is used, maximum allowed is 24 MHz. [4] Time to data active from high-impedance stat. [5] Hold time to high-impedance state. LP2 LP10 LP6 LP7 MSB IN BIT 6 . . . 1 TARGETMSB TARGET LSB OUT LP11 LP5LP5LP3 LP8 LP4 NOTE: Not defined LP11 SEE NOTE LP9 see note (INPUT) (CPOL=0) SCK SCK (CPOL=1) PCS (INPUT) (INPUT) SIN (INPUT) SOUT (OUTPUT) LSB INBIT 6 . . . 1

Figure 14. LPSPI target mode timing (CPHA = 1)

3.8.3 Inter-Integrated circuit interface (I2C) specifications

Table 51. I 2C timing Hold time (repeated) START condition. negative hold time can result, depending on the edge rates of the SDA and SCL lines. region of the falling edge of SCL. [3] The maximum tHD; DAT must be met only if the device does not stretch the LOW period (tLOW) of the SCL signal. KW47 All information provided in this document is subject to legal disclaimers. © 2025 NXP B.V. All rights reserved.

[5] Set-up time in target-transmitter mode is 1 IPBus clock period, if the TX FIFO is empty. [7] Cb = total capacitance of the one bus line in pF. Table 52. I 2C 1 Mbps timing period, the first clock pulse is generated. [1] Cb = total capacitance of the one bus line in pF. The max Cb value is 50 pF. Table 53. I2C HS mode timing[1] first clock pulse is generated. Table continues on the next page... KW47 All information provided in this document is subject to legal disclaimers. © 2025 NXP B.V. All rights reserved.

Table 53. I2C HS mode timing[1]...continued [1] Only PTB4/5, PTA18/19, PTC0/1, PTC4/5 pin can support Fast+ (3 MHz) mode. a threshold as low as possible for the falling edge of the SCLH signal minimizes this hold time. [3] Cb = total capacitance of the one bus line in pF. The max Cb value is 50 pF. Figure 15. Timing definition for devices on the I2C bus

3.8.4 Improved Inter-Integrated Circuit Interface (MIPI-I3C) specifications

Unless otherwise specified, MIPI-I3C specifications are timed to/from the VIH and/or VIL signal points. Table 54. MIPI-I3C specifications when communicating with legacy I2C devices [1] Cb = total capacitance of the one bus line in pF. KW47 All information provided in this document is subject to legal disclaimers. © 2025 NXP B.V. All rights reserved.

Table 55. MIPI-I3C open drain mode specifications

ENTAS0
ENTAS1
ENTAS2
ENTAS3 38.4 n 38.4 n 38.4 n 38.4 n 1 μ 100 μ 2 m 50 m s s s s tCBP Clock before STOP (P) condition tCAS(min)/2 — ns — tMMOverlap Current controller to secondary controller overlap time during handoff tDIG_OD_L — ns — tAVAL Bus available condition 1 — μs — tIDLE Bus idle condition 1 — ms — tMMLock Time internal where new controller not driving SDA low tAVAL — μs — [1] Cb = total capacitance of the one bus line in pF.

Table 56. MIPI-I3C push-pull specifications for SDR and HDR-DDR modes Table continues on the next page... KW47 All information provided in this document is subject to legal disclaimers. © 2025 NXP B.V. All rights reserved.

Table 56. MIPI-I3C push-pull specifications for SDR and HDR-DDR modes...continued

controller mode
target mode tCR + 3 and tCF + 3 ns — tSU_PP SDA signal setup 3 — — ns — tCASr Clock after repeated START (Sr) tCAS (min) — — ns — tCBSr Clock before repeated START (Sr) tCAS (min)/2 — — ns — Cb Capacitive load per bus line — — 50 pF — [1] When communicating with an I3C Device on a mixed Bus, the tDIG_H_MIXED period must be constrained in order to make sure that I2C devices do not interpret I3C signaling as valid I2C signaling. SDA SCL

0.3 X V DD

0.7 X V DD

3.8.5 CAN switching specifications

See General switching specifications.

3.9 Human Machine Interface (HMI) modules

3.9.1 General Purpose Input/Output (GPIO)

See General switching specifications.

3.9.2 Flexible IO controller (FlexIO)

Table 57. FlexIO timing specifications

4 Package dimensions

4.1 Obtaining package dimensions

Package dimensions are provided in package drawings.

5 Pinout

5.1 Pinout table

Table 58. KW47 Package pinout...continued

5 ALT0

22 ALT0 -

5.2 Recommended connection for unused analog and digital pins

Table 59. Recommended connection for unused interfaces also be disabled in software. tied to VSS through a 10 kΩ resistor. also be disabled in software. Power VDD_SWITCH Must be powered Powers FRO16 and a portion of RAM. is not used in the application. Table continues on the next page... KW47 All information provided in this document is subject to legal disclaimers. © 2025 NXP B.V. All rights reserved.

Table 59. Recommended connection for unused interfaces...continued

5.3 Pinouts diagram

a single pin. To determine what signals can be used on which pin, see the previous section. KW47 All information provided in this document is subject to legal disclaimers. © 2025 NXP B.V. All rights reserved.

Figure 19. 48-pin HVQFN package pinout diagram

6 Ordering parts

6.1 Determining valid orderable parts

7 Part identification

Part numbers for the device have fields that identify the specific part. Use the values of these fields to determine the specific part. KW47 All information provided in this document is subject to legal disclaimers. © 2025 NXP B.V. All rights reserved.

7.1 Part number format

Table 60. Part number fields descriptions

Z = No Radio PF Product Family • 42 RV Radio Version • Z = Upgradable
0 = Not Applicable (No Radio) FS Flash Size /SRAM • 8 = 1 MB + 512 KB/136 KB + 171 KB
9 = 1 MB + 512 KB/264 KB + 171 KB
B = 2 MB + 512 KB/264 KB + 171 KB SF Sub Feature • 2 = Secure Enclave
3 = Secure Enclave and CAN
6 = Secure Enclave and LCE
7 = Secure Enclave, CAN and LCE T Temperature • A = Automotive, -40 ºC to + 105 ºC (Ta), -40 ºC to + 125 ºC (Tj) SR Silicon Revision • A = Initial Mask Set
B = Production Release Mask Set PT Packaging Type • R = Tape and Reel
T = Tray

7.2 Example

7.3 Package marking information

First line: aaaaaaa
Second line: aaaaaa
Third line: mmmmm NXP Semiconductors KW47 KW47 Product Family KW47 All information provided in this document is subject to legal disclaimers. © 2025 NXP B.V. All rights reserved. Product data sheet Rev. 4 — 18 December 2025 Document feedback

Fourth line: xxxywwxx

Table 61. Package marking

8 Terminology and guidelines

8.1 Definitions

Table 62. Definitions

Operating ratings apply during operation of the chip.
Handling ratings apply when the chip is not powered. Note: The likelihood of permanent chip failure increases rapidly as soon as a characteristic begins to exceed one of its operating ratings. Operating requirement A specified value or range of values for a technical characteristic that you must guarantee during operation to avoid incorrect operation and possibly decreasing the useful life of the chip Operating behavior A specified value or range of values for a technical characteristic that are guaranteed during operation if you meet the operating requirements and any other specified conditions Typical value A specified value for a technical characteristic that:
Lies within the range of values specified by the operating behavior
Is representative of that characteristic during operation when you meet the typical-value conditions or other specified conditions Note: Typical values are provided as design guidelines and are neither tested nor guaranteed. NXP Semiconductors KW47 KW47 Product Family KW47 All information provided in this document is subject to legal disclaimers. © 2025 NXP B.V. All rights reserved. Product data sheet Rev. 4 — 18 December 2025 Document feedback

8.2 Examples

Figure 20. Examples

8.3 Typical-value conditions

8.4 Relationship between ratings and operating requirements

Figure 21. Relationship between ratings and operating requirements

8.5 Guidelines for ratings and operating requirements

Never exceed any of the chip’s ratings.
During normal operation, don’t exceed any of the chip’s operating requirements.
If you must exceed an operating requirement at times other than during normal operation (for example, during power sequencing), limit the duration as much as possible.

9 Abbreviations and acronyms

The following table provides the list of abbreviations and acronyms their definitions. Table 64. Abbreviations and acronyms and their definition Table continues on the next page... KW47 All information provided in this document is subject to legal disclaimers. © 2025 NXP B.V. All rights reserved.

Table 64. Abbreviations and acronyms and their definition...continued Table continues on the next page... KW47 All information provided in this document is subject to legal disclaimers. © 2025 NXP B.V. All rights reserved.

The following table provides a revision history for this document. Table 65. Revision History KW47 All information provided in this document is subject to legal disclaimers. © 2025 NXP B.V. All rights reserved.

Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term 'short data sheet' is explained in section "Definitions". [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL https://www.nxp.com. Definitions Draft — A draft status on a document indicates that the content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included in a draft version of a document and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. NXP Semiconductors KW47 KW47 Product Family KW47 All information provided in this document is subject to legal disclaimers. © 2025 NXP B.V. All rights reserved. Product data sheet Rev. 4 — 18 December 2025 Document feedback

Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at https://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 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Notice: All referenced brands, product names, service names, and trademarks are the property of their respective owners. NXP — wordmark and logo are trademarks of NXP B.V. AMBA, Arm, Arm7, Arm7TDMI, Arm9, Arm11, Artisan, big.LITTLE, Cordio, CoreLink, CoreSight, Cortex, DesignStart, DynamIQ, Jazelle, Keil, Mali, Mbed, Mbed Enabled, NEON, POP, RealView, SecurCore, Socrates, Thumb, TrustZone, ULINK, ULINK2, ULINK-ME, ULINK-PLUS, ULINKpro, μVision, Versatile — are trademarks and/or registered trademarks of Arm Limited (or its subsidiaries or affiliates) in the US and/or elsewhere. The related technology may be protected by any or all of patents, copyrights, designs and trade secrets. All rights reserved. EdgeLock — is a trademark of NXP B.V. I2C-bus — logo is a trademark of NXP B.V. NXP Semiconductors KW47 KW47 Product Family KW47 All information provided in this document is subject to legal disclaimers. © 2025 NXP B.V. All rights reserved. Product data sheet Rev. 4 — 18 December 2025 Document feedback

Please be aware that important notices concerning this document and the product(s) described herein, have been included in section 'Legal information'. © 2025 NXP B.V. All rights reserved. For more information, please visit: https://www.nxp.com Date of release: 18 December 2025 Document identifier: KW47

Product Information

KW47B42ZBXAFTBX specifications and overview.

Summary

KW47 Product Family Rev. 4- 18 December 2025

Description

KW47 Product Family Rev. 4- 18 December 2025

Source title KW47B42ZBXAFTBX Datasheet(PDF) - NXP Semiconductors

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