Microcontroller

KW45Z

NXP Semiconductors

Highly Secure, Bluetooth Low Energy 5.3 Wireless MCU with CAN FD Rev. 9 - 12/2022

Manufacturer: NXP Semiconductors

Document: 94 Pages / 1Mb

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Document overview

Manufacturer or author: NXP Semiconductors
PDF pages: 94

Technical content

Datasheet sections

1 Ratings
1.1 Thermal handling ratings
1.2 Moisture handling ratings
1.3 ESD and Latch-Up Ratings
1.4 Voltage and current maximum ratings
1.5 Required Power-On-Reset (POR) Sequencing
1.6 Power Sequence
2 General
2.1 AC electrical characteristics
2.2 Nonswitching electrical specifications
2.2.2 HVD, LVD, and POR operating requirements
2.2.3 Voltage and current operating behaviors
2.2.4 On-chip regulator electrical specifications
2.2.4.1 DCDC converter specifications
2.2.4.2 LDO_SYS electrical specifications
2.2.4.3 LDO_CORE electrical specifications
2.2.5 Smart power switch
2.2.7 Power consumption operating behaviors
2.2.7.1 Power Consumption Operating Behaviors
2.2.7.2 SoC Power Consumption
2.2.7.3 Typical power-down mode RAM current adders
2.2.7.4 Low power mode peripheral power
2.2.8 EMC radiated emissions operating behaviors
2.2.9 Designing with radiated emissions in mind
2.2.10 Capacitance attributes
2.3 Switching specifications
2.3.1 Device clock specifications
2.3.2 General switching specifications
2.4 Thermal specifications
2.4.1 Thermal operating requirements
2.4.2 Thermal attributes
3 Peripheral operating requirements and behaviors
3.1 Core modules
3.1.1 SWD electricals
3.2 Clock modules
3.2.1 Reference oscillator specification
3.2.3 Free-running oscillator FRO-192M
3.2.4 Free-running oscillator FRO-6M specifications
3.2.5 Free-running oscillator FRO-32K specifications
3.2.6 Free-running oscillator FRO-16K specifications
3.3 Memories and memory interfaces
3.3.1 Flash electrical specifications
3.3.1.1 Flash Read wait state control specifications
3.3.1.2 Flash timing specifications
3.3.1.3 Flash high voltage current behavior
3.3.1.4 Flash reliability specifications
3.4 Radio modules
3.4.2 Receiver Feature Summary
3.4.3 Transmit and PLL Feature Summary
3.5 Analog
3.5.1 ADC electrical specifications
3.5.3 Voltage reference electrical specifications
3.6 Timers
3.7 Communication interfaces
3.7.1 LPUART
3.7.2 LPSPI switching specifications
3.7.3 Inter-Integrated Circuit Interface (I2C)
3.7.4 Improved Inter-Integrated Circuit Interface
3.7.5 CAN switching specifications
3.8 Human Machine Interface (HMI) modules
3.8.1 General Purpose Input/Output (GPIO)
3.8.2 Flexible IO controller (FlexIO)
4 Package dimensions
4.1 Obtaining package dimensions
5 Pinout
5.1 Pinout Table
5.2 Recommended connection for unused analog
5.3 Pinouts diagram
6 Ordering parts
6.1 Determining valid orderable parts
7 Part identification
7.1 Part number format
7.2 Example
7.3 Package marking
7.3.1 Package marking information
8 Terminology and guidelines
8.1 Definitions
8.2 Examples

The KW45 product family is a low-power, highly secure, single-chip wireless MCU that integrates a high performance Bluetooth Low Energy version 5.3 radio and CAN FD for Automotive and Industrial applications. The family integrates a state-of-the-art, scalable security architecture including Arm TrustZone -M, a resource domain controller, and an isolated EdgeLock™ Secure Enclave supporting hardware cryptographic accelerators, random number generators and key generation, storage and management and secure debug. Flash memory contents can optionally be stored as encrypted data and then decrypted on-the-fly enabling protection of sensitive data and algorithms. For automotive applications, an integrated FlexCAN supporting CAN and CAN FD compliant with the ISO 11898-1 standard. The on-chip, low-power UARTs have LIN capabilities. The family is AEC-Q100 Grade 2 automotive certified, with an extended ambient operating temperature range up to +105 °C, MISRA C:2012, and Automotive SPICE (ASPICE) process compliant. Application core

Up to 96 MHz Arm Cortex®-M33 core
Up to 1 MB flash memory
128 KB SRAM
TrustZone-M, IEEE 754 FPU, DSP, MPU, NVIC, SysTick
8 KB Code Cache to improve performance and efficiency
Secure Boot ROM Target applications
Automotive — Secure Car Access — Keyless Entry — Passive Entry/Passive Start (PEPS) Systems — Wireless Battery Management Systems (WBMS)
Industrial/IoT — Positioning/Localization — Building Control and Monitoring — Process/Factory Automation Bluetooth Low Energy radio core
Dedicated CM3 core running at up to 64 MHz
256 kB Flash supporting upgradable software radio
88 KB SRAM optimized for link layer support
Up to 24 simultaneous connections
–106 dBm 125 kbps Long Range Receive Sensitivity
–102 dBm 500 kbps Long Range Receive Sensitivity
–97.5 dBm 1 Mbps Receive Sensitivity
–95 dBm 2 Mbps Receiver Sensitivity
Programmable Transmit Output Power up to +10 dBm
Data Rates: 125 kbps, 500 kbps, 1 Mbps, and 2 Mbps
Modulation Types: 2 Level FSK, GFSK, MSK, GMSK
Integrated memories in radio containing Bluetooth LE Controller Stack and radio drivers
On-chip balun with single ended bidirectional RF port
Low external component counts for low cost, small form- factor designs Table continues on the next page... KW45B41Zx2AFxBx KW45B41Zx3AFxBx KW45Z410x2AFxBx KW45Z410x3AFxBx 40HVQFN 6 x 6 x 0.85 mm Pitch 0.5 mm Wettable Flanks 48HVQFN 7 x 7 x 0.85 mm Pitch 0.5 mm Wettable Flanks KW45B (radio) and KW45Z (MCU) KW45 Product Family Highly Secure, Bluetooth Low Energy 5.3 Wireless MCU with CAN FD Rev. 9 — 12/2022 Data Sheet: Technical Data NXP reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. General Business Information

— Access Control EdgeLock Secure Enclave

Secure boot and debug
Trusted resource domain controller (TRDC) providing programmable control mechanisms for independent processing domains including embedded memory and peripherals — Privilege/user — Data only — Execute only — Read-only access — Secure/Non-secure Advanced flash access protection — Write/Erase protection, Execute only, Data only access control — Optional encryption and on-the-fly decryption using a PRINCE XEX block cipher mode
Hardware encryption and decryption — Symmetric Key Encryption ◦ AES-128/192/256 ◦ ECB, CBC, CTR, GCM, CMAC, and CCM Modes — Asymmetric Key Encryption ◦ ECC NIST P–192/224/256/384/521 ◦ Curve25519 — Key Exchange Algorithms ◦ ECDH(E) ◦ SPAKE2+ ◦ JPAKE — Digital Signature Algorithms ◦ ECDSA ◦ Ed25519 — Hash Algorithms ◦ SHA2-224/256/384/512 ◦ Poly1305
Secure key generation, storage, and management Safety
Memory Protection Unit (MPU)
Register write protection
Illegal memory access
Flash area protection
SRAM Error Correction Code (ECC) and SRAM parity error check
Clock Frequency Accuracy Measurement Circuit (CAC) using Signal Frequency Analyzer (SFA) module
Cyclic Redundancy Check (CRC) calculator
Two internal, independent and one external watchdog timer
Clock loss detection
Main oscillator stop detection (Loss of lock detection)
Low voltage / high voltage detection Low-power consumption (DCDC 3.6 V, 25 ºC)
Typical active core current: <5.3 mA at 96 MHz (<55 μA/ MHz)
Transceiver current (DC-DC buck mode, 3.3 V supply) — Typical RX: 4.7 mA — Typical TX at 0 dBm: 4.6 mA and 18.7 mA at 10 dBm
Less than 3 μA in power-down mode with real-time clock (RTC) active and 32 KB SRAM retention
Less than 1.5 μA in Deep Power-Down mode with RTC active
Multiple power-down modes supporting currents as low as 300 nA
Ultra-low leakage Smart Power Switch with less than 100 nA sleep current with exit from internal timer or GPIO. Clocks
32 MHz RF crystal oscillator
32.768 kHz crystal oscillator
Internal 192 MHz high frequency free running oscillator providing 48/64/96 MHz clock
Internal low frequency free running oscillator providing 6 MHz clock
Internal low power free running oscillator providing 32 kHz clock Table continues on the next page... NXP Semiconductors KW45 Product Family, Rev. 9, 12/2022 Data Sheet: Technical Data General Business Information 2 / 94

Pseudo (PRNG) and True Random Number Generator (TRNG) with 512-bits entropy supporting NIST SP 800-90A and SP 800-90B
Support for secure over-the-air (OTA) firmware updates
Four digital tamper pins with optional interrupt and seconds timestamp upon trigger
Universally Unique ID (UUID) programmed by NXP during factory programming
24-bit unique IEEE media access control (MAC) subaddress
Factory Root of Trust programming System peripherals
DC/DC converter supporting buck and bypass operating modes
Asynchronous DMA controller with per channel access permissions (secure/non-secure)
Two internal and one external watchdog monitors
Nested vectored interrupt controller
Wake-up unit for power-down modes Timers
Two 6-channel 32-bit timers (TPM) with PWM capability and DMA support
Two 32-bit low-power timers (LPTMR) or pulse counters with compare features
4-channel 32-bit low-power periodic interrupt timer (LPIT) with DMA support
One 56-bit timestamp timer
32-bit seconds real time counter (RTC) with 32-bit alarm and independent power supply
Signal frequency analyzer (SFA) provides facilities for measurement of clock period/frequency as well as time between triggers Input supply voltage options:
Integrated DCDC regulator 1.8–3.6 V providing power to Core_LDO regulator, SYS_LDO regulators, and Radio
Integrated Core_LDO regulator 1.2 V–3.6 V powering the core digital domain
Integrated SYS_LDO regulator 1.71 V to 3.6 V powering the SYS domain
DCDC and Core_LDO regulators can support bypass modes Analog modules
16-bit single ended SAR Analog-to-digital converter (ADC) up to 2 Msps
Two high-speed analog comparators (CMP) with 8-bit digital-to-analog converter (DAC)
1.0 V to 2.1 V Voltage Reference (Vref) Communication interfaces
FlexCAN with CAN and CAN FD supporting the full implementation of the CAN Specification Version 2.0, Part B. FD Support.
Two Low Power UART (LPUART) modules with LIN support
Two Low Power SPI modules and one MIPI-I3C module
Two Low Power I2C (LPI2C) modules supporting the System Management Bus (SMBus) Specification, version
One programmable FlexIO module supporting emulation of UART, I2C, SPI, Camera IF, LCD RGB, PWM/ Waveform generation Human Machine Interface modules
General-purpose input/output (GPIO) Operating characteristics
Temperature range (ambient): –40 °C to 105 °C
Temperature range (junction): –40 °C to 125 °C
DC/DC voltage range: 1.8 V to 3.6 V
Bypass voltage range: 1.8 V to 3.6 V
Qualification: AEC-Q100 Grade 2 NXP Semiconductors KW45 Product Family, Rev. 9, 12/2022 Data Sheet: Technical Data General Business Information 3 / 94

Table 1. Ordering Information of radio parts 1

To confirm current availability of orderable part numbers, go to http://www.nxp.com and perform a part number search.

Table 2. Ordering Information of non-radio parts 1 Table continues on the next page...

Table 2. Ordering Information of non-radio parts 1 (continued)

To confirm current availability of orderable part numbers, go to http://www.nxp.com and perform a part number search.

In case of Tray 7x7 48-pin HVQFN "Wettable" - Minimum Package Quantity is 260 pcs
In case of Tray 6x6 40-pin HVQFN "Wettable" - Minimum Package Quantity is 490 pcs
In case of Tape and Reel 7x7 48-pin and 6x6 40-pin HVQFN "Wettable" - Minimum Package Quantity is 2 kpcs NOTE

Table 3. Device Revision Number Table 4. Related Resources structure and function (operation) of a device. for a particular device mask set. Table continues on the next page...

Table 4. Related Resources (continued)

40 HVQFN:SOT618-13(DD) RTC OSC-RTC REGFILE-RTC (x2) FRO-32K TRDC TSTMR 56-bit VREF PRINCE TPM 6-ch 32-bit (x2) LPIT 4-ch 32-bit LPCMP (x2) LPTMR 32-bit (x2) 16-bit ADC LPUART w/LIN (x2) CRC LPSPI (x2) SECURITY PORT (A-D) SRAM (128 KB) I3C LPI2C (x2) GPIO (A-D) Secure Boot ROM SFA FMU SCG

1 MB Flash

96 MHz

Figure 1. KW45 block diagram

8.4 Relationship between ratings and operating

8.5 Guidelines for ratings and operating

1 Ratings

1.1 Thermal handling ratings

Table 5. Thermal handling ratings

Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic

Solid State Surface Mount Devices.

1.2 Moisture handling ratings

Table 6. Moisture handling ratings

Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic

Solid State Surface Mount Devices.

1.3 ESD and Latch-Up Ratings

Table 7. ESD and Latch-Up Ratings

Determined according to JEDEC Standard JS-001-2017, For Electrostatic Discharge (ESD) Sensitivity Testing, Human

Body Model (HBM) - Component Level.

Determined according to JEDEC Standard JS-002-2018, For Electrostatic Discharge (ESD) Sensitivity Testing, Charged-

Device Model (CDM) - Device Level .

Determined according to JEDEC Standard JESD78F, IC Latch-Up Test.

1.4 Voltage and current maximum ratings

Table 8. Voltage and current maximum ratings Table continues on the next page...

Table 8. Voltage and current maximum ratings (continued)

The part supports 2.75 V for up to 20 s over lifetime to allow fuse programming
The Max. of the VIN cannot be greater than the voltage applied to the VDD_IO_x.
Current loading is less than 40 mA

1.5 Required Power-On-Reset (POR) Sequencing

inputs on power-up must not exceed VDD voltage maximums.

Figure 2. VDD_CORE/VDD_IO_ABC Powering Sequence

1.6 Power Sequence

Table 9. Power Sequence

All domains can be powered at the same time. If external sources are used, make sure they start at the same time or they

follow the order in the sequence.

2 General

2.1 AC electrical characteristics

20 % and 80 % points, as shown in the following figure.

Figure 3. Input signal measurement reference

2.2 Nonswitching electrical specifications

2.2.1 Voltage and current operating requirements

Table 10. Voltage and current operating requirements

Normal mode
Fuse Programming 1.8 2.25 1.98 2.75 V VDD_DCDC Supply voltage DCDC regulator 1.8 3.6 V 1 VDD_IO_D Supply voltage for LDO_SYS regulator, PortD 1.86 3.6 V 2 VDD_LDO_ CORE Supply voltage for LDO_CORE regulator 1.25 3.6 V VDD_RF Supply voltage for OSC and radio analog 1.175 3.6 V VPA_2P4GH z Supply voltage for 2.4 GHz radio power amplifier 0.9 2.4 V VDD_IO_AB C Supply voltage for PortA, PortB, Port C, and CMPs 1.71 3.6 V 3 VDD_ANA Supply voltage for ADC, DAC, and VREF 1.71 3.6 V VSS - VSS_ANA VSS-to-VSS_ANA differential voltage –0.1 0.1 V VIH Input high voltage
1.71 V ≤ VDD_IO_ABC ≤ 3.6 V
1.86 V ≤ VDD_IO_D ≤ 3.6 V 0.7 × VDD_I O_ABC V Table continues on the next page... NXP Semiconductors General KW45 Product Family, Rev. 9, 12/2022 Data Sheet: Technical Data General Business Information 12 / 94

Table 10. Voltage and current operating requirements (continued)

1.71 V ≤ VDD_IO_ABC ≤ 3.6 V
1.86 V ≤ VDD_IO_D ≤ 3.6 V 0.3 × VDD_I O_ABC 0.3 × VDD_I O_D V VHYS Input hysteresis 0.1 × VDD_I O_X — V IICIO IO pin DC injection current — single pin
VIN < VSS – 0.3 V (negative current injection)
VIN > VDD + 0.3 V (positive current injection) mA 5, 6 VODPU Open drain pullup voltage level VDD_IO_X VDD_IO_X V 7 1. If DCDC is unused, then input supply should be tied to GND through a 10 kΩ resistor. 2. When LDO_SYS is bypassed, the input supply voltage is 1.8 V to 1.98 V and VDD_IO_D must be externally connected to VDD_SYS 3. If none of the PortA, PortB, and PortC pins are being used, then the VDD_IO_ABC can be left floating. 4. VIH and VIL for PTD0 are based of VDD_SYS instead of VDD_IO_D 5. All I/O pins are internally clamped to VSS and VDD_IO_x through an ESD protection diode. If VIN is greater than VDD_IO_x_MIN(= VSS – 0.3 V) or is less than VDD_IO_x_MAX(= VDD + 0.3 V), then there is no need to provide current limiting resistors at the pads. If this limit cannot be observed, then a current limiting resistor is required. 6. This device does not allow pin injection current. User must ensure that VIN is kept within the Voltage Maximum Ratings. 7. Open drain outputs must be pulled to whichever supply voltage corresponds to that IO, VDD_IO_X as appropriate.

2.2.2 HVD, LVD, and POR operating requirements

VDD_IO_ABC
VDD_CORE
VDD_SYS For VDD_SYS, it has Power-on-reset (POR) power supervisor circuits.

Table 11. VDD_IO_ABC supply HVD, LVD, and POR Operating Ratings Table continues on the next page...

Table 11. VDD_IO_ABC supply HVD, LVD, and POR Operating Ratings (continued) Table 12. VDD_CORE supply HVD and LVD Operating Ratings

Same value applies to all conditions.

Table 13. VDD_SYS supply HVD and LVD Operating Ratings Table continues on the next page...

Table 13. VDD_SYS supply HVD and LVD Operating Ratings (continued)

When fuses are being programmed VDD_SYS is raised to 2.5 V nominal. This is outside the HVD bounds, so HVD

2.2.3 Voltage and current operating behaviors

Table 14. Voltage and current operating behaviors

2.7 V ≤ VDD_IO_X ≤ 3.6 V, IOH = 4 mA
1.71 V ≤ VDD_IO_ABC < 2.7 V, IOH = 2.5 mA
1.86 V ≤ VDD_IO_D < 2.7 V, IOH = 2.5 mA VDD_IO_X – 0.5 — — V VOH Output high voltage — High drive strength
2.7 V ≤ VDD_IO_X ≤ 3.6 V, IOH = 6 mA
1.71 V ≤ VDD_IO_ABC < 2.7 V, IOH = 3.75 mA
1.86 V ≤ VDD_IO_D < 2.7 V, IOH = 3.75 mA VDD_IO_X – 0.5 — — V 1,2 IOHT Output high current total for all ports — — 100 mA VOL Output low voltage — Normal drive strength
2.7 V ≤ VDD_IO_X ≤ 3.6 V, IOL = 4 mA
1.71 V ≤ VDD_IO_ABC < 2.7 V, IOL = 2.5 mA
1.86 V ≤ VDD_IO_D < 2.7 V, IOH = 2.5 mA — — 0.5 V 1,3 VOL Output low voltage — High drive strength
2.7 V ≤ VDD_IO_X ≤ 3.6 V, IOL = 6 mA — — 0.5 V 1,3,2 Table continues on the next page... NXP Semiconductors General KW45 Product Family, Rev. 9, 12/2022 Data Sheet: Technical Data General Business Information 15 / 94

Table 14. Voltage and current operating behaviors (continued)

1.71 V ≤ VDD_IO_ABC < 2.7 V, IOL = 3.75 mA
1.86 V ≤ VDD_IO_D < 2.7 V, IOL = 3.75 mA IOLT Output low current total for all ports — — 100 mA IIN Input leakage current (per pin) for full temperature range — — 1 μA 4 IIN Input leakage current (per pin) at 25 °C — — 0.025 μA 4 IIN Input leakage current (total all pins) for full temperature range — — 41 μA 4 IOZ Hi-Z (off-state) leakage current (per pin) — — 1 μA RPU Internal pullup resistors 33 50 75 kΩ RPU (I3C) Internal pullup resistors 1.1 2 2.833 kΩ 5 RPD Internal pulldown resistors 33 50 75 kΩ RHPU High-resistance pullup option (PORTx_PCRy[PV] = 1) 0.67 — 1.5 MΩ 6 RHPD High-resistance pulldown option (PORTx_PCRy[PV] = 1) 0.67 — 1.5 MΩ 6 1. When setting DSE1=1, the same VOH / VOL is met with IOH / IOL doubled. 2. RTC signals are always configured in high drive mode 3. Open drain outputs must be pulled to VDD_IO_X. 4. Measured at VDD_IO_X = 3.6 V. 5. Only I3C pins support this option 6. Only Port D pins support this option.

2.2.4 On-chip regulator electrical specifications

2.2.4.1 DCDC converter specifications

Table 15. DCDC Converter Specifications

Normal drive strength
Low drive strength
SPC_DCD_CFG[FREQ_CNTRL_ON]=1 105 mA mA mA 1, 3 LX DCDC inductor value 0.47 1 2.2 µH 4 ESR External inductor equivalent series resistance — 110 — mΩ 5 Table continues on the next page... NXP Semiconductors General KW45 Product Family, Rev. 9, 12/2022 Data Sheet: Technical Data General Business Information 16 / 94

Table 15. DCDC Converter Specifications (continued)

In normal drive strength
In low drive strength mV fburst DCDC burst frequency 3 5 8 MHz 7 fburst_acc DCDC burst frequency accuracy — 10 — % 7 1. The system DCDC converter generates 1.8 V at DCDC_LX by default. The DCDC can be used to power VDD_RF, VDD_LDO_CORE, and external components as long as the max ILOAD is not exceeded. 2. The VDD_DCDC input supply to DCDC must be at least 500 mV higher than the desired output at DCDC_LX. 3. The maximum load current during boot up shall not exceed 60 mA. 4. Recommended inductor value is 1 µH to 1.5 µH. If the inductor is < 1 µH, the DCDC efficiency is not guaranteed 5. The maximum recommended ESR is 250 mΩ (not a hard limit). 6. The variation in capacitance of the capacitor at DCDC_LX due to aging, temperature, and voltage degradation must not exceed the Min./Max. values. 7. FREQ_CNTRL_ON = 1. NXP Semiconductors General KW45 Product Family, Rev. 9, 12/2022 Data Sheet: Technical Data General Business Information 17 / 94

Figure 4. Efficiency vs Load current in Normal drive

Figure 5. Efficiency vs Load current in Low-power drive

2.2.4.2 LDO_SYS electrical specifications

Table 16. LDO_SYS electrical specifications

LDO_SYS input supply voltage (Regulation mode)
LDO_SYS input supply voltage (Bypass mode)
Fuse programming mode 1.86 1.8 2.75 3.6 1.98 3.6 V 1 VOUT_SYS LDO_SYS regulator output voltage
Normal drive mode
Fuse Programming mode 1.71 2.25 1.8 2.5 1.98 2.75 V 2,3,4,5 ILOAD LDO_SYS maximum load current Table continues on the next page... NXP Semiconductors General KW45 Product Family, Rev. 9, 12/2022 Data Sheet: Technical Data General Business Information 19 / 94

Table 16. LDO_SYS electrical specifications (continued)

Normal drive mode
Low drive mode
Fuse programming mode mA mA mA IDD LDO_SYS power consumption
Normal drive mode
Low drive mode 100 μA nA COUT External output capacitor — 1.5 10 μF CDEC External output decoupling capacitor — 0.1 — μF ESR External output capacitor equivalent series resistance — 30 — mΩ IINRUSH LDO_SYS inrush current — — 120 mA 7 1. Regulator will automatically switch to passthrough (means the regulator driver is fully ON) with the supply is below 1.95 V. 2. The LDO_SYS converter generates 1.8 V by default at VOUT_SYS. VOUT_SYS can be used to power VDD_SYS, VDD_RF, VDD_IO_X, VDD_ANA, and external components as long as the max ILOAD is not exceeded. 3. VOUT_SYS and VDD_SYS are connected together. 4. VDD_IO_D must be at least 150 mV higher than the desired VOUT_SYS. 5. LDO_SYS can be used to program efuse and in this configuration the output voltage can range between 2.25 V and 2.75 V 6. In normal drive strength, LDO_SYS draws ~100 μA for every 20 mA of load current. 7. This is for 1.5 μF external output capacitor. If the capacitor has 10 μF value, this value should be 300 mA instead.

2.2.4.3 LDO_CORE electrical specifications

Table 17. LDO_CORE electrical specifications

Normal drive strength
Low drive strength 1.0 1.0 1.15 1.15 V ILOAD LDO_CORE max load current
Normal mode - VDD_LDO_CORE ≥ 1.5 V
Normal mode - VDD_LDO_CORE < 1.5 V
Low-power mode - VDD_LDO_CORE ≥ 1.5 V
Low-power mode - VDD_LDO_CORE < 1.5 V mA Table continues on the next page... NXP Semiconductors General KW45 Product Family, Rev. 9, 12/2022 Data Sheet: Technical Data General Business Information 20 / 94

Table 17. LDO_CORE electrical specifications (continued)

Normal drive strength - VDD_LDO_CORE ≥ 1.5 V
Normal drive strength - VDD_LDO_CORE < 1.5 V
Low drive strength - VDD_LDO_CORE ≥ 1.5 V
Low drive strength - VDD_LDO_CORE < 1.5 V 150 0.05 0.05 μA IINRUSH LDO_CORE inrush current — — 5 x ILOAD mA 1. To bypass LDO_CORE, tie VDD_LDO_CORE to VDD_CORE 2. The VDD_LDO_CORE input supply must also be at least 250 mV higher than the desired output at VOUT_CORE. 3. In normal drive strength, LDO_CORE draws ~40 μA for every 20 mA of load current. In low drive strength, LDO_CORE draws ~50 nA for every 100 μA of load current.

Table 18. LDO_CORE external device electrical specifications

2.2.5 Smart power switch

SWITCH_WAKEUP_B pulldown voltage is 0.7 V, duration time should be larger than 1 µs. Table 19. Smart power switch

2.2.6 Power mode transition operating behaviors

Table 20. Power mode transition operating behaviors

2.2.7 Power consumption operating behaviors

by each power domain in the corresponding KW45 power mode configuration.

Specifications below only include power for the MCU itself
On top of the device’s IDD current consumption, external loads applied to pins of the device need to be considered
Efficiency of regulators (on-chip or off-chip) used to generate supply voltages should be considered The maximum values stated in the following sections represent characterized results equivalent to the mean plus three times the standard deviation (mean + 6 sigma).

2.2.7.1 Power Consumption Operating Behaviors

Table 21. Power Consumption Operating Behaviors Table continues on the next page...

Table 21. Power Consumption Operating Behaviors (continued) Table continues on the next page...

Table continues on the next page...

All regulators are disabled. Voltages are come from external supplies. External 3.3V supply for VDD_SWITCH, VDD_ANA,
All regulators are disabled. Voltages are come from external supplies. External 3.3V supply for VDD_SWITCH, VDD_ANA,
8 KB of retained RAM correspond to the last RAM block and is powered by the standby LDO in smart power switch domain
External 3.3 V supply to Smart Power Switch. Power switch output connected to DCDC_IN, LDO_SYS, VDD_ANA, VDD_IO_D

2.2.7.2 SoC Power Consumption

Table 22. SoC POwer Consumption

2.2.7.3 Typical power-down mode RAM current adders

currents are measured in power-down mode, but RAM adder should be similar for other modes. Table 23. Typical power-down mode RAM current adders Table continues on the next page...

Table 23. Typical power-down mode RAM current adders (continued)

2.2.7.4 Low power mode peripheral power consumption adders

Table 24. Low power mode peripheral power consumption adders Table continues on the next page...

Table 24. Low power mode peripheral power consumption adders (continued) generating the clock signal. Table continues on the next page...

Table continues on the next page...

2.2.8 EMC radiated emissions operating behaviors

EMC measurements to IC-level IEC standards are available from NXP on request.

2.2.9 Designing with radiated emissions in mind

Go to https://www.nxp.com/.
Perform a keyword search for “EMC design”.

2.2.10 Capacitance attributes

Table 25. Capacitance attributes

2.3 Switching specifications

2.3.1 Device clock specifications

Table 26. Device clock specifications By default, VDD_CORE = 1.0 V, fCPU_CLK/fBUS_CLK = 32 MHz, fSLOW_CLK = 16 MHz.

2.3.2 General switching specifications

Table 27. General switching specifications

1.71 ≤ VDD_IO_x < 2.7 V — Fast slew rate (SRE = 0; DSE = 1) — Slow slew rate (SRE = 1; DSE = 1) 2.9 2.4 6.1 ns ns ns ns Fast I/O pins — Fast slew rate (SRE = 0; DSE = 0) — Slow slew rate (SRE = 1; DSE = 0)
1.71 ≤ VDD_IO_x < 2.7 V — Fast slew rate (SRE = 0; DSE = 1) — Slow slew rate (SRE = 1; DSE = 1) 0.6 0.8 0.4 0.6 1.6 1.8 1.6 1.9 ns ns ns ns I2C/I3C I/O pins — Normal drive, fast slew rate (SRE = 0; DSE = ) — Normal drive, slow slew rate (SRE = 1; DSE = 0) — High drive, fast slew rate (SRE = 0; DSE = 1) — High drive, slow slew rate (SRE = 1; DSE = 1)
1.71 ≤ VDD_IO_x < 2.7 V 6.1 2.8 5.6 ns ns ns ns Table continues on the next page... NXP Semiconductors General KW45 Product Family, Rev. 9, 12/2022 Data Sheet: Technical Data General Business Information 32 / 94

Table 27. General switching specifications (continued)

1.71 ≤ VDD_IO_x < 2.7 V 3.3 4.3 6.7 ns ns 1. The synchronous and asynchronous timing must be met. 2. This is the shortest pulse that is guaranteed to be recognized. 3. Load is 25 pF. Drive strength and slew rate are configured using PORTx_PCRn[DSE] and PORTx_PCRn[SRE]. 4. These are effectively Port C pins. 5. Load is 25 pF for DSE=0 or DSE=1. Load is 50 pF for DSE=2 or DSE=3. Drive strength and slew rate are configured using PORTx_PCRn[DSE1], PORTx_PCRn[DSE], and PORTx_PCRn[SRE]. 6. Load is 25 pF.

2.4 Thermal specifications

2.4.1 Thermal operating requirements

Table 28. Thermal operating requirements

Maximum TA can be met only if the user ensures that TJ does not exceed the maximum. The simplest method to determine

TJ is: TJ = TA + RθJA × chip power dissipation.

2.4.2 Thermal attributes

Table 29. Thermal attributes

Thermal test board meets JEDEC specification for this package (JESD51-7).
Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions

—Natural Convection (Still Air).

3 Peripheral operating requirements and behaviors

3.1 Core modules

3.1.1 SWD electricals

Table 30. SWD timing Figure 6. Serial wire clock input timing

Figure 7. Serial wire data timing

3.2 Clock modules

3.2.1 Reference oscillator specification

temperature, mechanical, and aging excursions. The table below shows typical specifications for the Crystal Oscillator. Table 31. Reference Crystal Specification Table continues on the next page...

Table 31. Reference Crystal Specification (continued)

Full temperature range of this device. A reduced range can be chosen to meet application needs.
Recommended crystal specification.
Combination of frequency stability variation over desired temperature range and frequency variation due to aging over
Variation due to temperature, process, and aging of MCU.
Sum of crystal initial frequency tolerance, crystal frequency stability and aging, oscillator variation, and PCB manufacturing

variation must not exceed this value.

Typical is target. 30 % tolerances shown.
Time from oscillator enables to clock ready. Dependent on the complete hardware configuration of the oscillator.

Figure 8. Crystal Electrical Block Diagram

Table 32. 32 kHz oscillator electrical specifications

Period jitter (RMS)
Accumulated jitter over 1 ms (RMS) ns ESR Crystal equivalent series resistance — — 80/150 kΩ 1 Cpara Parasitic capacitance of EXTAL32 and XTAL32 — 1 2 pF tstart Crystal start-up time — 1000 8000 ms 2 IOSC_32k Current consumption
OFF mode
ON mode 0.5 100 — nA Vpp Peak-to-peak amplitude of oscillation — 0.2 — V 3 fec_extal32 Externally provided input clock frequency — 32.768 — kHz 4 vec_extal32 Externally provided input clock amplitude — VDD_SYS — mV 4, 5 Cextal/xtal EXTAL, XTAL Load Capacitance 0 — 30 pF 6 1. Maximum value is 80 kOhms for parasitic capacitances higher than 1 pF, and 150 kOhms for parasitic capacitances around 1 pF. 2. Proper PC board layout procedures must be followed to achieve specifications. 3. When a crystal is being used with the 32 kHz oscillator, the EXTAL32 and XTAL32 pins should only be connected to required oscillator components and must not be connected to any other devices. 4. This specification is for an externally supplied clock driven to EXTAL32 and does not apply to any other clock input. The oscillator remains enabled and XTAL32 must be left unconnected. 5. The parameter specified is a peak-to-peak value and VIH and VIL specifications do not apply. The voltage of the applied clock must be within the range of VSS to VDD_IO_D. 6. With 2 pF steps. It is recommended that the oscillator margin be measured on the actual application PCB with the target crystal. NOTE

3.2.3 Free-running oscillator FRO-192M specifications

Table 33. FRO-192M specifications

Open loop — ±0.25 Table continues on the next page... NXP Semiconductors Peripheral operating requirements and behaviors KW45 Product Family, Rev. 9, 12/2022 Data Sheet: Technical Data General Business Information 37 / 94

Table 33. FRO-192M specifications (continued)

Closed loop (using accurate clock source as reference) tstartup Start-up time
Oscillation time with initial accuracy of ±20 % to ±2 % of enable signal assertion
Oscillation time within ±2 % from enable signal assertion μs μs fos Frequency overshoot during startup — — 2 % jitper • Period jitter RMS 1
Accumulated jitter over 1 μs 375 ps jitcyc Cycle to Cycle jitter RMS — 60 — ps Ifro192m Current consumption — 40 100 μA 1. Reference clock = 192 MHz.

3.2.4 Free-running oscillator FRO-6M specifications

Table 34. FRO-6M specifications

open loop
closed loop (using accurate clock source as reference) ±0.6 tstartup Start-up time
Oscillation time with initial accuracy of -20 % to +2 % of enable signal assertion
Oscillation time within ± 2 % from enable signal assertion μs μs fos Frequency overshoot during startup — 10 — % Ifro6m Current consumption — — 4 μA

3.2.5 Free-running oscillator FRO-32K specifications

Table 35. FRO-32K specifications Table continues on the next page...

Table 35. FRO-32K specifications (continued)

open loop — — ±2 % TRIMstep Trimming step — 0.03 — % tstartup Start-up time — — 120 μs fos Frequency overshoot during startup
Trimmed — 10 — % Ifro32k Current consumption — 350 — nA

3.2.6 Free-running oscillator FRO-16K specifications

Table 36. FRO-16K specifications

Over –40 °C~125 °C temperature range — — ±6 % TRIMstep Frequency trimming step — 1.5 — % Ifro16k Current consumption — 50 — nA 2 Ipor Current consumption — 26 — nA 1. FRO-16K is in Power Switch block, which is powered by min 1.9 V VDD_SWITCH 2. The Typical value (70 nA) of current consumption includes 20 nA POR current consumption in stable running period.

3.3 Memories and memory interfaces

3.3.1 Flash electrical specifications

This section describes the electrical characteristics of the flash memory module.

3.3.1.1 Flash Read wait state control specifications

and low-power modes. The following requirements must be met. Table 37. Recommend RWSC settings on KW45 (for MCU flash and Radio Flash) Table continues on the next page...

Table 37. Recommend RWSC settings on KW45 (for MCU flash and Radio Flash) (continued)

3.3.1.2 Flash timing specifications

a command is not included in the following table. Table 38. Flash command time specifications

Time to abort the command may significantly impact the time to execute the command.
Measured from the time PERDY is cleared.

3.3.1.3 Flash high voltage current behavior

Table 39. Flash high voltage current behavior

See the Power Management chapter in the reference manual for the specific VDD_IO_x voltage supply powering the flash

3.3.1.4 Flash reliability specifications

Table 40. Flash reliability specifications

100 K 500 K — cycles 3

Typical data retention values are based on measured response accelerated at high temperature and derated to a constant
Sector cycling endurance represents the number of Program/Erase cycles on a single sector at -40 °C ≤ Tj ≤ 125 °C.
For devices with a single flash block, sectors must be located within the last 256 KB of the flash main memory. For devices

with two flash blocks, sectors must be located within the last 256 KB of each flash main memory.

3.4 Radio modules

Table 41. 2.4 GHz radio transceiver specifications Table continues on the next page...

Table 41. 2.4 GHz radio transceiver specifications (continued)

Voltage required at this rail depends on the desired output power. See Transmit and PLL Feature Summary for the
VPA_2P4GHZ is internally connected to the VDD_RF pin. When not powered externally, VPA_2P4GHZ = VDD_RF - 0.275

V. An internal regulator prevents VPA_2P4GHZ from going above 2.4 V when powered through the VDD_RF pin.

Bluetooth LE. Other modes have different requirements

3.4.2 Receiver Feature Summary

Table 42. Top-level Receiver Specifications (TA = 25 °C, nominal process unless otherwise noted) Table continues on the next page...

Table 42. Top-level Receiver Specifications (TA = 25 °C, nominal process unless otherwise noted) (continued) offset (Wanted signal at –67 dBm, BER < 0.1 %. offset (Wanted signal at –67 dBm, BER < 0.1 %. offset (Wanted signal at –67 dBm, BER < 0.1 %. offset (Wanted signal at –67 dBm, BER < 0.1 %. offset (Wanted signal at –67 dBm, BER < 0.1 %. offset (Wanted signal at –67 dBm, BER < 0.1 %. Table continues on the next page...

offset (Wanted signal at –67 dBm, BER < 0.1 %. offset (Wanted signal at –67 dBm, BER < 0.1 %. offset (Wanted signal at –67 dBm, BER < 0.1 %. offset (Wanted signal at –67 dBm, BER < 0.1 %. ±10 MHz – Wanted signal at –67 dBm, BER < 0.1 %. MHz to 12750 MHz (Wanted signal at –67 dBm, BER < 0. Table continues on the next page...

offset (Wanted signal at –67 dBm, BER < 0.1 %. offset (Wanted signal at –67 dBm, BER < 0.1 %. offset (Wanted signal at –67 dBm, BER < 0.1 %. offset (Wanted signal at –67 dBm, BER < 0.1 %.

All the RX parameters are measured at the RF pins.
Transceiver power consumption.
Variation across temperature (-40 °C to 105 °C) is up to 3 dB.
Receiver noise Figure is computed from RF pin to composite (I+jQ) ADC output
With RSSI_CTRL_0.RSSI_ADJ field calibrated to account for antenna to RF input losses.
With one point calibration over frequency and temperature.

Exceptions allowed for twice the reference clock frequency(fref) multiples.
Measured at 0.1 % BER using 37 byte long packets in maximum gain mode and nominal conditions.
Bluetooth LE adjacent and alternate selectivity performance is measured with modulated interference signals.
Exceptions allowed for multiple of XTAL frequency
Exceptions allowed for carrier frequency sub harmonics.
Exceptions allowed for carrier frequency harmonics.

Table 43. Receiver Specifications with Generic FSK Modulations

Selectivity measured with an unmodulated blocker.
Variation across temperature (-40 °C to 105 °C) is up to 3 dB.

3.4.3 Transmit and PLL Feature Summary

Supports constant envelope modulation of 2.4 GHz ISM frequency band.
Fast PLL Lock time: < 25 µs
Reference Frequency: — 32 MHz crystals supported for Bluetooth LE and Generic FSK modes

Table 44. Top-level Transmitter Specifications (TA = 25 °C, nominal process unless otherwise noted) Table continues on the next page...

Table 44. Top-level Transmitter Specifications (TA = 25 °C, nominal process unless otherwise noted) (continued) Table continues on the next page...

All the TX parameters are measured at test hardware SMA connector.
Transceiver power consumption. NBU running at @16 MHz.
Measured at RF pins, with VPA_2P4GHz ≥ 2.4 V.
Variation across temperature (-40 °C to 105 °C) is up to 3 dB.
Measured at the RF pins single supply configuration VDD_RF = VDD_LDO_CORE = 1.25V
Maximum drift of carrier frequency of the PLL during a Bluetooth LE packet with a nominal 32 MHz reference crystal.
Harmonic levels based on recommended 2 component match for TX output power ≤ 5 dBm. Transmit harmonic levels
Measured at Pout > 5 dBm and recommended high-power TX match.

Figure 9. TX Pout (dBm) as function TX-PA Power Code at RF pins

Table 45. Transmit Output Power as a function of PA_POWER VPA_2P4GHZ = 1 V / 0 dBm output power target Table continues on the next page...

Figure 10. TX Pout (dBm) as function TX-PA Power Code at 7 dBm Table 46. Transmit Output Power as a function of PA_POWER VPA_2P4GHZ = 1.6 V / 7 dBm output power target Table continues on the next page...

Figure 11. TX Pout (dBm) as function TX-PA Power Code at 10 dBm Table 47. Transmit Output Power as a function of PA_POWER VPA_2P4GHZ = 2.2 V / 10 dBm output Table continues on the next page...

Table 47. Transmit Output Power as a function of PA_POWER VPA_2P4GHZ = 2.2 V / 10 dBm output (continued)

3.5 Analog

3.5.1 ADC electrical specifications

Table 48. 16-bit ADC operating conditions Table continues on the next page...

Table 48. 16-bit ADC operating conditions (continued)

Low-power mode (PWRSEL=00)
High-speed 16b mode (PWRSEL = 10)
High-speed 12b mode (PWRSEL = 10) MHz MHz MHz CADIN Input capacitance — 3.7 4.63 pF Cp Parasitic Cap of pad /package — 2 3 pF RAS Analog source resistance (external) — — 5 kΩ 6 RADIN • High-speed dedicated input channel (CH0:3) — VDD_ANA ≥ 1.71 V — VDD_ANA ≥ 2.1 V — VDD_ANA ≥ 2.5 V
Standard external input channel (Ch4:7) — VDD_ANA ≥ 1.71 V — VDD_ANA ≥ 2.1 V — VDD_ANA ≥ 2.5 V
Standard muxed input channel (Ch4:11) — VDD_ANA ≥ 1.71 V — VDD_ANA ≥ 2.1 V — VDD_ANA ≥ 2.5 V 0.95 0.95 0.95 1.35 1.35 1.35 1.65 1.65 1.65 1.7 1.6 1.4 3.25 2.15 1.75 7.25 3.05 2.35 kΩ 7,8 1. Typical values assume VDD_ANA= 3.0 V, Temp = 25 °C, fADCK = 24 MHz, unless otherwise stated. Typical values are for reference only, and are not tested in production. 2. DC potential difference. 3. For devices that do not have a dedicated VREFL and VSS_ANA pins, VREFL and VSS_ANA are tied to VSS internally. 4. If VREFH is less than VDD_ANA, then voltage inputs greater than VREFH but less than VDD_ANA are allowed but result in a full scale conversion result 5. ADC selected inputs and unselected dedicated inputs must not exceed VDD_ANA during an ADC conversion. Unselected muxed inputs may exceed VDD_ANA but must not exceed the IO supply associated with the inputs (VDD_IO_X) when a conversion is in progress. If an ADC input may exceed these levels, then a minimum of 1 K series resistance must be used between the source and the ADC input pin. 6. This resistance is external to MCU. To achieve the best results, the analog source resistance must be kept as low as possible. 7. There are several types of ADC inputs. To see which channels correspond to which type of ADC inputs, see channel index map in reference manual 8. If the input come through a mux in the IO pad, add the IO Mux Resistance Adder value to the resistance for the channel type NXP Semiconductors Peripheral operating requirements and behaviors KW45 Product Family, Rev. 9, 12/2022 Data Sheet: Technical Data General Business Information 54 / 94

Figure 12. ADC input impedance equivalency diagram Table 49. 16-bit ADC characteristics (VREFH = VDD_ANA, VREFL = VSS_ANA)

PWREN=0, Conversions triggered at 1 kS/s
PWREN=1, No Conversions
Low-power, single-ended mode, 6 MHz
Low-power, or dual-SE mode, 6 MHz
Low-power, single-ended mode, 24 MHz
Low-power, or dual-SE mode, 24 MHz
High-speed, single-ended mode, 48 MHz
High-speed, or dual-SE mode, 48 MHz 2.2 160 340 500 415 580 940 1500 215 440 640 530 750 1200 1950 μA μA μA μA μA μA μA μA ITS Temp Sensor Current Adder — 40 50 μA CSMP ADC Sample cycles 3.5 — 131.5 cycles 3 CCONV ADC conversion cycles 24 — 152 cycles CRATE ADC conversion rate — — 0.857 MS/s 4 Table continues on the next page... NXP Semiconductors Peripheral operating requirements and behaviors KW45 Product Family, Rev. 9, 12/2022 Data Sheet: Technical Data General Business Information 55 / 94

Table 49. 16-bit ADC characteristics (VREFH = VDD_ANA, VREFL = VSS_ANA) (continued)

Low-power mode
High-speed mode (16-bits)
High-speed mode (12-bits) 3.16 TSMP_REQ Required Sample Time See equation — — ns 5 TAZ_REQ Required Auto-zero Time
Low-power mode
High-power mode (16-bits)
High-power mode (12-bits) 291.7 72.9 58.3 ns 5 TSMP Sample Time External inputs See equation — — ns 5 TSMP_INT Internal channel sample time 1.5 — — μs 6 DNL Differential non-linearity — ±0.7 +1.4/–0.95 LSB7 8 INL Integral non-linearity — ±2.0 +4.0/–2.0 LSB7 8 ZSE Zero-scale error (VADIN = VREFL) — ±1.0 ±2.0 LSB7 8 FSE Full-scale error (VADIN=V REFH) — ±2.0 +2.0/–8.0 LSB7 8 TUE Total unadjusted error — ±4.0 ±10.0 LSB7 8 ENOB Effective number of bits
Differential mode — 0.5 MS/s — 2 MS/s
Single-ended mode — 0.5 MS/s — 2 MS/s 12.7 12.0 12.4 11.5 13.5 12.7 13.1 12.2 bits 8,9 SINAD Signal-to-noise plus distortion
Differential mode — 0.5 MS/s — 2 MS/s
Single-ended mode — 0.5 MS/s — 2 MS/s dB 8,9 THD Total harmonic distortion 85 92 — dB 8,10 SFDR Spurious free dynamic range 86 94 — dB 8,10 Table continues on the next page... NXP Semiconductors Peripheral operating requirements and behaviors KW45 Product Family, Rev. 9, 12/2022 Data Sheet: Technical Data General Business Information 56 / 94

T=–40 °C to 105 °C
T=–40 °C to 125 °C ±1.5 °C 13 1. Typical values assume VDD_ANA = 3.0 V, Temp = 25 °C, fADCK = 24 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 2. The ADC supply current depends on the ADC conversion clock speed, conversion rate and power mode. Typical value show is at 6 MHz, 24 MHz, and 48 MHz. For lowest power operation, PWRSEL should be set to 00. 3. Must meet minimum TSMP requirement. 4. Maximum conversion rate for high-speed mode is with FADCK = 48 MHz. Maximum conversion rate for low-power mode is FADCK = 24 MHz and 7.5 sample cycles (to meet the minimum auto-zero time requirement). 5. Required sample time is dictated by external components RAS, CAS, internal components RADIN, CADIN, CP, and desired sample accuracy in bits. Calculated it with formula: T SMP_REQ = B*IN(2)*[RAS*(CAS*CP)+ (RAS + R ADIN)* CADIN(typ). Required auto-zero time is for ADC comparator offset cancellation. The chosen sample time should be no less than maximum of the two: TSMP = max(TSMP_REQ,TAZ_REQ). 6. Internal channel inputs are those that do not come from external source (temperature sensor, bandgap). 7. 1 LSB = (VREFH - VREFL)/2N (N=14 bits), for 16-bit specifications, multiply by 4. 8. All accuracy numbers assume the ADC is calibrated with VREFH=VDD_ANA and using a high-speed dedicated input channel. 9. Dynamic results assume Fin = 1 kHz sinewave, AVGS = 0 for 2 MS/s, AVGS = 4 for 0.5 MS/s. 10. Dynamic results assume Fin = 1 kHz sinewave, no averaging. 11. Set the power up delay (PUDLY) according to the ADC start-up time if PWREN=0. 12. Ilkg = leakage current (Refer to pin leakage specification in the packaged device's voltage and current operating ratings). 13. The temperature sensor can be calibrated to a ± 0.5% precision after board assembly by using a 3 temperature calibration flow with accurate ± 0.15 % temperature chamber.

3.5.2 CMP and 8-bit DAC electrical specifications

Table 50. Comparator and 8-bit DAC electrical specifications

High-speed mode (EN=1, HPMD=1)
Normal mode (EN=1, HPMD=0, NPMD=0)
Nano mode (EN=1, HPMD=0, NPMD=1) 200 400 μA μA nA VAIN Analog input voltage VSS_ANA — VDD_ANA V 1 VAIO Analog input offset voltage
High-speed mode
Normal mode mV mV Table continues on the next page... NXP Semiconductors Peripheral operating requirements and behaviors KW45 Product Family, Rev. 9, 12/2022 Data Sheet: Technical Data General Business Information 57 / 94

Table 50. Comparator and 8-bit DAC electrical specifications (continued)

Nano mode — — 40 mV VH Analog comparator hysteresis
CR0[HYSTCTR] = 00
CR0[HYSTCTR] = 01
CR0[HYSTCTR] = 10
CR0[HYSTCTR] = 11 mV mV mV mV tD Propagation delay
High-speed mode, 100 mV overdrive, power > 1.71 V
High-speed mode, 30 mV overdrive, power > 1.71 V
Normal mode, 30 mV overdrive, power > 1.71 V
Nano mode, 30 mV overdrive, power > 1.71 V 600 ns ns ns μs tinit Analog comparator initialization delay — — 40 μs 4 IDAC8b 8-bit DAC current adder (enabled)
High-power mode (EN=1, PMODE=1)
Low-power mode (EN=1, PMODE=0) μA μA INL 8-bit DAC integral non-linearity
Low/High power mode, supply power > 1.71 V –1.0 — +1.0 LSB 5 DNL 8-bit DAC differential non-linearity
Low/High power mode, power > 1.71 V –1.0 — +1.0 LSB 5 1. For devices that do not have a dedicated VSS_ANA pin, VSS_ANA is tied to VSS internally. 2. Typical hysteresis is measured with input voltage range limited to 0.6 to VDD_ANA–0.6 V. 3. Overdrive does not include input offset voltage or hysteresis. 4. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to CMP_DACCR[DACEN], CMP_DACCR[VRSEL], CMP_DACCR[VOSEL], CMP_MUXCR[PSEL], and CMP_MUXCR[MSEL]), and the comparator output settling to a stable level. 5. 1 LSB = Vreference/256. Typical hysteresis NXP Semiconductors Peripheral operating requirements and behaviors KW45 Product Family, Rev. 9, 12/2022 Data Sheet: Technical Data General Business Information 58 / 94

Figure 15. Typical hysteresis vs. Vin level (VDD = 3.3 V, HPMD = 0, NPMD = 1)

3.5.3 Voltage reference electrical specifications

Table 51. VREF operating requirements

CL must be connected to VREFO if the VREFO functionality is being used for either an internal or external reference.

Table 52. VREF operating behaviors

1.0 V low-power reference voltage

Table continues on the next page...

Table 52. VREF operating behaviors (continued)

See the chip's Reference Manual for the appropriate settings of the VREF Status and Control register.
Vvrefo max is also ≤ VDD_ANA - 600 mV.
Load regulation voltage is the difference between the VREFO voltage with no load vs. voltage with defined load.

3.6 Timers

See General switching specifications.

3.7 Communication interfaces

3.7.1 LPUART

See General switching specifications.

3.7.2 LPSPI switching specifications

of the transfer attributes are programmable. The following tables provide timing characteristics for classic SPI timing modes. Table 53. LPSPI master mode timing

LPSPI0
LPSPI1 MHz MHz LP2 SPSCK period 2 x tperiph 2048 x tperiph ns 2 LP3 Enable lead time 1/2 — tperiph 2 LP4 Enable lag time 1/2 — tperiph 2 LP5 Clock (SPSCK) high or low time tSPSCK/2 - 3 tSPSCK/2 ns — LP6 Data setup time (inputs) 8 — ns — LP7 Data hold time (inputs) 0 — ns — LP8 Data valid (after SPSCK edge) — 6 ns — LP9 Data hold time (outputs) 2 — ns — 1. The frequency of operation is also limited to a minimum of fperiph/2048 and a max of fperiph/2, where fperiph is the LPSPI peripheral functional clock. 2. tperiph = 1/fperiph. NXP Semiconductors Peripheral operating requirements and behaviors KW45 Product Family, Rev. 9, 12/2022 Data Sheet: Technical Data General Business Information 61 / 94

Table 54. LPSPI slave mode timing (continued)

The frequency of operation is also limited to a minimum of fperiph/2048 and a max of fperiph/4, where fperiph is the LPSPI

peripheral functional clock.

Time to data active from high-impedance stat.
Hold time to high-impedance state.

Figure 18. LPSPI slave mode timing (CPHA = 0)

Figure 19. LPSPI slave mode timing (CPHA = 1)

3.7.3 Inter-Integrated Circuit Interface (I2C) specifications

Table 55. I 2C timing Hold time (repeated) START condition.

The master mode I2C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves

A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the VIH(min) of the SCL

signal) to bridge the undefined region of the falling edge of SCL.

The maximum tHD; DAT must be met only if the device does not stretch the LOW period (tLOW) of the SCL signal.
Input signal Slew = 10 ns and Output Load = 50 pF
Set-up time in slave-transmitter mode is 1 IPBus clock period, if the TX FIFO is empty.
A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but the requirement tSU; DAT ≥ 250 ns must

1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification) before the SCL line is released.

Cb = total capacitance of the one bus line in pF.

Table 56. I 2C 1 Mbps timing period, the first clock pulse is generated.

Cb = total capacitance of the one bus line in pF. The max Cb value is 50 pF.

Table 57. I2C HS mode timing1 first clock pulse is generated. Table continues on the next page...

Table 57. I2C HS mode timing1 (continued)

Only PTB4/5, PTA18/19, PTC0/1, PTC4/5 pin can support Fast+ (3 MHz) mode.
A device must internally provide a data hold time to bridge the undefined part between VIH and VIL of the falling edge of
Cb = total capacitance of the one bus line in pF. The max Cb value is 50 pF.

Figure 20. Timing definition for devices on the I2C bus

3.7.4 Improved Inter-Integrated Circuit Interface (MIPI-I3C) specifications

Unless otherwise specified, MIPI-I3C specifications are timed to/from the VIH and/or VIL signal points. Table 58. MIPI-I3C specifications when communicating with legacy I2C devices Table continues on the next page...

Table 58. MIPI-I3C specifications when communicating with legacy I2C devices (continued)

Cb = total capacitance of the one bus line in pF.

Table 59. MIPI-I3C open drain mode specifications

ENTAS0
ENTAS1
ENTAS2
ENTAS3 38.4 n 38.4 n 38.4 n 38.4 n 1 μ 100 μ 2 m 50 m s s s s tCBP Clock before STOP (P) condition tCAS(min)/2 — ns tMMOverlap Current master to secondary master overlap time during handoff tDIG_OD_L — ns tAVAL Bus available condition 1 — μs tIDLE Bus idle condition 1 — ms tMMLock Time internal where new master not driving SDA low tAVAL — μs 1. Cb = total capacitance of the one bus line in pF.

Table 60. MIPI-I3C push-pull specifications for SDR and HDR-DDR modes Table continues on the next page...

Table 60. MIPI-I3C push-pull specifications for SDR and HDR-DDR modes (continued)

Master mode
Slave mode tCR + 3 and tCF + 3 ns tSU_PP SDA signal setup 3 — — ns tCASr Clock after repeated START (Sr) tCAS (min) — — ns tCBSr Clock before repeated START (Sr) tCAS (min)/2 — — ns Cb Capacitive load per bus line — — 50 pF 1. When communicating with an I3C Device on a mixed Bus, the tDIG_H_MIXED period must be constrained in order to make sure that I2C devices do not interpret I3C signaling as valid I2C signaling. NXP Semiconductors Peripheral operating requirements and behaviors KW45 Product Family, Rev. 9, 12/2022 Data Sheet: Technical Data General Business Information 68 / 94

0.3 X V DD

0.7 X V DD

Figure 21. I3C legacy mode timing Figure 22. tDIG_H and tDIG_L

Figure 23. Timing definition for devices on the I3C bus

3.7.5 CAN switching specifications

See General switching specifications.

3.8 Human Machine Interface (HMI) modules

3.8.1 General Purpose Input/Output (GPIO)

See General switching specifications.

3.8.2 Flexible IO controller (FlexIO)

Table 61. FlexIO Timing Specifications Table continues on the next page...

Table 61. FlexIO Timing Specifications (continued)

Assumes pins muxed on same VDD_IO domain with same load

4 Package dimensions

4.1 Obtaining package dimensions

Package dimensions are provided in package drawings.

5 Pinout

5.1 Pinout Table

Table continues on the next page...

Table continued from the previous page... 48H VQ FN 40H VQ FN Pin Name ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 ALT8 ALT9 ALT1 ALT1 Wake up 7 6 VOUT _SWI TCH VOUT _SWI TCH 8 7 PTA0 PTA0 CMP0 _OUT LPUA RT0_ CTS_ b RF_G PO_1 TPM0 _CH4 FLEXI O0_D SWD_ DIO WUU 0_P0 9 8 PTA1 PTA1 CMP1 _OUT LPUA RT0_ RTS_ b RF_G PO_1 TPM0 _CH5 FLEXI O0_D SWD_ CLK 10 9 PTA4 ADC0 _A10/ CMP0 _IN0 PTA4 RF_G PO_9 TPM0 _CLKI N TRAC E_SW O FLEXI O0_D BOOT _CON FIG WUU 0_P2/ RF_X TAL_ OUT_ ENAB LE1

11 PTA1

_A12 PTA1 LPSPI 0_PC EWM 0_OU T_b LPI2C 0_SC LS TPM0 _CH4 LPUA RT0_ RX RF_G PO_8 FLEXI O0_D RF_N OT_A LLOW ED1 12 10 PTA1 ADC0 _A13 PTA1 LPSPI 0_SIN EWM 0_IN LPI2C 0_SD AS TPM0 _CH5 LPUA RT0_ TX RF_G PO_7 RF_G PO_8 FLEXI O0_D RF_E XT_X TAL_ REQU EST/ RF_G PO_7 WUU 0_P3/ RF_N OT_A LLOW ED1 13 11 PTA1 CMP1 _IN1 PTA1 LPSPI 0_SO UT LPUA RT0_ CTS_ b LPI2C 0_SD A TPM0 _CH3 RF_G PO_0 LPUA RT0_ RX SPC0 _LPR EQ 14 12 PTA1 CMP1 _IN0/ PTA1 LPSPI 0_SC K LPUA RT0_ RTS_ b LPI2C 0_SC L TPM0 _CH2 RF_G PO_1 WUU 0_P4 15 13 VDD_ LDO_ CORE VDD_ LDO_ CORE Table continues on the next page... NXP Semiconductors Pinout KW45 Product Family, Rev. 9, 12/2022 Data Sheet: Technical Data General Business Information 72 / 94

Table continued from the previous page... 48H VQ FN 40H VQ FN Pin Name ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 ALT8 ALT9 ALT1 ALT1 Wake up 16 14 VOUT _COR VDD_ CORE VOUT _COR VDD_ CORE 17 15 PTA2 ADC0 _A14/ CMP0 _IN3 PTA2 LPSPI 0_PC LPUA RT0_ TX EWM 0_IN TPM0 _CH1 RF_G PO_2 FLEXI O0_D 18 16 PTA2 ADC0 _A15/ CMP0 _IN2 PTA2 LPSPI 0_PC LPUA RT0_ RX EWM 0_OU T_b TPM0 _CH0 RF_G PO_3 RF_G PO_7 FLEXI O0_D RF_G PO_1 WUU 0_P5 19 17 VSS_ DCDC VSS_ DCDC 20 18 DCDC _LX DCDC _LX 21 19 VDD_I O_D/ VDD_ DCDC VDD_I O_D/ VDD_ DCDC 22 20 VOUT _SYS/ VDD_ SYS VOUT _SYS/ VDD_ SYS 23 21 PTD0 ADC0 _A5 PTD0 RESE T_b

24 PTD1 ADC0

_B5 PTD1 SPC0 _LPR EQ NMI_b RF_G PO_4

25 PTD2 ADC0

_A6 PTD2 LPTM R0_A LT3 TAMP ER0 RF_G PO_5

26 PTD3 ADC0

_B6 PTD3 LPTM R1_A LT3 TAMP ER1 RF_G PO_6 TRG MUX0 _IN2 27 22 PTD4 XTAL 32K PTD4 LPTM R0_A LT2 TAMP ER2 Table continues on the next page... NXP Semiconductors Pinout KW45 Product Family, Rev. 9, 12/2022 Data Sheet: Technical Data General Business Information 73 / 94

Table continued from the previous page... 48H VQ FN 40H VQ FN Pin Name ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 ALT8 ALT9 ALT1 ALT1 Wake up 28 23 PTD5 EXTA L32K PTD5 LPTM R1_A LT2 29 24 VDD_ ANA VDD_ ANA 30 25 VREF O VREF O 49 41 VREF VREF L

31 XTAL

_OUT XTAL _OUT 32 26 XTAL XTAL 33 27 EXTA L EXTA L 34 28 VDD_ RF VDD_ RF 35 29 ANT_ 2P4G HZ1,3 ANT_ 2P4G HZ1 36 30 VPA_ 2P4G HZ1,3 VPA_ 2P4G HZ1

37 PTC0 PTC0 LPSPI

1_PC CAN0 _TX4 I3C0_ SDA TPM1 _CH0 LPI2C 1_SC L FLEXI O0_D WUU 0_P7

38 PTC1 PTC1 LPSPI

1_PC CAN0 _RX4 I3C0_ SCL TPM1 _CH1 LPI2C 1_SD A FLEXI O0_D WUU 0_P8 39 31 PTC2 PTC2 LPSPI 1_SO UT LPUA RT1_ RX LPI2C 1_SC LS TPM1 _CH2 I3C0_ PUR FLEXI O0_D WUU 0_P9 40 32 PTC3 PTC3 LPSPI 1_SC K LPUA RT1_ TX LPI2C 1_SD AS TPM1 _CH3 FLEXI O0_D 41 33 VDD_ CORE VDD_ CORE 42 34 PTC4 PTC4 LPSPI 1_SIN CAN0 _TX4 LPI2C 1_SC L TPM2 _CH0 FLEXI O0_D WUU 0_P10 Table continues on the next page... NXP Semiconductors Pinout KW45 Product Family, Rev. 9, 12/2022 Data Sheet: Technical Data General Business Information 74 / 94

Table continued from the previous page... 48H VQ FN 40H VQ FN Pin Name ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 ALT8 ALT9 ALT1 ALT1 Wake up 43 35 PTC5 PTC5 LPSPI 1_PC CAN0 _RX4 LPI2C 1_SD A TPM1 _CH4 TPM2 _CH1 FLEXI O0_D 44 5 PTC6 ADC0 _A8 PTC6 LPSPI 1_PC TPM1 _CH5 FLEXI O0_D WUU 0_P11 45 36 PTC7 PTC7 TRG MUX0 _IN3 TRG MUX0 _OUT SFA0 _CLK TPM1 _CLKI N TPM2 _CLKI CLKO UT FLEXI O0_D WUU 0_P12 NMI_ RF_N OT_A LLOW ED 1 46 37 PTB0 ADC0 _B10 PTB0 LPSPI 1_PC TPM1 _CH0 FLEXI O0_D WUU 0_P13 47 38 PTB1 ADC0 _B11 PTB1 LPSPI 1_SIN TPM1 _CH1 FLEXI O0_D 48 39 PTB2 ADC0 _B12 PTB2 LPSPI 1_SC K LPUA RT1_ TX TPM1 _CH2 FLEXI O0_D 1 40 PTB3 ADC0 _B13 PTB3 LPSPI 1_SO UT LPUA RT1_ RX TPM1 _CH3 FLEXI O0_D WUU 0_P14 49 41 VSS VSS 1. This signal is not available for the parts without Radio modules. 2. VREF shorts to VSS. 3. For the parts that have no radio modules, this pin is not connected. 4. This signal is not available for the parts without CAN module. 5. PTC6_WUU0_P11 pin signal available only as a wake up source for FlexCAN module on signal CAN0_RX from pin PTC5. Other configuration on PTC6 shall not be used.

5.2 Recommended connection for unused analog and digital pins

Table 62 shows the recommended connections for pins if those pins are not used in the customer's application NXP Semiconductors Pinout KW45 Product Family, Rev. 9, 12/2022 Data Sheet: Technical Data General Business Information 75 / 94

Table 62. Recommended connection for unused interfaces also be disabled in software. also be disabled in software. regulator should also be disabled in software. tied to VSS through a 10 kΩ resistor. should also be disabled in software. Power VDD_SWITCH Must be powered Powers FRO16 and a portion of RAM. Table continues on the next page...

Table 62. Recommended connection for unused interfaces (continued)

5.3 Pinouts diagram

a single pin. To determine what signals can be used on which pin, see the previous section.

Figure 24. 48-pin HVQFN package pinout diagram

Figure 25. 40-pin HVQFN package pinout diagram

6 Ordering parts

6.1 Determining valid orderable parts

7 Part identification

Part numbers for the device have fields that identify the specific part. Use the values of these fields to determine the specific part.

7.1 Part number format

Table 63. Part number fields descriptions

Z = No Radio PF Product Family • 41 R Radio • Z = Upgradable
0 = Not Applicable (No Radio) FS Flash Size • 5 = 512 KB
8 = 1 MB SF Sub Feature • 2 = Secure Enclave
3 = Secure Enclave and CAN T Temperature • A = Automotive, –40 ºC to +105 ºC (Ta), -40 ºC to +125 ºC (Tj)
FT = 48 HVQFN “Wettable”, 7 mm x 7 mm, 0.5p SR Silicon Revision • A = Initial Mask Set
B = Production Release Mask Set PT Packaging Type • R = Tape and Reel
T = Tray

7.2 Example

7.3 Package marking

Table 64. Package marking

Z = No Radio PF Product Family • 41 R Radio • Z = Upgradable
0 = Not Applicable (No Radio) FS Flash Size • 5 = 512 KB
8 = 1MB SF Sub Feature • 2 = Secure Enclave
3 = Secure Enclave and CAN T Temperature • A = Automotive, –40 ºC to +105 ºC (Ta), -40 ºC to +125 ºC (Tj)
FT = 48 HVQFN “Wettable”, 7 mm x 7 mm, 0.5p

7.3.1 Package marking information

First line: aaaaaaa
Second line: aaaaaa
Third line: mmmmm
Fourth line: xxxywwxx

Table 65. Package marking

8 Terminology and guidelines

8.1 Definitions

Rating A minimum or maximum value of a technical characteristic that, if exceeded, may cause permanent chip failure:

Operating ratings apply during operation of the chip.
Handling ratings apply when the chip is not powered. The likelihood of permanent chip failure increases rapidly as soon as a characteristic begins to exceed one of its operating ratings. NOTE Operating requirement A specified value or range of values for a technical characteristic that you must guarantee during operation to avoid incorrect operation and possibly decreasing the useful life of the chip Operating behavior A specified value or range of values for a technical characteristic that are guaranteed during operation if you meet the operating requirements and any other specified conditions Typical value A specified value for a technical characteristic that:
Lies within the range of values specified by the operating behavior
Is representative of that characteristic during operation when you meet the typical-value conditions or other specified conditions Typical values are provided as design guidelines and are neither tested nor guaranteed. NOTE

8.2 Examples

Operating rating: Operating requirement: Operating behavior that includes a typical value: EXAMPLE EXAMPLEEXAMPLE EXAMPLE NXP Semiconductors Terminology and guidelines KW45 Product Family, Rev. 9, 12/2022 Data Sheet: Technical Data General Business Information 82 / 94

8.3 Typical-value conditions

8.4 Relationship between ratings and operating requirements

8.5 Guidelines for ratings and operating requirements

Never exceed any of the chip’s ratings.
During normal operation, don’t exceed any of the chip’s operating requirements.
If you must exceed an operating requirement at times other than during normal operation (for example, during power sequencing), limit the duration as much as possible.

9 Abbreviations and Acronyms

The following table provides the list of abbreviations and acronyms their definitions. Table 66. Abbreviations and Acronyms and their definition Table continues on the next page...

Table 66. Abbreviations and Acronyms and their definition (continued) Table continues on the next page...

The following table provides a revision history for this document. Table 67. Revision History

0 June 2020 Initial internal release

1 September

Editorial updates in the front matter
Updated the partnumber from K32W to KW45 all over the document
Added Device Mask Set Number in Device Revision Number table
Added the package drawing resource in Related Resource Table
Removed VRAM and VDD_IO_X- VDD_ANA from Voltage and current operating requirements
Updated Power consumption operating behaviors table
Updated the description of Δffro6m in FRO-6M specifications table and Δffro32k in FRO-32K specifications table
Updated Ifro16k and added I por in Free-running oscillator FRO-16K specifications
Updated the maximum values in Flash timing specifications
Updated Receiver Specifications with Generic FSK Modulations table
Updated Part number format
Updated LDO_CORE electrical specifications Table continues on the next page... NXP Semiconductors

Revision history

KW45 Product Family, Rev. 9, 12/2022 Data Sheet: Technical Data General Business Information 85 / 94

Table 67. Revision History (continued)

Updated VDD_IO_D in LDO_SYS electrical specifications
Updated Smart power switch
Updated Receiver Feature Summary
Added Package marking section
Added Power Sequence table

2 November

Editorial updates in the front matter
Updated minimum voltage of DC/DC voltage range from 1.8 V to 1.71 V
Added the names of Reference Manual and Chip errata in Related Resources Table
Updated the K4W1 block diagram in front matter
Removed IICIO, IICcont, VOPDU, and VRFSYS from Voltage and current operating requirements
Removed VHVD_HYS_SYS and VLVD_HYS_SYS from VDD_SYS supply HVD and LVD Operating Ratings table in HVD, LVD, and POR operating requirements
Removed IOHT, RPU(I3C), RHPU, RHPD, and IOLT from Voltage and current operating behaviors
Updated Power Switch to Smart Power Switch
Updated the values of Power mode transition operating behaviors
Removed EMC radiated emissions operating behaviors section and Designing with radiated emissions in mind
Updated the General switching specificationssection
Updated 16-bit ADC electrical characteristicssection
Updated LPI values from LPSPI master mode timing table and LP10 value from LPSPI slave mode timing
Updated Timing definition for devices on the I3C bus diagram
Updated Package marking and Package marking information
Added pinout table and pinout diagram and removed excel sheet format 3 May 2021 • Changed VREF_OUT to VREFO to make it aligned in the whole book.
Updated the Timers section in front matter content
Updated DCDC converter specifications
Updated the tstartup and jitper in Free-running oscillator FRO-192M specifications table
Updated the tstartup in Free-running oscillator FRO-6M specifications
Updated Free-running oscillator FRO-32K specifications
Updated the Low power mode peripheral power consumption adders
Updated Voltage and current maximum ratings Table continues on the next page... NXP Semiconductors

KW45 Product Family, Rev. 9, 12/2022 Data Sheet: Technical Data General Business Information 86 / 94

Removed VRFSYS and under-drive (0.9) Operation, updated note to the IICIO in the Voltage and current operating requirements.
Removed Target VDD_Core = 0.9 V from VDD_CORE supply HVD and LVD Operating Ratings table in HVD, LVD, and POR operating requirements
Updated 32 MHz to 64 MHz in Power mode transition operating behaviors.
Updated the Power Consumption Operating Behaviors
Updated the Typical power-down mode RAM current adders
Updated Thermal attributes.
Added VPA_2P4GHz, VREFO and Digital/non-GPIO rows in Recommended connection for unused analog and digital pins.
Updated CPU_CLK and slow clock frequency in Power mode transition operating behaviors
Updated the values in General switching specifications
Updated Transmit and PLL Feature Summary
Updated Pinout Table
Updated tsco in MIPI-I3C push-pull specifications for SDR and HDR-DDR modes table and added figures in Improved Inter-Integrated Circuit Interface (MIPI-I3C) specifications
Updated the descriptions to the VOUT_SYS, ILOAD and IDD in the LDO_SYS electrical specifications
Updated the comments to the DCDC_LX in the Recommended connection for unused analog and digital pins

4 September

Editorial changes
Updated the front matter content
Updated the part numbers to add 'T' for Tray or 'R' for Reel in the end
Updated ESD and Latch-Up Ratings
Removed IDD from Voltage and current maximum ratings
Updated the Voltage and current operating requirements table
Updated the typical value of VLVDV_HYS_IO_ABC, VHVD_HYS_SYS and VLVD_HYS_SYS in HVD, LVD, and POR operating requirements
Updated the typical values of VDD_CORE supply HVD and LVD Operating Ratings table
Updated the EdgeLock Secure Enclave in KW45 block diagram
Updated the description and values of VDD_IO_D in LDO_SYS electrical specifications
Updated Voltage and current operating behaviors table
Updated the description of I2C/I3C I/O pins in General switching specifications
Updated the minimum value of VBAT in Free-running oscillator FRO-16K specifications and added footnote Table continues on the next page... NXP Semiconductors

KW45 Product Family, Rev. 9, 12/2022 Data Sheet: Technical Data General Business Information 87 / 94

Removed the bullet of 0 to 40 °C in Δffro16K in Free-running oscillator FRO-16K specifications
Added four low voltage command times in Flash timing specifications table
Added tPORFAST and updated tPOR in Power mode transition operating behaviors table
Updated the values in Power mode transition operating behaviors table
Added Typical hysteresis vs. Vin level (VDD = 3.3 V, HPMD = 1) chart, Typical hysteresis vs. Vin level (VDD = 3.3 V, HPMD = 0, NPMD = 1), and Typical hysteresis vs. Vin level (VDD = 3.3 V, HPMD = 0, NPMD = 0) in CMP and 8-bit DAC electrical specifications
Updated Power Consumption Operating Behaviors table
Updated maximum value of CL in VREF operating requirements and VREF operating behaviors in Voltage reference electrical specifications
Updated VDD_ANA symbol to VDD_IO_ABC and the maximum value of VREFH to VDD_IO_ABLC in CMP and 8-bit DAC electrical specifications
Removed the references of NVM and added footnote for CAN in pinout table Pinout Table
Updated Receiver Feature Summary and Transmit and PLL Feature Summary
Removed the references of SUOX and SOX from 32 kHz oscillator electrical specifications

4.1 December

Added parts
Updated the Front matter content

5 December

Editorial updates
Removed the Note below package drawings
Updated the Reel to Tape and Reel in Ordering Information table
Added SIM_SDID value in Device Revision table
Removed IICcont parameter, updated the values of IICIO, and added another footnote to IICIO in Table 10
Updated the first footnote in Table 15
Updated the maximum value of ILOAD at Normal drive mode in Table 16
Updated ILOAD parameter in Table 17
Updated Table 21
Updated the values of Jitosc and vec_extal32 in Table 32
Added typical values to all parameters in Table 40
Added new parameter VPA_2P4GHz in Table 41
Added footnotes in Table 42
Updated Table 43 Table continues on the next page... NXP Semiconductors

KW45 Product Family, Rev. 9, 12/2022 Data Sheet: Technical Data General Business Information 88 / 94

Updated the values of fADCK and RADIN in Table 48
Updated Table 49
Updated Table 50
Updated typical and maximum value of Vacc in Table 52
Added maximum value of fSCL and minimum value of tSU_PP in Table 60
Added Abbreviations and Acronyms
Updated Table 44
Removed RF_UART signal from Pinout Table

6 September

Updated the Front Matter Content content
Updated Bluetooth Low Energy 5.2 to Bluetooth Low Energy 5.3 all over the datasheet
Updated the minimum value and maximum value of VOUT_CORE for low drive strength in LDO_CORE electrical specifications
Updated the values of tPWDN and tDPWDN in Power mode transition operating behaviors
Updated the values to TBD in Power Consumption Operating Behaviors and added IDD tables for phantoms: 512M + RF, 1M + non-RF and 512 + non_RF.
Updated the ambient temperature range from 120 °C to 105 °C
Removed the values for ambient temperature 120 °C all over the document
Updated the range of Target VDD_CORE in Table 12
Updated the values of VLVD_COREat Target VDD_CORE = 1.05 in Table 12
Updated the values of VOUT_DCDC in Table 15
Updated Table 24 to show only 25 °C
Updated Typical power-down mode RAM current adders
Added footnotes to Receiver Feature Summary and Transmit and PLL Feature Summary
Update the minimum value of VDD_CORE, VDD_LDO_CORE and maximum value of VDD_RF in Voltage and current operating requirements
Updated Table 31
Added footnotes to Table 42

7 September

Updated the Ordering information of radio parts and non-radio parts in Front Matter Content content to reflect "B" instead of "A" as Silicon Revision
Updated Table 63

8 December

Updated Front matter content
Updated Power Consumption Operating Behaviors and removed IDD tables for phantom parts
Updated minimum and maximum value of Electrostatic discharge voltage, charged- device model (antenna pin) in ESD and Latch-Up Ratings to -250 V and +250 V Table continues on the next page... NXP Semiconductors

KW45 Product Family, Rev. 9, 12/2022 Data Sheet: Technical Data General Business Information 89 / 94

Updated Power mode transition operating behaviors to remove tPOR and tPORFAST
Updated description and IDD values in Low power mode peripheral power consumption adders
Removed 26.0 MHz information from Reference oscillator specification
Merged crystal and frequency tolerance entry and crystal frequency stability and aging information entry to single entry in Reference oscillator specification
Removed the maximum value of SELBLE1M, 4+ MHz in Table 42
Removed 26 MHz from Reference frequency bullet in Transmit and PLL Feature Summary
Added SoC Power Consumption section
Updated typical value of fref in 2.4 GHz radio transceiver electrical specification to show

32 MHz only

Updated the typical value of TRIMstep in Free-running oscillator FRO-32K specifications to 0.03
Added footnote to PTC6 pin in 40 HVQFN package in Pinout Table
Added footnote to PTC5 in 40HVQFN pinout diagram
Removed VswitchWakeup and t switchWakeup from Smart power switch
Updated Part number format and Package marking

9 December

Updated the frequency from 48 MHz to 64 MHz in "Dedicated CM3 core running at up to 48MHz" in front matter
Updated the complete ESD and Latch-Up Ratings table NXP Semiconductors

KW45 Product Family, Rev. 9, 12/2022 Data Sheet: Technical Data General Business Information 90 / 94

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Please be aware that important notices concerning this document and the product(s) described herein, have been included in section 'Legal information'. © NXP B.V. 2022. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 12/2022 Document identifier: KW45

Product Information

KW45Z specifications and overview.

Summary

Highly Secure, Bluetooth Low Energy 5.3 Wireless MCU with CAN FD Rev. 9 - 12/2022

Description

Highly Secure, Bluetooth Low Energy 5.3 Wireless MCU with CAN FD Rev. 9 - 12/2022

Source title KW45Z Datasheet(PDF) - NXP Semiconductors

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