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© Freescale Semiconductor, Inc., 2013. All rights reserved. Freescale Semiconductor User’s Guide Document Number: KTPF0100UG Rev. 2.0, 2/2013 KITPF0100EPEVBE Evaluation Board Featuring the MMPF0100 14-Channel Configurable PMIC Figure 1. KITPF0100EPEVBE Evaluation Board
Contents
KTPF0100UG, Rev. 2.0
2 Freescale Semiconductor
Kit Contents / Packing List
1 Kit Contents / Packing List
- Customer evaluation board KITPF0100EPEVBE
- KITPF0100EPEVBE Quick Start Guide
- Warranty card and Technical support brochure
KTPF0100UG, Rev. 2.0 Freescale Semiconductor 3 Important Notice
2 Important Notice
Freescale provides the enclosed product(s) under the following conditions: This evaluation kit is intended for use of ENGINEERING DEVELOPMENT OR EVALUATION PURPOSES ONLY. It is provided as a sample IC pre-soldered to a printed circuit board to make it easier to access inputs, outputs, and supply terminals. This EVB may be used with any development system or other source of I/O signals by simply connecting it to the host MCU or computer board via off-the-shelf cables. This EVB is not a Reference Design and is not intended to represent a final design recommendation for any particular application. Final device in an application will be heavily dependent on proper printed circuit board layout and heat sinking design as well as attention to supply filtering, transient suppression, and I/O signal quality. The goods provided may not be complete in terms of required design, marketing, and or manufacturing related protective considerations, including product safety measures typically found in the end product incorporating the goods. Due to the open construction of the product, it is the user's responsibility to take any and all appropriate precautions with regard to electrostatic discharge. In order to minimize risks associated with the customers applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. For any safety concerns, contact Freescale sales and technical support services. Should this evaluation kit not meet the specifications indicated in the kit, it may be returned within 30 days from the date of delivery and will be replaced by a new kit. Freescale reserves the right to make changes without further notice to any products herein. Freescale makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typical”, must be validated for each customer application by customer’s technical experts. Freescale does not convey any license under its patent rights nor the rights of others. Freescale products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale was negligent regarding the design or manufacture of the part.Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2013
KTPF0100UG, Rev. 2.0
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3 Introduction
The KITPF0100EPEVBE evaluation board allows full evaluation capability of the PF0100 PMIC for the i.MX6 family of application processors. It provides access to all output voltage rails as well as control and signal pins through terminal block connectors for an easier out-of-the-box evaluation experience. A single terminal block connector for the input power supply allows the user to supply the board with an external DC power supply to fully evaluate the performance of the device. The KITPF0100EPEVBE comes with a non-programmed version of the PF0100 PMIC, so it is prepared to power up from the default sequence. However, an integrated control/fuse programming interface is provided to allow the customer to program the OTP/TBB (One Time Programmable/Try-Before-Buy) memory and also to select it as the default source for the power-up configuration. Likewise, the programming interface allows full control of the PF0100 through the I 2C communication lines. This document is intended to provide an overview of the KITPF0100EPEVBE evaluation board as well as detailed instruction for programming the PF0100 through its dedicated Graphic User Interface (GUI). Note: This document provides updated information on the installation and use of the current PF0100 EVK Control version of the GUI you are using, please refer to section “Graphical User Interface Description”.
4 KITPF0100EPEVBE Features
- Input voltage operation range from 3.1 V to 4.5 V
- Output voltage supplies accessible through detachable terminal blocks
- Four to six independent buck converters
- One 5.0 V boost regulator
- Six general purpose LDO regulators
- One DDR memory termination voltage reference
- One VSRTC supply
- Coin cell support for “Try-Before-Buy” (TBB) mode
- On/off push button support
- Hardware configuration flexibility throu gh various jumper headers and resistors
- Integrated USB to I 2C programming interface for full control/configuration
- Onboard OTP programming supply and control
- Onboard PMIC control through the I 2C register map
- Fully featured programmer through J36 for external device control/programming
- On board connectors for interfacing with future evaluation/debug tools
- Compact form factor (4 x 4 in 2)
KTPF0100UG, Rev. 2.0 Freescale Semiconductor 5 Hardware/Software Requirements
5 Hardware/Software Requirements
5.1 Hardware Requirements
- Power supply:
- Output voltage range from 3.1 V to 4.5 V
- Current capability from 3 to 5 A (current requirement is dependent on output loading)
- Supply to board connection cables (capable of withstanding up to 5 A current)
- USB (male) to mini USB (male) communication cable.
- USB-enabled computer.
5.2 Software Requirements
- Windows XP or Windows 7 operating system
- Microsoft .NET Framework 4.0
- NI-VISA 5.1.2 communication package + developm ent support with .NET Framework 4.0 languages support
- KITPF0100GUI.zip: Graph ical User Interface (GUI) for KITPF0100EPEVBE
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6 Software and Drivers Installation
- Install Windows Installer 3.1 (Windows XP Only), download and run
enabling the NI-VISA 5.1.2 drivers. Figure 2. NI-VISA 5.1.2 Features Install window
- Go to Start > Programs > National Instruments > VISA > Driver Wizard
- Select USB under Hardware Bus Selection and press “Next” button
Figure 3. NI-VISA Hardware Bus Selection Window
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- Enter "15A2" in the vendor ID and "00F5" in th e product ID fields and press the “Next” button.
Figure 4. NI-VISA USB Device Information Window
- Enter "PF0100-Evaluation" in the instrument prefix fi eld, browse to a folder where you want to save the
Figure 5. NI-VISA Output File Generation Window
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- Select the option of automatically installing the generated .INF driver and press the “Finish” button.
Figure 6. NI-VISA Installation Options Window
- Supply 3.6V to J25 of KITPFGMEVME and then conn ect the USB cable from the USB-MiniB port (J34) to
the computer. See Figure 10 for the connection diagram.
- To check if the USB device driver was installed correctly, go to Start > Setting > Control Panels> System >
Device Driver. You should see "PF0100-Evaluation Board" under "NI-VISA USB Devices". Figure 7. Microsoft Windows Device Manager
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6.2 Installing the KITPF0100GUI
- Create a directory on your PC as follows:
- Extract the KITPF0100GUI.zip file into that directory.
- Launch the "setup.exe" program.
- When the following popup dialog appears, press the “Install” button.
Figure 8. KITPF0100 GUI installation Window If everything installs correctly, the next scre en you should see is the application GUI.
7 Hardware Configuration
By default, the KITPF0100EPEVBE evaluation board is set to power up from the default power-up sequence. functionality, refer to Table 1. Figure 9. Default Jumper Configuration Diagram
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Figure 10. Evaluation Board Setup pull-up resistors by removing R34 and R33 and shorting pins 1, 2 and 3 of J30.
8 Evaluation Board Schematic
Figure 11. KITPF0100EPEVBE LDO/Cont rol Schematic Part 1
200 OHM
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Figure 12. KITPF0100EPEVBE LDO/Control Schematic Part 2
Figure 13. KITPF0100EPEVBE Switching Regulators Schematic
12 MHz
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Figure 14. KITPF0100EPEVBE Control/program ming Interface Schematic
9 Hardware Description
Description for a d etailed description of the KITPF0100GUI software. buck regulator in the start-up sequence. Refer to the MMPF0100 Datasheet for details on buck regulator setup.
9.1 Jumper Description
Table 1. KITPF0100EPEVBE jumper description J1 - J7 Closed Buck regulators input power path isolation. Short these jumpers to allow SWxIN to be powered from the SWVIN supply. J9 Closed SWBST regulator input power path isolation. Short this jumper to allow SWBSTIN to be powered from the SWVIN supply.
- 1-2: Connect VDDOTP to the OTP Boost output (VD DOTPIN) for OTP programming.
- 3-4: Connect VDDOTP to GND to power up from OTP/TBB sequence.
- 5-6: Connect VDDOTP to VCOREDIG to power up from Default Power up sequence. J20 1-2 Coin cell selector.
- 1-2: Enables BAT1 as the main coin cell supply.
- 2-3: Enables BAT2 as the main coin cell supply. J40 Closed Shorts PVIN and SWVIN. Allows supply isolation to provide more accurate efficiency readings on the switching supplies. J41 Open Shorts SWVIN to VIN. Allows one to isolate or connect the PF0100 logic input supply to SWVIN net. (debugging option) J27 Closed Shorts PVIN to VIN. Allows one to isolate or connect the PF0100 logic input supply to PVIN net. (debugging option) J22 2-3 PF0100 input logic supply selector.
- 1-2: Connects PF0100 VIN terminal to the 3.3V external LDO regulator for debugging purposes.
- 2-3: Connects PF0100 VIN terminal to the main input supply. Refer to Figure 11. J26 Open Short to hold PWRON pin low. J24 Open Short to pull STANDBY to VSNVS voltage supply. J30 2-3 I2C pull-up supply selector
- 1-2: Pull the SCL/SDA signals to the external 3.3V LDO regulator output.
- 2-3: Pull the SCL/SDA signals to the selected VDDIO supply. If 3.3V LDO output is desired as the VDDIO and I2C supply, remove R33 and R34 and short pins 1,2 and 3 to make sure VDDIO uses the same reference as the I2C supply. J39 1-2 Control Interface input supply selector
- 1-2: Enables PVIN node as the input suppl y source for the control interface.
- 2-3: Enables USB power as the input suppl y source for the control interface.
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9.2 Connectors and Terminal Blocks Description
Table 2. Terminal Blocks descriptions
Figure 15. Input/Output Terminal Blocks
Table 3. Connector Description J42 Debug Port 1 Debugging connector for future development tools.
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9.3 Debug and Configuration Components
supplies to test various loading and supplying scenarios.
9.3.1 SW1A/B/C Config uration Components
Figure 16. SW1A/B/C Output Configuration The SW1A/B/C regulator can be configured in va rious operating modes as described in Table 4. Table 4. SW1ABC Configuration Chart
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9.3.2 SW3A/B Configuration Components
Figure 17. SW3A/B Output Configuration The SW3A/B regulator can be configured in var ious operating modes as described in Table 5. Table 5. SW3ABC Configuration Chart
9.3.3 LDO Input Supply Source Selection
Figure 18. LDO Schematic Configuration
Figure 19. Logic and Core Supplies Schematic Table 6. LDO Input Supply Configuration Chart
- Make sure to populate only one option per input pin to avoid shorts between
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9.3.4 Test point
various test points of interest during evaluation. Figure 20. Key Test Point Locations and Default Voltages
9.4 Miscellaneous Components
9.4.1 Power on Push Button
Figure 21. Power on Circuit
9.4.2 PMIC LED Indicators
given signal debug is required. Figure 22. PMIC Status Indicator
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Table 7 describes the meaning of the LED states. Table 7. LED State Description
9.4.3 Control/Programming Interface
This onboard USB-to-I2C interface comprises three basic blocks.
- Controlling MCU (MC9S0 8J M60CGTE) for USB-I2C translation.
- 3.3V LDO supply for external device controlling.
- 8.25V boost converter for OTP programming.
can serve as a programmer for external devices though the connector J36. Figure 23. Control/Programming Int erface Schematic
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10 Graphical User Interface Description
with one functional aspect of the PF0100 device.
10.1 Getting Started
- Supply 3.6V to J25 of the EVK boar d, then connect the USB cable from the USB-MiniB port (J34) to the
computer. J30 should be in position (2-3); otherwise, you will receive an error message.
- Press the “Open Session” button to se ar ch for the PF Programmer device.
- The “Select Resource” dialog box should pop up, and you should see the KITPF0100E PEVBE device
listed. The USB Vendor ID is 0x15A2, and the Part ID is 0x00F5 for the KITPF0100EPEVBE. Select the device and press the “OK” button. Figure 24. OPEN USB Connection
- The “Select Resource” dialog should close, and the Log List w ill display a message that you are connected
connected to the right device.
- The Log List can be saved to a text file at any time by pr essing the “Save Log” button, and a "File Save” dialog box will pop up.
- The Log List can also be cleared at any time by pressing the “Clear Log” button.
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10.2 Verify I 2C Communication to PF0100
what I2C transactions the GUI has processed. Figure 28. Verify I2C Communication.
10.3 GUI Features
one to perform either prototyping or One-Time Programming (OTP) of the fuse registers. The Power tab provides user access to control both the switching as well as the linear regulators on PF0100. phase configuration for SW1 and SW3. Figure 29. Switching Regulators Tab
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and the start-up sequence of the regulators as well as to choose between the standby and low power mode. Figure 30. LDO Regulators Tab can choose to read the interrupts by pressing on the “Read Interrupt x” button. also cause the INTB pin to go high. INTB pin will not go low. A masked interrupt can still be read from the Interrupt Status register. interrupt sources. They are read only, and neither latched nor clearable.
The user may choose to press the “Poll Interrupt x” control to read the Interrupts tab every 500ms. Figure 31. Interrupts Tab
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write and read controls shown in section “Verify I2C Communication to PF0100”. Figure 32. Register Bits Tab
short-circuit protection, set the de-bounce time of logic IO, and communicate with memory registers A-D. Figure 33. Miscellaneous Tab
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The EVK Test Points tab provides a visual aid to the top layer of KITPF0100EPEVBE. Figure 34. EVK Test Point Tab information on how to create a configuration script, see section “Using the Script Editor”.
10.4 Using the Script Editor
be explored and validated prior to connecting to a host i.MX processor. ys the script output as it steps sequentially. Figure 35. Script Editor Window
KTPF0100UG, Rev. 2.0
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Graphical User Interface Description The following list describes all the available buttons on the Script Editor tab.
- Load Script: Launches the “File Load” dialog box allowing the user to select and load a stored script file.
- Save Script: Launches the “File Save” dialog box, allowing the user to save a script file to storage.
- Clear Script: Clears the current Script Editor work area to prepare for writing a new script.
- Run Script: Begins execution of the currently loaded script. Execution runs sequentially.
- Step Delay: Entered as an integer number between 0 and 1000 milliseconds. Double-click with the left mouse button over the text box to begin editing the value, then press the Enter key.
- Insert Line Separator: Inserts a comment at the current cursor position that represents a separating line. Used to organize long scripts.
- Append Programming: Inserts all the commands required to program the OTP memory into the Script Editor at the current cursor location.
- Save Log: Launches the “File Save” dialog box, allowing users to save the Script Log to a file.
- Clear Log: Clears the Script Log.
- Commands: Displays the pop-up window shown in Figure 40, with a graphical set of commands to add to the script.
10.4.1 Loading and Running a Script
to navigate to the directory where your script file is located. Select the file you want and press the “Open” button. Figure 36. Loading a Script File label and also as an entry in the Script Log.
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color returns to white, indicating that your updated value has been accepted. Figure 37. Script Dialog Box
Figure 38. Running the Script
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10.4.2 Writing a New Script
To write your own scripts, begin by creating a comment header using the “Insert Line Separator” button. Figure 39. Inserting Line Separators
selector in a new window, as shown in Figure 40. Figure 40. Command Selector Window
- PF0100 - SWITCHING SUPPLIES> place a single script comm and with the selected buck regulator and the desired function. The available functions are: mode selection, operating voltage setpoint, standby voltage setpoint, OFF voltage setpoint, enable current limit and disable current limit. Note that for SW2, SW3A/B and SW4, the VOLTS RANGE HIGH box need to be checked if the initial power up voltage is set to the high voltage operating range. If working in the lower voltage range, leave the box unchecked.
- PF0100 - LINEAR SUPPLIES> places a single scrip t comm and with the selected LDO regulator and the desired function. The available functions are: operating voltage setpoint, enable and disable output.
- PF0100 - SWBST> Permits changing the operating vo lt age, as well as enabling and disabling the SWBST output.
- PROGRAMMER COMMANDS> Enables or disables the 3.3V su pply as well as the ~8.0V boost supply on the KITPF0100EPEVBE. Allows a progressive step-up/step-down of the ~8.0V output and controls the general purpose output to set the PWRON terminal on the PF0100 high or set the same PWRON terminal low or toggle a pulse that triggers a PWRON event.
- OTHER COMMANDS> This section provides access to co mmon instruc tions initiated by the control MCU. The possible commands include delay, add separator bar, generic I2C write/read, set GPIO1 and GPIO2 high, low or toggle.
- LOG COMMAND> provide a log report of the a ctual status of a specific configuration on the PMIC. Syntax for the log commands are shown in Table 8.
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10.4.2.1 Syntax and Command Set
- ':' - Is used as a separator
- '/' - Anything after a '/' will be ignored.
- White spaces will be truncated.
Table 8. Command List(2) VPGM:ON Enables the 8.0 V OTP programming supply. VPGM:OFF Disables the 8.0 V OTP programming supply. VPGM:UP:<n> Increases the OTP programming voltage (VPGM) in <n> DAC steps. VPGM:DOWN:<n> Decreases the OTP programming voltage (VPGM) in <n> DAC steps. V3V3:ON Enables the 3.3 V system supply. V3V3:OFF Disables the 3.3 V system supply. PWRON:LOW Asserts the PWRON signal LOW, forcing the PF0100 to shutdown. high-impedance state, generating a power on event on the PF0100. with the Script Delay set on the Editor. delay is set in ms. GPIO1:HIGH Releases the GPIO1 signal to a high-impedance state. GPIO1:LOW Asserts the GPIO1 signal LOW. GPIO2:HIGH Releases the GPIO2 signal to a high-impedance state. GPIO2:LOW Asserts the GPIO2 signal LOW.
- O F F
- P F M
- P W M
- APS SW1x:VOUT:<value> Sets the SW1x output voltage in normal operation. Operating range from 0.300 V to 1.875 V in 0.025 V steps.
- O N
- O F F SWx:MODE:<operator> Sets the mode of operation of the SWx regulator. Following are valid operators:
- O F F
- P F M
- P W M
- APS SWx:VOUT:<value> Sets the SWx output voltage to normal operation. Full operating range from 0.300 V to 3.300 V divided into two operating ranges(4):
- Low Voltage Range > 0.300 V to 1.875 V in 0.025 V steps.
- High voltage Range > 0.800 V to 3.300 V in 0.050 V steps. SWx:VSTBY:<value> Sets the SWx output voltage to the STANDBY mode. Full operating range from 0.300 V to 3.300 V divided in two operating ranges(4):
- Low Voltage Range > 0.300 V to 1.875 V in 0.025 V steps.
- High voltage Range > 0.800 V to 3.300 V in 0.050 V steps. SWx:OFF:<value> Sets the SWx output voltage to the OFF mode. Full operating range from 0.300 V to 3.300 V divided into two operating ranges(4):
- Low Voltage Range > 0.300 V to 1.875 V in 0.025 V steps.
- High voltage Range > 0.800 V to 3.300 V in 0.050 V steps. SWx:ILIM:<operator> Enables/disables the SWx current limit. Valid operators:
- O N
- O F F SWBST:VOUT:<value> Set the output voltage of the SWBST regulator. Valid output voltage:
- 5 . 0 0 0
- 5 . 0 5 0
- 5 . 1 0 0
- 5 . 1 5 0 SWBST:ON Enables SWBST regulator SWBST:OFF Disables SWBST regulator. VGENx:ON Enables the VGENx supply. VGENx:OFF Disables the VGENx supply. VGENx:VOUT:<value> Sets the output voltage for VGENx supply.
- VGEN1/2 operating range: 0.800 V to 1.550 V with 50 mV steps.
- VGEN3/4/5/6 operating range: 1.800 V to 3.3 V with 100 mV steps. VREFDDR:ON Enables the VREFDDR supply.
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VREFDDR:OFF Disables the VREFDDR supply. VSNVS:OFF Disables the VSNVS supply. LOG:SWx:<log operator> Shows the current value of the <log operator> for the SWx regulator.
- VOUT = Output voltage in normal operation.
- STBY = Output voltage in STANDBY mode.
- OFF = Output voltage in OFF mode.
- MODE = Current switching mode set.
- OTP_VOUT = Default power up voltage set through OTP.
- OTP_SEQUENCE = Default power up sequence of regulator. LOG:VGENx:<log operator> Shows the current value of the <log operator> for the VGENx regulator. Log operators:
- VOUT = Output voltage.
- ENABLE = supply is ENABLED/DISABLED.
- OTP_VOUT = Default power up voltage set through OTP.
- OTP_SEQUENCE = Default power up sequence of regulator. LOG:VSWBST:<log operator> Shows the current value of the <log operator> for the VSWBST regulator. Log operators:
- VOUT = Output voltage.
- ENABLE = Supply is ENABLED/DISABLED.
- OTP_VOUT = Default power up voltage set through OTP.
- OTP_SEQUENCE = Default power up sequence of regulator. LOG:VREFDDR:<log operator> Shows the current value of the <log operator> for the VREFDDR regulator. Log operators:
- ENABLE = supply is ENABLED/DISABLED.
- OTP_SEQUENCE = Default power up sequence of regulator. LOG:VSNVS:<log operator> Shows the current value of the <log operator> for the VSNVS regulator. Log operators:
- VOUT = Output voltage.
- OTP_VOUT = Default power up voltage set through OTP. LOG:OTP_PU_CONFIG:<log operator> Shows the current value set as default by OTP.
- SEQ_CLK_SPEED = programmed power up sequencing speed.
- DVS_CLK_SPEED = programmed DVS speed.
- PWRON_MODE = programmed PWRON pin active level.
- PGOOD_ENABLE = Power good mode is on/off.
LOG:INT:<Int operator> Shows the status of the corresponding interrupt bit.
- 110_DEGREES
- 120_DEGREES
- 125_DEGREES
- 130_DEGREES
- SW1A_OVERCURRENT
- SW1C_OVERCURRENT
- SW2_OVERCURRENT
- SW3A_OVERCURRENT
- SW3B_OVERCURRENT
- SW4_OVERCURRENT
- SWBST_OVERCURRENT
- VGEN1_OVERCURRENT
- VGEN2_OVERCURRENT
- VGEN3_OVERCURRENT
- VGEN4_OVERCURRENT
- VGEN5_OVERCURRENT
- VGEN6_OVERCURRENT 2. All characters (except for the "Float" subc ommand) have to be entered in uppercase. 3. The register and data values should be entered as he xadecimal numbers, for example: 0x20 is entered as 20. 4. The output voltage operating range is set during OTP programming and cannot be changed under normal PMIC control.
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Figure 41 shows a small sample script which enables the VGEN1 supply and reads the SW1AB mode register. Figure 41. Sample Script
Figure 42. Verifying Script Results.
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Figure 43. Verifying SW1 Mode Read Command
will appear. Enter the desired script file name, including the “.txt” file extension, then press the “Save” button. Figure 44. Saving a Script
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10.5 Loading a Configuration File
Figure 45. Loading a Configuration File
Figure 46. Scripting Tab PMIC in use. Remember to add the .txt file extension.
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10.6 Programming an External PF0100 Through J36
- Verify that J22 is NOT in position 1-2
- Verify that J17 is NOT in position 1-2
- Verify that J30 is NOT in position 1-2
- Remove R43 (bottom layer)
- Remove R46 (bottom layer)
- Remove R47 (bottom layer)
Figure 47. KITPF0100EPEVBE Bottom View - Component s Location can be easily done by pressing the “OTP Blank?” button.
comparison between the data written and the data actually programmed into the part. Figure 48. Verify After Programming and OTP Blank? sequence will be displayed in the Log List. programming errors will be reported in the Log List.
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Figure 49. Scripting Log Session Example the I2C pull-up resistors by removing R34 and R33 and shorting pins 1, 2 and 3 of J30.
11 KITPF0100EPEVBE Board Layout
11.1 Assembly Layer Top
Figure 50. Assembly Top Layer
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11.2 Assembly Layer Bottom
Figure 51. Assembly Layer Bottom
11.3 Top Layer Routing
Figure 52. Top Layer Routing
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11.4 Inner Layer 1 Routing
Figure 53. Inner Layer 1 Routing
11.5 Inner Layer 2 Routing
Figure 54. Inner Layer 2 Routing
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11.6 Bottom Layer Routing
Figure 55. Bottom Layer Routing
KTPF0100UG, Rev. 2.0 Freescale Semiconductor 65 Bill of Materials
12 Bill of Materials
Label Value/Description Part Number Manufacturer 1 1 BAT1 BATTERY LITHIUM -- 3V 5.5MAH MS621F-FL11E SII MICRO PARTS LTD. 2 1 BAT2 HOLDER COIN CELL 6.8MM SMT BK-879 MEMORY PROTECTION DEVICES INC 3 4 BH1, BH2, BH3, BH4 MOUNTING HOLE 0.130 INCH, NOT A PART TO ORDERr NOT A PART TO ORDER NO MFG 4 7 C1, C3, C5, C8, C9, C12, C13 CAP CER 4.7μF 10V 10% X5R 0603 5 7 C2, C6, C10, C11, C14, C44, C45 CAP CER 0.1μF 10V 10% X5R 0402 6 5 C4, C7, C19, C56, C77 CAP CER 0.1μF 10V 10% X7R 0402 7 1 C15 CAP CER 0.01μF 50V 10% X7R 0402 8 14 C16, C21, C22, C25, C26, C27, C28, C29, C30, C31, C32, C33, C82, C83 CAP CER 22μF 10V 20% X5R 0805 9 1 DNP C17 CAP CER 1000PF 50V X7R 5% 0402 10 1 C18 CAP CER 10μF 10V 10% X7R 0805 11 5 C20, C34, C38, C42, C43 CAP CER 2.2μF 6.3V 20% X5R 0402 12 1 DNP C23 CAP CER 22μF 10V 20% X5R 0805 13 1 DNP C24 CAP CER 22μF 10V 10% X7R 1210 14 2 C35, C41 CAP CER 4.7μF 6.3V 20% X5R 0402 15 3 C36, C37, C39 CAP CER 10μF 16V 10% X7R 0805
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16 9 C40, C48, C49, C50, C51, C52, C54, C84, C87 CAP CER 1.0μF 10V 10% X5R 0402 17 2 C46, C53 CAP CER 0.22μF 16V 10% X7R 0402 18 1 C47 CAP CER 0.47μF 10V 10% X7R 0402 19 1 DNP C55 CAP CER 1.0μF 10V 10% X5R 0402 20 5 C57, C58, C62, C63, C65 CAP CER 0.1μF 16V 10% X5R 0402 21 1 C59 CAP TANT 10μF 16V 10% -- 3216-18 22 3 C60, C61, C72 CAP CER 22PF 25V 5% C0G 0402 23 1 C64 CAP CER 0.47μF 16V 10% X7R 0603 24 1 C66 CAP TANT 4.7μF 10V 10% -- 3216-18 25 1 C71 CAP TANT ESR 0.600 OHMS 15μF 25V 10% -- 3528-21 26 1 C73 CAP TANT 4.7μF 25V 10% -- 3528-21 27 1 C74 CAP CER 0.1μF 25V 10% X5R 0402 28 1 C75 CAP CER 1.0μF 25V 10% X5R 0603 29 1 C76 CAP CER 0.1μF 6.3V 10% X7R 0402 30 2 C78, C86 CAP CER 470PF 50V 5% COG 0603 31 1 DNP C79 CAP CER 2.2μF 16V 10% X5R 0603 32 1 C80 CAP CER 1.0μF 16V 10% X5R 0603 33 1 C81 CAP TANT ESR=1.800 OHMS 2.2μF 10V 10% 3216-18 34 1 DNP C85 CAP CER 2.2μF 6.3V 20% X5R 0402 Item Qty Assy Opt Schematic Label Value/Description Part Number Manufacturer
KTPF0100UG, Rev. 2.0 Freescale Semiconductor 67 Bill of Materials 35 1 D1 DIODE SCH PWR RECT 1A 20V SMT MBR120LSFT1G ON SEMICONDUCTOR 36 3 D2, D3, D11 LED RED SGL 30MA 0603 SML-LXFM0603SIC-TR LUMEX 37 1 D4 LED DUAL GRN/RED 30MA SMT LTST-C195KGJRKT LITE ON 38 4 D5, D6, D7, D8 DIODE TVS ESD PROT ULT LOW CAP 5-5.4V SOD-923 ESD9L5.0ST5G ON SEMICONDUCTOR 39 1 D9 DIODE SCH PWR RECT 1A 30V SOD-123 MBR130LSFT1G ON SEMICONDUCTOR 40 1 D10 LED GRN SGL 30MA SMT 0603 SML-LXFM0603SUGCTR LUMEX 41 1 F1 FUSE PLYSW 0.5A 13.2V SMT MICROSMD050F-2 RAYCHEM 42 56 DNP - TEST POINT RED 40 MIL DRILL 180 MIL TH 109L 43 13 J1, J2, J3, J4, J5, J6, J7, J9, J24, J26, J27, J40, J41 HDR 1X2 TH 100MIL SP 339H AU 118L 44 9 J8, J10, J11, J12, J13, J14, J15, J31, J33 SUBASSEMBLY CON 1X2 TB TH 3.81MM SP 201H -- 138L + TERM BLOCK PLUG 3.81MM 2POS 45 7 J16, J18, J19, J21, J25, J29, J32 SUBASSEMBLY CON 1X3 TB TH 3.81MM SP 201H -- 138L + TERM BLOCK PLUG 3.81MM 3POS 46 2 J17, J35 HDR 2X3 TH 100MIL CTR 335H AU 95L 47 4 J20, J22, J30, J39 HDR 1X3 TH 100MIL SP 340H AU 118L 48 1 J34 CON 5 USB MINI-B RA SHLD SKT SMT 31MIL SP AU
675031340 MOLEX
49 1 J36 HDR 2X4 TH 100MIL CTR 425H AU 310L 50 3 DNP J42, J43, J44 HDR 2X10 SMT 100MIL SP 383H AU 51 1 L1 IND PWR 2.2UH@100KHZ 2.0A 20% SMT LPS3015-222ML_ COILCRAFT 52 1 L2 IND PWR 1UH@100kHz 6A 20% SMT XAL4020-102MEC COILCRAFT Item Qty Assy Opt Schematic Label Value/Description Part Number Manufacturer
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53 4 L3, L4, L5, L8 IND PWR 1UH@100KHZ 2.4A 30% SMT LPS4012-102NLC COILCRAFT 54 1 L6 IND PWR 1UH@1MHZ 2A 30% SMT VLS252010T-1R0N TDK 55 1 L7 IND PWR 1UH@100KHZ 2.65A 20% SMT LPS5015-102MLC COILCRAFT 56 1 L9 IND FER 100 OHM@100MHZ 8A 25% SMD/1812 HI1812V101R-10 LAIRD TECHNOLOGIES 57 1 L10 IND PWR CHK 22UH@1KHZ 1A 20% SMD
744773122 WURTH
GMBH & CO. KG 58 1 L11 IND FER 100 OHM@100MHZ 8A 25% SMD/1812 HI1812V101R-10 LAIRD TECHNOLOGIES 59 1 Q1 TRAN MOSFET DUAL N & P CHANNEL 2.5V S-SOT6 FDC6327C FAIRCHILD 60 2 Q2, Q3 TRAN PMOS SW 120MA 25V SOT23 FDV302P FAIRCHILD 61 3 Q5, Q6, Q10 TRAN PMOS SW 2A 30V SSOT3 FDN360P FAIRCHILD 62 2 Q8, Q9 TRAN NMOS 50V 220MA SOT-23 BSS138 FAIRCHILD 63 6 R1, R3, R4, R6, R8, R16 RES -- 0.001 OHM 1/4W 5% 0805 LMI-R001-5.0 ISABELLENHÜTTE HEUSLER GMBH & CO. KG 64 1 DNP R2 RES MF 1.0 OHM 1/16W 1% 0402 65 5 DNP R7, R9, R10, R17, R70 RES -- 0.001 OHM 1/4W 5% 0805 LMI-R001-5.0 ISABELLENHÜTTE HEUSLER GMBH & CO. KG 66 1 R11 RES MF 0.001 OHM 1W 1% 1206 CSNL1206FT1L00 STACKPOLE ELECTRONICS 67 5 DNP R20, R23, R24, R27, R33 RES MF ZERO OHM 1/10W 1% 0603 68 6 R21, R22, R25, R26, R34, R85 RES MF ZERO OHM 1/10W 1% 0603 69 2 R28, R41 RES MF 1.0M 1/16W 1% 0402 70 2 R29, R79 RES MF 100K 1/16W 5% 0402 Item Qty Assy Opt Schematic Label Value/Description Part Number Manufacturer
KTPF0100UG, Rev. 2.0 Freescale Semiconductor 69 Bill of Materials 71 3 R30, R31, R32 RES MF 10.0K 1/16W 1% 0402 72 6 R35, R43, R46, R47, R73, R74 RES MF ZERO OHM 1/10W -- 0402 73 4 R36, R37, R50, R51 RES MF 4.70K 1/16W 1% 0402 74 4 R38, R39, R40, R69 RES MF 200 OHM 1/10W 1% 0402 75 2 R42, R45 RES MF 33.0 OHM 1/16W 1% 0402 76 2 DNP R48, R49 RES MF 1.5K 1/16W 5% 0402 77 1 R55 RES MF 100 OHM 1/10W 1% 0603 78 1 R56 RES MF 604K 1/16W 1% 0402 79 1 R59 RES MF 374K 1/16W 1% 0402 80 2 R60, R76 RES MF 470K 1/16W 1% 0402 81 1 R61 RES MF 120K 1/16W 1% 0402 82 3 R63, R64, R65 RES MF 10K 1/16W 5% 0402 83 2 R66, R75 RES MF 47K 1/16W 1% 0402 84 2 R67, R68 RES MF 470 OHM 1/16W 1% 0402 85 1 R71 RES MF 20K 1/10W 5% 0603 86 1 R72 RES MF 12.0K 1/10W 1% 0603 87 2 R77, R78 RES MF 100K 1/16W 1% 0402 88 1 R80 RES MF 27K 1/16W 5% 0402 89 1 R81 RES MF 470K 1/16W 5% 0402 90 3 DNP R82, R83, R84 RES MF ZERO OHM 1/10W -- 0402 91 1 DNP SW1 SW SPST PB 12V 50MA SMT Item Qty Assy Opt Schematic Label Value/Description Part Number Manufacturer
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92 1 U1 IC POWER MANAGEMENT CONSUMER/INDUSTRIAL QFN56 MMPF0100NPEP FREESCALE SEMICONDUCTOR 93 1 U2 IC MCU 8BIT 48MHZ 60KB FLASH 2.7-5.5V QFN48 MC9S08JM60CGTE FREESCALE SEMICONDUCTOR 94 1 U4 IC DAC CTRL BOOST INV MAX686EEE+ MAXIM 95 2 U5, U7 IC LIN VREG LDO 1.5-15V 150MA 2.5-16V SOT23-5 MIC5205YM5 MICREL 96 1 Y1 XTAL 12MHZ SER 9PF SMT ECS-120-9-42X-CKM-TR ECS INC. INTERNATIONAL Freescale does not assume liability, endorse, or warrant components from external manufacturers that are referenced in circuit drawings or tables. While Freescale offers component recommendations in this configuration, it is the customer’s responsibility to validate their application Item Qty Assy Opt Schematic Label Value/Description Part Number Manufacturer
MMPF0100 Data Sheet http://cache.freescale.com/files/analog/doc/data_sheet/MMPF0100.pdf MMPF0100ER Errata http://cache.freescale.com/files/analog/doc/errata/MMPF0100ER.pdf PFSERIESFS Fact Sheet http://cache.freescale.com/files/analog/doc/fact_sheet/PFSeriesFS.pdf AN4622 Layout Application Note http://cache.freescale.com/files/analog/doc/app_note/AN4622.pdf Product Summary Page www.freescale.com/MMPF0100 Tool Summary Page www.freescale.com/KITPF0100EPEVBE Analog Home Page www.freescale.com/analog Power Management Home Page www.freescale.com/PMIC KTPF0100UG, Rev. 2.0 Freescale Semiconductor 71 References
13 References
13.1 Support
Visit Freescale.com/support for a list of phone numbers within your region.
13.2 Warranty
Visit Freescale.com/warranty for a list of phone numbers within your region.
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Revision History
Revision Date Description of Changes 1.0 11/2012 • Initial Release 2.0 2/2013 • Updated document for the latest GUI Revision 3.0.0.20
- Added Figure 14. to section 8 Evaluation Board Schematic
- Added TBB operation Mode.
- Updated section 10.4 Using the Script Editor
- Updated section 10.5 Loading a Configuration File
KTPF0100UG, Rev. 2.0 Freescale Semiconductor 73
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