KSZ8081MNX

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Document overview

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Technical content

Features

• Single-chip 10Base-T/100Base-TX IEEE 802.3 compliant Ethernet transceiver
• MII interface support (KSZ8081MNX)
• RMII v1.2 Interface support with a 50MHz reference clock output to MAC, and an option to input a 50MHz reference clock (KSZ8081RNB)
• Back-to-back mode support for a 100Mbps copper repeater
• MDC/MDIO management interface for PHY register configuration
• Programmable interrupt output
• LED outputs for link, activity, and speed status indication
• On-chip termination resistors for the differential pairs
• Baseline wander correction
• HP Auto MDI/MDI-X to reliably detect and correct straight-through and crossover cable connections with disable and enable option
• Auto-negotiation to automatically select the highest link- up speed (10/100Mbps) and duplex (half/full)
• Power-down and power-saving modes
• LinkMD TDR-based cable diagnostics to identify faulty copper cabling
• Parametric NAND Tree support for fault detection between chip I/Os and the board
• HBM ESD rating (6kV) Functional Diagram

Micrel, Inc. KSZ8081MNX/KSZ8081RNB August 19, 2015 2 Revision 1.4 Features (Continued)

• Loopback modes for diagnostics
• Single 3.3V power supply with VDD I/O options for 1.8V, 2.5V, or 3.3V
• Built-in 1.2V regulator for core
• Available in 32-pin (5mm × 5mm) QFN package

Applications

• Game console
• IP phone
• IP set-top box
• IP TV
• LOM
• Printer

Ordering Information

KSZ8081MNXCA 0°C to +70°C 32-Pin QFN Pb-Free MII, Commercial Temperature. KSZ8081MNXIA(1) −40°C to +85°C 32-Pin QFN Pb-Free MII, Industrial Temperature. KSZ8081RNBCA 0°C to +70°C 32-Pin QFN Pb-Free RMII with 25MHz crystal/clock input and 50MHz RMII REF_CLK output (power-up default), Commercial Temperature. KSZ8081RNBIA(1) −40°C to +85°C 32-Pin QFN Pb-Free RMII with 25MHz crystal/clock input and 50MHz RMII REF_CLK output (power-up default), Industrial Temperature. KSZ8081MNX-EVAL KSZ8081MNX Evaluation Board (Mounted with KSZ8081MNX device in commercial temperature) KSZ8081RNB-EVAL KSZ8081RNB Evaluation Board (Mounted with KSZ8081RNB device in commercial temperature) Note: 1. Contact factory for lead time.

Micrel, Inc. KSZ8081MNX/KSZ8081RNB August 19, 2015 3 Revision 1.4

Revision History

Revision Date Summary of Changes 1.0 11/5/12 Initial release of datasheet. 1.1 2/6/14 Removed copper wire bonding part numbers from Ordering Information. Added note for TXC (Pin 22) and Register 16h, Bit [15] regarding a Reserved Factory Mode for KSZ8081MNX device. Corrected TXC (Pin 22) pin type for KSZ8081MNX device. Removed TXC and RXC clock connections for MII Back-to-Back mode. This is a datasheet correction. There is no change to the silicon. Added series resistance and load capacitance for the crystal selection criteria. 1.2 12/18/14 Added silver wire bonding part numbers to Ordering Information. Updated Ordering Information to include Ordering Part Number and Device Marking. 1.3 04/14/15 Updated Table 7, add a note for Table 7. Updated Table 8, updated NAND tree I/O testing descriptions. Add Max frequency for MDC in MII Management (MIIM) Interface section. Updated Table 23, add a note for Table 23. Updated Figure 22 and Figure 22 descriptions. Updated descriptions under Figure 23 for LED strap pins, add a note for Figure 23. Fixed the missing value for maximum junction and thermal resistance (θJC). 1.4 08/19/15 Updated descriptions in local loopback section for data loopback path. Updated Table 17 and Table 21. Updated Ordering Information Table. Updated pin 22 TXC and register 16h bit [15] description for MNX part. Updated description and add an equation in LinkMD section. Add HBM ESD rating in Features.

Micrel, Inc. KSZ8081MNX/KSZ8081RNB August 19, 2015 4 Revision 1.4 Table of Contents

Micrel, Inc. KSZ8081MNX/KSZ8081RNB August 19, 2015 5 Revision 1.4

Micrel, Inc. KSZ8081MNX/KSZ8081RNB August 19, 2015 8 Revision 1.4 Pin Configuration – KSZ8081MNX 32-Pin 5mm × 5mm QFN

Micrel, Inc. KSZ8081MNX/KSZ8081RNB August 19, 2015 9 Revision 1.4 Pin Description – KSZ8081MNX Pin Number Pin Name Type(2) Pin Function

1 GND GND Ground

capacitors to ground. 3 VDDA_3.3 P 3.3V analog VDD. 4 RXM I/O Physical receive or transmit signal (− differential). 5 RXP I/O Physical receive or transmit signal (+ differential). 6 TXM I/O Physical transmit or receive signal (− differential). 7 TXP I/O Physical transmit or receive signal (+ differential).

8 XO O

Crystal feedback for 25MHz crystal. This pin is a no connect if an oscillator or external clock source is used. 9 XI I Crystal / Oscillator / External Clock Input. 25MHz ±50ppm. 10 REXT I Set PHY transmit output current. Connect a 6.49kΩ resistor to ground on this pin.

11 MDIO Ipu/Opu Management Interface (MII) Data I/O This pin has a weak pull-up, is open-drain, and

requires an external 1.0kΩ pull-up resistor. 12 MDC Ipu Management Interface (MII) Clock Input. This clock pin is synchronous to the MDIO data pin. RXD3/ PHYAD0 Ipu/O MII Mode: MII Receive Data Output3. Config Mode: The pull-up/pull-down value is latched as PHYADDR[0] at the de- assertion of reset. See the Strapping Options – KSZ8081MNX section for details. RXD2/ PHYAD1 Ipd/O MII Mode: MII Receive Data Output2. Config Mode: The pull-up/pull-down value is latched as PHYADDR[1] at the de- assertion of reset. See the Strapping Options – KSZ8081MNX section for details. RXD1/ PHYAD2 Ipd/O MII Mode: MII Receive Data Output1. Config Mode: The pull-up/pull-down value is latched as PHYADDR[2] at the de- assertion of reset. See the Strapping Options – KSZ8081MNX section for details. Notes: 2. P = Power supply. GND = Ground. I = Input. O = Output. I/O = Bi-directional. Ipu = Input with internal pull-up (see Electrical Characteristics for value). Ipu/O = Input with internal pull-up (see Electrical Characteristics for value) during power-up/reset; output pin otherwise. Ipd/O = Input with internal pull-down (see Electrical Characteristics for value) during power-up/reset; output pin otherwise. Ipu/Opu = Input with internal pull-up (see Electrical Characteristics for value) and output with internal pull-up (see Electrical Characteristics for value). 3. MII RX Mode: The RXD[3:0] bits are synchronous with RXC. When RXDV is asserted, RXD[3:0] presents valid data to the MAC. RXD[3:0] is invalid data from the PHY when RXDV is de-asserted.

Micrel, Inc. KSZ8081MNX/KSZ8081RNB August 19, 2015 10 Revision 1.4 Pin Description – KSZ8081MNX (Continued) Pin Number Pin Name Type(2) Pin Function RXD0/ DUPLEX Ipu/O MII Mode: MII Receive Data Output0. Config Mode: The pull-up/pull-down value is latched as DUPLEX at the de-assertion of reset. See the Strapping Options – KSZ8081MNX section for details. 17 VDDIO P 3.3V, 2.5V, or 1.8V digital VDD RXDV/ CONFIG2 Ipd/O MII Mode: MII Receive Data Valid Output. Config Mode: The pull-up/pull-down value is latched as CONFIG2 at the de-assertion of reset. See the Strapping Options – KSZ8081MNX section for details. RXC/ B-CAST_OFF Ipd/O MII Mode: MII Receive Clock Output. Config Mode: The pull-up/pull-down value is latched as B-CAST_OFF at the de- assertion of reset. See the Strapping Options – KSZ8081MNX section for details. RXER/ ISO Ipd/O MII mode: MII Receive Error Output. Config Mode: The pull-up/pull-down value is latched as ISOLATE at the de-assertion of reset. See the Strapping Options – KSZ8081MNX section for details. INTRP/ NAND_Tree# Ipu/Opu Interrupt Output: Programmable Interrupt Output. This pin has a weak pull-up, is open-drain, and requires an external 1.0kΩ pull-up resistor. Config Mode: The pull-up/pull-down value is latched as NAND Tree# at the de- assertion of reset. See the Strapping Options – KSZ8081MNX section for details

22 TXC Ipd/O

MII Mode: MII Transmit Clock Output. At the de-assertion of reset, this pin needs to latch in a pull-down value for normal operation. If MAC side pulls this pin high, see Register 16h, Bit [15] for solution. It is better having an external pull-down resistor to avoid MAC side pulls this pin high. 23 TXEN I MII Mode: MII Transmit Enable input. 24 TXD0 I MII Mode: MII Transmit Data Input0. 25 TXD1 I MII Mode: MII Transmit Data Input1. 26 TXD2 I MII Mode: MII Transmit Data Input2. 27 TXD3 I MII Mode: MII Transmit Data Input3. COL/ CONFIG0 Ipd/O MII Mode: MII Collision Detect output. Config Mode: The pull-up/pull-down value is latched as CONFIG0 at the de-assertion of reset. See the Strapping Options – KSZ8081MNX section for details. CRS/ CONFIG1 Ipd/O MII mode: MII Carrier Sense output Config mode: The pull-up/pull-down value is latched as CONFIG1 at the de-assertion of reset. See the Strapping Options – KSZ8081MNX section for details. Note: 4. MII TX Mode: The TXD[3:0] bits are synchronous with TXC. When TXEN is asserted, TXD[3:0] presents valid data from the MAC. TXD[3:0] has no effect on the PHY when TXEN is de-asserted.

Micrel, Inc. KSZ8081MNX/KSZ8081RNB August 19, 2015 11 Revision 1.4 Pin Description – KSZ8081MNX (Continued) Pin Number Pin Name Type(2) Pin Function LED0/ NWAYEN Ipu/O LED Output: Programmable LED0 output. Config Mode: Latched as auto-negotiation enable (Register 0h, Bit [12]) at the de- assertion of reset. See the Strapping Options – KSZ8081MNX section for details. The LED0 pin is programmable using Register 1Fh bits [5:4], and is defined as follows: LED Mode = [00] Link/Activity Pin State LED Definition No link High OFF Link Low ON Activity Toggle Blinking LED Mode = [01] Link Pin State LED Definition No link High OFF Link Low ON LED Mode = [10], [11] Reserved LED1/ SPEED Ipu/O LED Output: Programmable LED1 Output. Config Mode: Latched as Speed (Register 0h, Bit [13]) at the de-assertion of reset. See the Strapping Options – KSZ8081MNX section for details. The LED1 pin is programmable using Register 1Fh bits [5:4], and is defined as follows: LED Mode = [00] Speed Pin State LED Definition 10Base-T High OFF 100Base-TX Low ON LED Mode = [01] Activity Pin State LED Definition No activity High OFF Activity Toggle Blinking LED Mode = [10], [11] Reserved 32 RST# Ipu Chip Reset (active low). PADDLE GND GND Ground

Micrel, Inc. KSZ8081MNX/KSZ8081RNB August 19, 2015 12 Revision 1.4 Strapping Options – KSZ8081MNX The strap- in pins are latched at the de- assertion of reset. In some systems, the MAC MII receive input pins may drive high/low during power -up or reset, and consequently cause the PHY strap- in pins on the MII signals to be latched to unintended high/low states. In this case, external pull -ups (4.7kΩ) or pull -downs (1.0kΩ) should be added on these PHY strap-in pins to ensure that the intended values are strapped-in correctly. Pin Number Pin Name Type(5) Pin Function PHYAD2 PHYAD1 PHYAD0 Ipd/O Ipd/O Ipu/O PHYAD[2:0] is latched at de-assertion of reset and is configurable to any value from 0 to 7 with PHY Address 1 as the default value. PHY Address 0 is assigned by default as the broadcast PHY address, but it can be assigned as a unique PHY address after pulling the B-CAST_OFF strapping pin high or writing a ‘1’ to Register 16h, Bit [9]. PHY Address bits [4:3] are set to 00 by default. CONFIG2 CONFIG1 CONFIG0 Ipd/O Ipd/O Ipd/O The CONFIG[2:0] strap-in pins are latched at the de-assertion of reset: CONFIG[2:0] Mode

000 MII (default)

110 MII back-to-back

001 – 101, 111 Reserved – not used

20 ISO Ipd/O

Isolate Mode: Pull-up = Enable Pull-down (default) = Disable At the de-assertion of reset, this pin value is latched into Register 0h, Bit [10].

31 SPEED Ipu/O

Speed Mode: Pull-up (default) = 100Mbps Pull-down = 10Mbps At the de-assertion of reset, this pin value is latched into Register 0h, Bit [13] as the speed select, and also is latched into Register 4h (auto-negotiation advertisement) as the speed capability support.

16 DUPLEX Ipu/O

Duplex Mode: Pull-up (default) = Half-duplex Pull-down = Full-duplex At the de-assertion of reset, this pin value is latched into Register 0h, Bit [8]. Note: 5. Ipu/O = Input with internal pull-up (see Electrical Characteristics for value) during power-up/reset; output pin otherwise. Ipd/O = Input with internal pull-down (see Electrical Characteristics for value) during power-up/reset; output pin otherwise. Ipu/Opu = Input with internal pull-up (see Electrical Characteristics for value) and output with internal pull-up (see Electrical Characteristics for value).

Micrel, Inc. KSZ8081MNX/KSZ8081RNB August 19, 2015 13 Revision 1.4 Strapping Options – KSZ8081MNX (Continued) Pin Number Pin Name Type(5) Pin Function

30 NWAYEN Ipu/O

Nway Auto-Negotiation Enable: Pull-up (default) = Enable auto-negotiation Pull-down = Disable auto-negotiation At the de-assertion of reset, this pin value is latched into Register 0h, Bit [12].

19 B-CAST_OFF Ipd/O

Broadcast Off – for PHY Address 0: Pull-up = PHY Address 0 is set as an unique PHY address Pull-down (default) = PHY Address 0 is set as a broadcast PHY address At the de-assertion of reset, this pin value is latched by the chip.

21 NAND_Tree# Ipu/Opu

NAND Tree Mode: Pull-up (default) = Disable Pull-down = Enable At the de-assertion of reset, this pin value is latched by the chip.

Micrel, Inc. KSZ8081MNX/KSZ8081RNB August 19, 2015 14 Revision 1.4 Pin Configuration – KSZ8081RNB 32-Pin 5mm × 5mm QFN

Micrel, Inc. KSZ8081MNX/KSZ8081RNB August 19, 2015 15 Revision 1.4 Pin Description – KSZ8081RNB Pin Number Pin Name Type(6) Pin Function capacitors to ground. 3 VDDA_3.3 P 3.3V analog VDD. 4 RXM I/O Physical receive or transmit signal (− differential). 5 RXP I/O Physical receive or transmit signal (+ differential). 6 TXM I/O Physical transmit or receive signal (− differential). 7 TXP I/O Physical transmit or receive signal (+ differential). 8 XO O Crystal feedback for 25MHz crystal. This pin is a no connect if an oscillator or external clock source is used.

9 XI I

25MHz Mode: 25MHz ±50ppm Crystal / Oscillator / External Clock Input 50MHz Mode: 50MHz ±50ppm Oscillator / External Clock Input 10 REXT I Set PHY transmit output current. Connect a 6.49kΩ resistor to ground on this pin. 11 MDIO Ipu/Opu Management Interface (MII) Data I/O. This pin has a weak pull-up, is open-drain, and requires an external 1.0kΩ pull-up resistor. 12 MDC Ipu Management Interface (MII) Clock Input. This clock pin is synchronous to the MDIO data pin.

13 PHYAD0 Ipu/O

The pull-up/pull-down value is latched as PHYADDR[0] at the de-assertion of reset. See the Strapping Options – KSZ8081RNB section for details.

14 PHYAD1 Ipd/O

The pull-up/pull-down value is latched as PHYADDR[1] at the de-assertion of reset. See the Strapping Options – KSZ8081RNB section for details. RXD1/ PHYAD2 Ipd/O RMII Mode: RMII Receive Data Output1. Config Mode: The pull-up/pull-down value is latched as PHYADDR[2] at the de- assertion of reset. See the Strapping Options – KSZ8081RNB section for details. RXD0/ DUPLEX Ipu/O RMII Mode: RMII Receive Data Output0. Config Mode: The pull-up/pull-down value is latched as DUPLEX at the de-assertion of reset. See the Strapping Options – KSZ8081RNB section for details. Notes: 6. P = Power supply. GND = Ground. I = Input. O = Output. I/O = Bi-directional. Ipu = Input with internal pull-up (see Electrical Characteristics for value). Ipu/O = Input with internal pull-up (see Electrical Characteristics for value) during power-up/reset; output pin otherwise. Ipd/O = Input with internal pull-down (see Electrical Characteristics for value) during power-up/reset; output pin otherwise. Ipu/Opu = Input with internal pull-up (see Electrical Characteristics for value) and output with internal pull-up (see Electrical Characteristics for value). NC = Pin is not bonded to the die. 7. RMII RX Mode: The RXD[1:0] bits are synchronous with the 50MHz RMII Reference Clock. For each clock period in which CRS_DV is asserted, two bits of recovered data are sent by the PHY to the MAC.

Micrel, Inc. KSZ8081MNX/KSZ8081RNB August 19, 2015 16 Revision 1.4 Pin Description – KSZ8081RNB (Continued) Pin Number Pin Name Type(6) Pin Function 17 VDDIO P 3.3V, 2.5V, or 1.8V digital VDD. CRS_DV/ CONFIG2 Ipd/O RMII Mode: RMII Carrier Sense/Receive Data Valid Output. Config Mode: The pull-up/pull-down value is latched as CONFIG2 at the de-assertion of reset. See the Strapping Options – KSZ8081RNB section for details. REF_CLK/ B-CAST_OFF Ipd/O RMII Mode: 25MHz Mode. This pin provides the 50MHz RMII reference clock output to the MAC. See also XI (Pin 9). 50MHz mode: This pin is a no connect. See also XI (Pin 9). Config Mode: The pull-up/pull-down value is latched as B-CAST_OFF at the de- assertion of reset. See the Strapping Options – KSZ8081RNB section for details. RXER/ ISO Ipd/O RMII Mode: RMII Receive Error Output. Config Mode: The pull-up/pull-down value is latched as ISOLATE at the de-assertion of reset. See the Strapping Options – KSZ8081RNB section for details. INTRP/ NAND_Tree# Ipu/Opu Interrupt Output: Programmable Interrupt Output. This pin has a weak pull-up, is open-drain, and requires an external 1.0kΩ pull-up resistor. Config Mode: The pull-up/pull-down value is latched as NAND Tree# at the de- assertion of reset. See the Strapping Options – KSZ8081RNB section for details. 22 NC - No Connect. This pin is not bonded and can be left floating. 23 TXEN I RMII Transmit Enable input. 24 TXD0 I RMII Transmit Data Input0. 25 TXD1 I RMII Transmit Data Input1. 26 NC - No Connect. This pin is not bonded and can be left floating. 27 NC - No Connect. This pin is not bonded and can be left floating. 28 CONFIG0 Ipd/O The pull-up/pull-down value is latched as CONFIG0 at the de-assertion of reset. See the Strapping Options – KSZ8081RNB section for details. 29 CONFIG1 Ipd/O The pull-up/pull-down value is latched as CONFIG1 at the de-assertion of reset. See the Strapping Options – KSZ8081RNB section for details. Note: 8. RMII TX Mode: The TXD[1:0] bits are synchronous with the 50MHz RMII Reference Clock. For each clock period in which TXEN is asserted, two bits of data are received by the PHY from the MAC.

Micrel, Inc. KSZ8081MNX/KSZ8081RNB August 19, 2015 17 Revision 1.4 Pin Description – KSZ8081RNB (Continued) Pin Number Pin Name Type(6) Pin Function LED0/ NWAYEN Ipu/O LED Output: Programmable LED0 Output. Config Mode: Latched as auto-negotiation enable (Register 0h, Bit [12]) at the de- assertion of reset. See the Strapping Options – KSZ8081RNB section for details. The LED0 pin is programmable using Register 1Fh bits [5:4], and is defined as follows: LED Mode = [00] Link/Activity Pin State LED Definition No link High OFF Link Low ON Activity Toggle Blinking LED Mode = [01] Link Pin State LED Definition No link High OFF Link Low ON LED Mode = [10], [11] Reserved LED1/ SPEED Ipu/O LED Output: Programmable LED1 Output. Config Mode: Latched as Speed (Register 0h, Bit [13]) at the de-assertion of reset. See the Strapping Options – KSZ8081RNB section for details. The LED1 pin is programmable using Register 1Fh bits [5:4], and is defined as follows: LED Mode = [00] Speed Pin State LED Definition 10Base-T High OFF 100Base-TX Low ON LED Mode = [01] Activity Pin State LED Definition No activity High OFF Activity Toggle Blinking LED Mode = [10], [11] Reserved 32 RST# Ipu Chip Reset (active low). PADDLE GND GND Ground.

Micrel, Inc. KSZ8081MNX/KSZ8081RNB August 19, 2015 18 Revision 1.4 Strapping Options – KSZ8081RNB The strap-in pins are latched at the de- assertion of reset. In some systems, the MAC RMII receive input pins may drive high/low during power -up or reset, and consequently cause the PHY strap- in pins on the RMII signals to be latched to unintended high/low states. In this case, external pull -ups (4.7kΩ) or pull -downs (1.0kΩ) should be added on these PHY strap-in pins to ensure that the intended values are strapped-in correctly. Pin Number Pin Name Type(9) Pin Function PHYAD2 PHYAD1 PHYAD0 Ipd/O Ipd/O Ipu/O PHYAD[2:0] is latched at de-assertion of reset and is configurable to any value from 0 to 7 with PHY Address 1 as the default value. PHY Address 0 is assigned by default as the broadcast PHY address, but it can be assigned as a unique PHY address after pulling the B-CAST_OFF strapping pin high or writing a ‘1’ to Register 16h, Bit [9]. PHY Address bits [4:3] are set to 00 by default. CONFIG2 CONFIG1 CONFIG0 Ipd/O Ipd/O Ipd/O The CONFIG[2:0] strap-in pins are latched at the de-assertion of reset. CONFIG[2:0] Mode

001 RMII

101 RMII back-to-back

000, 010 – 100, 110, 111 Reserved – not used Pull-up = Enable Pull-down (default) = Disable At the de-assertion of reset, this pin value is latched into Register 0h, Bit [10]. Pull-up (default) = 100Mbps Pull-down = 10Mbps At the de-assertion of reset, this pin value is latched into Register 0h, Bit [13] as the speed select, and also is latched into Register 4h (auto-negotiation advertisement) as the speed capability support. Pull-up (default) = Half-duplex Pull-down = Full-duplex At the de-assertion of reset, this pin value is latched into Register 0h, Bit [8]. Nway auto-negotiation enable Pull-up (default) = Enable auto-negotiation Pull-down = Disable auto-negotiation At the de-assertion of reset, this pin value is latched into Register 0h, Bit [12]. Broadcast off – for PHY Address 0 Pull-up = PHY Address 0 is set as an unique PHY address Pull-down (default) = PHY Address 0 is set as a broadcast PHY address At the de-assertion of reset, this pin value is latched by the chip. Pull-up (default) = Disable Pull-down = Enable At the de-assertion of reset, this pin value is latched by the chip. Note: 9. Ipu/O = Input with internal pull-up (see Electrical Characteristics for value) during power-up/reset; output pin otherwise. Ipd/O = Input with internal pull-down (see Electrical Characteristics for value) during power-up/reset; output pin otherwise. Ipu/Opu = Input with internal pull-up (see Electrical Characteristics for value) and output with internal pull-up (see Electrical Characteristics for value).

Micrel, Inc. KSZ8081MNX/KSZ8081RNB August 19, 2015 19 Revision 1.4 Functional Description: 10Base-T/100Base-TX Transceiver The KSZ8081 is an integrated single 3.3V supply Fast Ethernet transceiver. It is fully compliant with the IEEE 802.3 Specification, and reduces board cost and simplifies board layout by using on -chip terminat ion resistors for the two differential pairs and by integrating the regulator to supply the 1.2V core. On the copper media side, the KSZ8081 supports 10Base- T and 100Base-TX for transmission and reception of data over a standard CAT-5 unshielded twisted pair (UTP) cable, and HP Auto MDI/MDI-X for reliable detection of and correction for straight-through and crossover cables. On the MAC processor side, the KSZ8081MNX offers the Media Independent Interface (MII) and the KSZ8081RNB offers the Reduced Media Ind ependent Interface (RMII) for direct connection with MII and RMII compliant Ethernet MAC processors and switches, respectively. The MII management bus option gives the MAC processor complete access to the KSZ8081 control and status registers. Additionally, an interrupt pin eliminates the need for the processor to poll for PHY status change. The KSZ8081MNX/RNB is used to refer to both KSZ8081MNX and KSZ8081RNB versions in this datasheet. 100Base-TX Transmit The 100Base- TX transmit function performs parallel -to-serial conversion, 4B/5B encoding, scrambling, NRZ -to-NRZI conversion, and MLT3 encoding and transmission. The circuitry starts with a parallel -to-serial conversion, which converts the MII data from the MAC into a 125MHz serial bit stream. The data and control stream is then converted into 4B/5B coding and followed by a scrambler. The serialized data is further converted from NRZ -to-NRZI format, and then transmitted in MLT3 current output. The output current is set by an external 6.49kΩ 1% resistor for the 1:1 transformer ratio. The output signal has a typical rise/fall time of 4ns and complies with the ANSI TP -PMD standard regarding amplitude balance, overshoot, and timing jitter. The wave- shaped 10Base- T output is also incorporated into the 100Base- TX transmitter. 100Base-TX Receive The 100Base- TX receiver function performs adaptive equalization, DC restoration, MLT3- to-NRZI conversion, data and clock recovery, NRZI-to-NRZ conversion, de-scrambling, 4B/5B decoding, and serial-to-parallel conversion. The receiving side starts with the equalization filter to compensate for inter -symbol interference (ISI) over the twisted pair cable. Because the amplitude loss and phase distortion is a function of the cable length, the equalizer must adjust its characteristics to optimize performance. In this design, the variable equalizer makes an initial estimation based on comparisons of incoming signal strength against some known cable characteristics, then tunes itself for optimization. This is an ongoing process and self-adjusts against environmental changes such as temperature variations. Next, the equalized signal goes through a DC -restoration and data- conversion block. The DC -restoration circuit compensates for the effect of baseline wander and improves the dynamic range. The differential data- conversion circuit converts MLT3 format back to NRZI. The slicing threshold is also adaptive. The clock-recovery circuit extracts the 125MHz clock from the edges of the NRZI signal. This recovered clock is then used to convert the NRZI signal to NRZ format. This signal is sent through the de- scrambler, then the 4B/5B decoder. Finally, the NRZ serial data is converted to MII format and provided as the input data to the MAC. Scrambler/De-Scrambler (100Base-TX Only) The scrambler spreads the power spectrum of the transmitted signal to reduce electromagnetic interference (EMI) and baseline wander. The de-scrambler recovers the scrambled signal. 10Base-T Transmit The 10Base-T drivers are incorporated with the 100Base- TX drivers to al low for transmission using the same magnetic. The drivers perform internal wave- shaping and pre- emphasis, and output 10Base- T signals with a typical amplitude of 2.5V peak. The 10Base- T signals have harmonic contents that are at least 27dB below the fundam ental frequency when driven by an all-ones Manchester-encoded signal.

Micrel, Inc. KSZ8081MNX/KSZ8081RNB August 19, 2015 20 Revision 1.4 10Base-T Receive On the receive side, input buffer and level detecting squelch circuits are used. A differential input receiver circuit and a phase-locked loop (PLL) performs the decoding function. The Manchester -encoded data stream is separated into clock signal and NRZ data. A squelch circuit rejects signals with levels less than 400mV, or with short pulse widths, to prevent noise at the RXP and RXM inputs from falsely triggering the decoder. When the input exceeds the squelch limit, the PLL locks onto the incoming signal and the KSZ8081MNX/RNB decodes a data frame. The receive clock is kept active during idle periods between data receptions. SQE and Jabber Function (10Base-T Only) In 10Base-T operation, a short pulse is put out on the COL pin after each frame is transmitted. This SQE test is needed to test the 10Base- T transmit/receive path. If transmit enable (TXEN) is high for more than 20ms (jabbering), the 10Base- T transmitter is dis abled and COL is asserted high. If TXEN is then driven low for more than 250ms, the 10Base- T transmitter is re-enabled and COL is de-asserted (returns to low). PLL Clock Synthesizer The KSZ8081MNX/RNB generates all internal clocks and all external clocks f or system timing from an external 25MHz crystal, oscillator, or reference clock. For the KSZ8081RNB in RMII 50MHz clock mode, these clocks are generated from an external 50MHz oscillator or system clock. Auto-Negotiation The KSZ8081MNX/RNB conforms to the auto-negotiation protocol, defined in Clause 28 of the IEEE 802.3 Specification. Auto-negotiation allows unshielded twisted pair (UTP) link partners to select the highest common mode of operation. During auto-negotiation, link partners advertise capabili ties across the UTP link to each other and then compare their own capabilities with those they received from their link partners. The highest speed and duplex setting that is common to the two link partners is selected as the mode of operation. The following list shows the speed and duplex operation mode from highest to lowest priority.

• Priority 1: 100Base-TX, full-duplex
• Priority 2: 100Base-TX, half-duplex
• Priority 3: 10Base-T, full-duplex
• Priority 4: 10Base-T, half-duplex If auto-negotiation is not supported or the KSZ8081MNX/RNB link partner is forced to bypass auto- negotiation, then the KSZ8081MNX/RNB sets its operating mode by observing the signal at its receiver. This is known as parallel detection, which allows the KSZ8081MNX/RNB to establish a link by listening for a fixed signal protocol in the absence of the auto- negotiation advertisement protocol. Auto-negotiation is enabled by either hardware pin strapping (NWAYEN, Pin 42) or software (Register 0h, Bit [12]). By default, auto- negotiation is enabled after power -up or hardware reset. After that, auto- negotiation can be enabled or disabled by Register 0h, Bit [12]. If auto-negotiation is disabled, the speed is set by Register 0h, Bit [13], and the duplex is set by Register 0h, Bit [8]. The auto-negotiation link-up process is shown in Figure 1.

Figure 1. Auto-Negotiation Flow Chart

• Pin count is 15 pins (6 pins for data transmission, 7 pins for data reception, and 2 pins for carrier and collision indication).
• 10Mbps and 100Mbps data rates are supported at both half- and full-duplex.
• Data transmission and reception are independent and belong to separate signal groups.
• Transmit data and receive data are each 4 bits wide, a nibble. By default, the KSZ8081MNX is configured to MII mode after it is powered up or hardware reset with the following:
• A 25MHz crystal connected to XI, XO (pins 9, 8), or an external 25MHz clock source (oscillator) connected to XI.
• The CONFIG[2:0] strapping pins (pins 18, 29, 28) set to 000 (default setting). MII Signal Definition Table 1 describes the MII signals. Refer to Clause 22 of the IEEE 802.3 Specification for detailed information.

Table 1. MII Signal Definition 2.5MHz for 10Mbps operation and 25MHz for 100Mbps operation. before the first TXC following the final nibble of a frame. TXEN transitions synchronously with respect to TXC.

Micrel, Inc. KSZ8081MNX/KSZ8081RNB August 19, 2015 23 Revision 1.4 Transmit Data[3:0] (TXD[3:0]) TXD[3:0] transitions synchronously with respect to TXC. When TXEN is asserted, TXD[3:0] are accepted by the PHY for transmission. TXD[3:0] is 0 0 to indicate idle when TXEN is de- asserted. Values other than 00 on TXD[3:0] while TXEN is de-asserted are ignored by the PHY. Receive Clock (RXC) RXC provides the timing reference for RXDV, RXD[3:0], and RXER.

• In 10Mbps mode, RXC is recovered from the line while the carrier is active. RXC is derived from the PHY’s reference clock when the line is idle or the link is down.
• In 100Mbps mode, RXC is continuously recovered from the line. If the link is down, RXC is derived from the PHY’s reference clock. RXC is 2.5MHz for 10Mbps operation and 25MHz for 100Mbps operation. Receive Data Valid (RXDV) RXDV is driven by the PHY to indicate that the PHY is presenting recovered and decoded nibbles on RXD[3:0].
• In 10Mbps mode, RXDV is asserted with the first nibble of the start-of-frame delimiter (SFD), 5D, and remains asserted until the end of the frame.
• In 100Mbps mode, RXDV is asserted from the first nibble of the preamble to the last nibble of the frame. RXDV transitions synchronously with respect to RXC. Receive Data[3:0] (RXD[3:0]) RXD[3:0] transitions synchronously with respect to RXC. For each clock period in which RXDV is asserted, RXD[3:0] transfers a nibble of recovered data from the PHY. Receive Error (RXER) RXER is asserted for one or more RXC periods to indicate that a symbol error (for example, a coding error that a PHY can detect that may otherwise be undetectable by the MAC sub- layer) was detected somewhere in the frame being transferred from the PHY. RXER transitions synchronously with respect to RXC. While RXDV is de-asserted, RXER has no effect on the MAC. Carrier Sense (CRS) CRS is asserted and de-asserted as follows:
• In 10Mbps mode, CRS assertion is based on the reception of valid preambles. CRS de- assertion is based on the reception of an end-of-frame (EOF) marker.
• In 100Mbps mode, CRS is asserted when a start-of-stream delimiter or /J/K symbol pair is detected. CRS is de- asserted when an end-of-stream delimiter or /T/R symbol pair is detected. Additionally, the PMA layer de- asserts CRS if IDLE symbols are received without /T/R. Collision (COL) COL is asserted in half -duplex mode whenever the transmitter and receiver are simultaneously active on the line. This informs the MAC that a collision has occurred during its transmission to the PHY. COL trans itions asynchronously with respect to TXC and RXC. MII Signal Diagram The KSZ8081MNX MII pin connections to the MAC are shown in Figure 2.

Figure 2. KSZ8081MNX MII Interface

• Pin count is 8 pins (3 pins for data transmission, 4 pins for data reception, and 1 pin for the 50MHz reference clock).
• 10Mbps and 100Mbps data rates are supported at both half- and full-duplex.
• Data transmission and reception are independent and belong to separate signal groups.
• Transmit data and receive data are each 2 bits wide, a dibit. RMII – 25MHz Clock Mode The KSZ8081RNB is configured to RMII – 25MHz clock mode after it is powered up or hardware reset with the following:
• A 25MHz crystal connected to XI, XO (pins 9, 8), or an external 25MHz clock source (oscillator) connected to XI.
• The CONFIG[2:0] strapping pins (pins 18, 29, 28) set to 001.
• Register 1Fh, Bit [7] is set to 0 (default value) to select 25MHz clock mode. RMII – 50MHz Clock Mode The KSZ8081RNB is configured to RMII – 50MHz clock mode after it is powered up or hardware reset with the following:
• An external 50MHz clock source (oscillator) connected to XI (Pin 9).
• The CONFIG[2:0] strapping pins (pins 18, 29, 28) set to 001.
• Register 1Fh, Bit [7] is set to 1 to select 50MHz clock mode. RMII Signal Definition Table 2 describes the RMII signals. Refer to RMII Specification v1.2 for detailed information.

Table 2. RMII Signal Defintion 9) and leaves the REF_CLK (Pin 19) as a no connect.

Micrel, Inc. KSZ8081MNX/KSZ8081RNB August 19, 2015 26 Revision 1.4 Transmit Enable (TXEN) TXEN indicates that the MAC is presenting dibits on TXD[1:0] for transmission. It is asserted synchronously with the first dibit of the preamble and remains asserted while all dibits to be transmitted are presented on the RMII. It is negated before the first REF_CLK following the final dibit of a frame. TXEN transitions synchronously with respect to REF_CLK. Transmit Data[1:0] (TXD[1:0]) TXD[1:0] transitions synchronously with respect to REF_CLK. When TXEN is asserted, the PHY accepts TXD[1:0] for transmission. TXD[1:0] is 00 to indicate idle when TXEN is de- asserted. The PHY ignores values other than 00 on TXD[1:0] while TXEN is de-asserted. Carrier Sense/Receive Data Valid (CRS_DV) The PHY asserts CRS_DV when the receive medium is non- idle. It is asserted asynchronously when a carrier is detected. This happens when squelch is passed in 10Mbps mode, and when two non- contiguous 0s in 10 bits are detected in 100Mbps mode. Loss of carrier results in the de-assertion of CRS_DV. While carrier detection criteria are met, CRS_DV remains asserted continuously from the first recovered dibit of the frame through the final recovered dibit. It is negated before the first REF_CLK that follows the final dibit. The data on RXD[1:0] is considered valid after CRS_DV is asserted. However, because the assertion of CRS_DV is asynchronous relative to REF_CLK, the data on RXD[1:0] is 00 until receive signals are properly decoded. Receive Data[1:0] (RXD[1:0]) RXD[1:0] transitions synchronously with respect to REF_CLK. For each clock period in which CRS_DV is asserted, RXD[1:0] transfers two bits of recovered data from the PHY. RXD[1:0] is 00 to indicate idle when CRS_DV is de-asserted. The MAC ignores values other than 00 on RXD[1:0] while CRS_DV is de-asserted. Receive Error (RXER) RXER is asserted for one or more REF_CLK periods to indicate that a symbol error (for example, a coding error that a PHY can detect that may otherwise be undetectable by the MAC sub- layer) was detected somewhere in the frame being transferred from the PHY. RXER transitions synchronously with respect to REF_ CLK. . While CRS_DV is de- asserted, RXER has no effect on the MAC. Collision Detection (COL) The MAC regenerates the COL signal of the MII from TXEN and CRS_DV. RMII Signal Diagram The KSZ8081RNB RMII pin connections to the MAC for 25MHz clock mode are sho wn in Figure 3. The connections for 50MHz clock mode are shown in Figure 4.

Two KSZ8081MNX/RNB devices can be connected back-to-back to form a 100Base-TX copper repeater. Figure 5. KSZ8081MNX/RNB to KSZ8081MNX/RNB Back-to-Back Copper Repeater

• Strapping pin CONFIG[2:0] (Pins 18, 29, 28) set to 110
• A common 25MHz reference clock connected to XI (Pin 9) of both KSZ8081MNX devices
• MII signals connected as shown in Table 3.

Table 3. MII Signal Connection for MII Back-to-Back Mode (100Base-TX Copper Repeater)

• Strapping pin CONFIG[2:0] (Pins 18, 29, 28) set to 101
• A common 50MHz reference clock connected to XI (Pin 9) of both KSZ8081RNB devices
• RMII signals connected as shown in Table 4.

Table 4. RMII Signal Connection for RMII Back-to-Back Mode (100Base-TX Copper Repeater)

• A physical connection that incorporates the clock line (MDC) and the data line (MDIO).
• A specific protocol that operates across the physical connection mentioned earlier, which allows the external controller to communicate with one or more PHY devices.
• A set of 16-bit MDIO registers. Registers [0:8] are standard registers, and their functions are defined in the IEEE 802.3 Specification. The additional registers are provided for expanded functionality. See the “Register Map” section for details. As the default, the KSZ8081MNX/RNB supports unique PHY addresses 1 to 7, and broadcast PHY address 0. The latter is defined in the IEEE 802.3 Specification, and can be used to read/writ e to a single KSZ8081MNX/RNB device, or write to multiple KSZ8081MNX/RNB devices simultaneously. PHY address 0 can optionally be disabled as the broadcast address by either hardware pin strapping (B -CAST_OFF, Pin 19) or software (Register 16h, Bit [9]), and assigned as a unique PHY address. The PHYAD[2:0] strapping pins are used to assign a unique PHY address between 0 and 7 to each KSZ8081MNX/RNB device. The MIIM interface can operates up to a maximum clock speed of 10MHz MAC clock. Table 5 shows the MII management frame format for the KSZ8081MNX/RNB.

Table 5. MII Management Frame Format for the KSZ8081MNX/RNB which interrupt conditions have occurred. The interrupt status bits are cleared after reading Register 1Bh. Bit [9] of Register 1Fh sets the interrupt level to active high or active low. The default is active low. registers. Additionally, an interrupt pin eliminates the need for the processor to poll the PHY for status change. receive pairs from the link partner and assigns transmit and receive pairs to the KSZ8081MNX/RNB accordingly. selected by Register 1Fh, Bit [14] if HP Auto MDI/MDI-X is disabled. An isolation transformer with symmetrical transmit and receive data paths is recommended to support Auto MDI/MDI -X. Table 6 shows how the IEEE 802.3 Standard defines MDI and MDI-X. Table 6. MDI/MDI-X Pin Definition

1 TX+ 1 RX+

2 TX− 2 RX−

3 RX+ 3 TX+

6 RX− 6 TX−

The KSZ8081MNX/RNB supports the following loopback operations to verify analog and/or digital data paths.

• Local (digital) loopback
• Remote (analog) loopback Local (Digital) Loopback This loopback mode checks the MII/RMII transmit and receive data paths between the KSZ8081MNX/RNB and the external MAC, and is supported for both speeds (10/100Mbps) at full-duplex. The loopback data path is shown in Figure 8. 1. The MII/RMII MAC transmits frames to the KSZ8081MNX/RNB. 2. Frames are wrapped around inside the KSZ8081MNX/RNB. 3. The KSZ8081MNX/RNB transmits frames back to the MII/RMII MAC. 4. Except the frames back to the RMII MAC, the transmit frames also go out from the copper port.

Figure 8. Local (Digital) Loopback The following programming action and register settings are used for local loopback mode.

• Set Register 0h, Bit [14] = 1 // Enable local loopback mode Bit [13] = 0/1 // Select 10Mbps/100Mbps speed Bit [12] = 0 // Disable auto-negotiation Bit [8] = 1 // Select full-duplex mode If don’t want the frames go out from the copper port in the local loopback, please follow the steps as below. 1. Set register 1Fh bit [3] to ‘1’ to disable the transmitter. 2. Run local loopback test as above. 3. Set register 1Fh bit [3] to ‘0’ to enable the transmitter.

data paths between the KSZ8081MNX/RNB and its link partner, and is supported for 100Base- TX full-duplex mode only. The loopback data path is shown in Figure 9.

1. The Fast Ethernet (100Base-TX) PHY link partner transmits frames to the KSZ8081MNX/RNB.
2. Frames are wrapped around inside the KSZ8081MNX/RNB.
3. The KSZ8081MNX/RNB transmits frames back to the Fast Ethernet (100Base-TX) PHY link partner.

Figure 9. Remote (Analog) Loopback The following programming steps and register settings are used for remote loopback mode. or just auto-negotiate and link up at 100Base-TX full-duplex mode with the link partner.

Micrel, Inc. KSZ8081MNX/KSZ8081RNB August 19, 2015 34 Revision 1.4 LinkMD® Cable Diagnostic The LinkMD function uses time- domain reflectometry (TDR) to analyze the cabling plant for common cabling problems. These include open circuits, short circuits, and impedance mismatches. LinkMD works by sending a pulse of known amplitude and duration down the MDI or MDI -X pair, then analyzing the shape of the reflected signal to determine the type of fault. The time duration for the reflected signal to return provides the approximate distance to the cabling fault. The LinkMD function processes this TDR information and presents it as a numerical value that can be translated to a cable distance. LinkMD is initiated by accessing Register 1Dh, the LinkMD Control/Status register, in conjunction with Register 1Fh, the PHY Control 2 register. The latter register is used to disable Auto MDI/MDI -X and to select either MDI or MDI -X as the cable differential pair for testing. Usage The following is a sample procedure for using LinkMD with Registers 1Dh and 1Fh: 3. Disable auto MDI/MDI-X by writing a ‘1’ to Register 1Fh, bit [13]. 4. Start cable diagnostic test by writing a ‘1’ to Register 1Dh, bit [15]. This enable bit is self-clearing. 5. Wait (poll) for Register 1Dh, bit [15] to return a ‘0’, and indicating cable diagnostic test is completed. 6. Read cable diagnostic test results in Register 1Dh, bits [14:13]. The results are as follows: 00 = normal condition (valid test) 01 = open condition detected in cable (valid test) 10 = short condition detected in cable (valid test) 11 = cable diagnostic test failed (invalid test) The ‘11’ case, invalid test, occurs when the device is unable to shut down the link partner. In this instance, the test is not run, since it would be impossible for the device to determine if the detected signal is a reflection of the signal generated or a signal from another source. 7. Get distance to fault by concatenating Register 1Dh, bits [8:0] and multiplying the result by a constant of 0. 38. The distance to the cable fault can be determined by the following formula: D (distance to cable fault) = 0.38 x (Register 1Dh, bits [8:0]) D (distance to cable fault) is expressed in meters. Concatenated value of Registers 1Dh bits [8:0] should be converted to decimal before multiplying by 0.38. The constant (0.38) may be calibrated for different cabling conditions, including cables with a velocity of propagation that varies significantly from the norm.

• Enabling NAND tree mode
• Pulling all NAND tree input pins high
• Driving each NAND tree input pin low, sequentially, according to the NAND tree pin order
• Checking the NAND tree output to make sure there is a toggle high-to-low or low-to-high for each NAND tree input driven low Table 7 and Table 8 list the NAND tree pin orders for KSZ8081MNX and KSZ8081RNB, respectively.

Table 7. NAND Tree Test Pin Order for KSZ8081MNX

11 MDIO Input

12 MDC Input

15 RXD1 Input

16 RXD0 Input

18 CRS_DV Input

19 REF_CLK Input

21 INTRP Input

23 TXEN Input

30 LED0 Input

24 TXD0 Input

25 TXD1 Output

is required, please use KSZ8091MNX device that supports all the required pins.

Table 8. NAND Tree Test Pin Order for KSZ8081RNB

31 LED1 Input

1. Enable NAND tree mode using either hardware (NAND_Tree#, Pin 21) or software (Register 16h, Bit [5]).
2. Use board logic to drive all KSZ8081MNX/RNB NAND tree input pins high.
3. Use board logic to drive each NAND tree input pin, in KSZ8081MNX/RNB NAND tree pin order, as follows:

the first pin is connected properly. b. Leave the first pin (MDIO) low. that the second pin is connected properly. d. Leave the first pin (MDIO) and the second pin (MDC) low. e. Continue with this sequence until all KSZ8081MNX/RNB NAND tree input pins have been toggled.

Micrel, Inc. KSZ8081MNX/KSZ8081RNB August 19, 2015 37 Revision 1.4 Power Management The KSZ8081MNX/RNB incorporates a number of power -management modes and features that provide methods to consume less energy. These are discussed in the following sections. Power-Saving Mode Power-saving mode is used to reduce the transceiver power consumption when the cable is unplugged. It is enabled by writing a ‘1’ to Register 1Fh, Bit [10], and is in effect when auto-negotiation mode is enabled and the cable is disconnected (no link). In this mode, the KSZ8081MNX/RNB shuts down all transceiver blocks, except for the transmitter, energy detect, and PLL circuits. By default, power-saving mode is disabled after power-up. Energy-Detect Power-Down Mode Energy-detect power -down (EDPD) mode is used to further reduce transceiver power consumption when the cable is unplugged. It is enabled by writing a ‘0’ to Register 18h, B it [11], and is in effect when auto- negotiation mode is enabled and the cable is disconnected (no link). EDPD mode works with the PLL off (set by writing a ‘1’ to Register 10h, B it [4] to automatically turn the PLL off in EDPD mode) to turn off all KSZ8081MNX/RNB transceiver blocks except the transmitter and energy-detect circuits. Power can be reduced further by extending the time interval between transmissions of link pulses to check for the presence of a link partner. The periodic transmission of link pulses is needed to ensure the KSZ808 1MNX/RNB and its link partner, when operating in the same low -power state and with Auto MDI/MDI-X disabled, can wake up when the cable is connected between them. By default, energy-detect power-down mode is disabled after power-up. Power-Down Mode Power-down mode is used to power down the KSZ8081MNX/RNB device when it is not in use after power -up. It is enabled by writing a ‘1’ to Register 0h, Bit [11]. In this mode, the KSZ8081MNX/RNB disables all internal functions except the MII management interface. The KSZ8081MNX/RNB exits (disables) power-down mode after Register 0h, Bit [11] is set back to ‘0’. Slow-Oscillator Mode Slow-oscillator mode is used to disconnect the input reference crystal/clock on XI ( Pin 8) and select the on- chip slow oscillator when th e KSZ8081MNX/RNB device is not in use after power -up. It is enabled by writing a ‘1’ to Register 11h, Bit [5]. Slow-oscillator mode works in conjunction with power -down mode to put the KSZ8081MNX/RNB device in the lowest power state, with all internal func tions disabled except the MII management interface. To properly exit this mode and return to normal PHY operation, use the following programming sequence: 1. Disable slow-oscillator mode by writing a ‘0’ to Register 11h, Bit [5]. 2. Disable power-down mode by writing a ‘0’ to Register 0h, Bit [11]. 3. Initiate software reset by writing a ‘1’ to Register 0h, Bit [15].

ground connections are shown in Figure 10 and Table 9 for 3.3V VDDIO. Figure 10. KSZ8081MNX/RNB Power and Ground Connections Table 9. KSZ8081MNX/RNB Power Pin Descriptions VDD_1.2 2 Decouple with 2.2µF and 0.1µF capacitors to ground. Connect to board’s 3.3V supply through a ferrite bead. Decouple with 22µF and 0.1µF capacitors to ground. Connect to board’s 3.3V supply for 3.3V VDDIO. Decouple with 22µF and 0.1µF capacitors to ground.

regulator current for the 1.2V core. Table 10. Typical Current/Power Consumption (VDDA_3.3 = 3.3V, VDDIO = 3.3V) Table 11. Typical Current/Power Consumption (VDDA_3.3 = 3.3V, VDDIO = 2.5V)

Table 12. Typical Current/Power Consumption (VDDA_3.3 = 3.3V, VDDIO = 1.8V)

Micrel, Inc. KSZ8081MNX/KSZ8081RNB August 19, 2015 41 Revision 1.4 Register Map Register Number (Hex) Description 0h Basic Control 1h Basic Status 2h PHY Identifier 1 3h PHY Identifier 2 4h Auto-Negotiation Advertisement 5h Auto-Negotiation Link Partner Ability 6h Auto-Negotiation Expansion 7h Auto-Negotiation Next Page 8h Link Partner Next Page Ability 9h Reserved 10h Digital Reserved Control 11h AFE Control 1 12h – 14h Reserved 15h RXER Counter 16h Operation Mode Strap Override 17h Operation Mode Strap Status 18h Expanded Control 19h – 1Ah Reserved 1Bh Interrupt Control/Status 1Ch Reserved 1Dh LinkMD Control/Status 1Eh PHY Control 1 1Fh PHY Control 2

Micrel, Inc. KSZ8081MNX/KSZ8081RNB August 19, 2015 42 Revision 1.4 Register Description Address Name Description Mode(10) Default Register 0h – Basic Control

0.15 Reset

1 = Software reset 0 = Normal operation This bit is self-cleared after a ‘1’ is written to it. RW/SC 0

0.14 Loopback

1 = Loopback mode 0 = Normal operation RW 0

0.13 Speed Select

1 = 100Mbps 0 = 10Mbps This bit is ignored if auto-negotiation is enabled (Register 0.12 = 1). RW Set by the SPEED strapping pin. See the Strapping Options – KSZ8081MNX section for details. 0.12 Auto- Negotiation Enable 1 = Enable auto-negotiation process 0 = Disable auto-negotiation process If enabled, the auto-negotiation result overrides the settings in registers 0.13 and 0.8. RW Set by the NWAYEN strapping pin. See the Strapping Options – KSZ8081MNX section for details.

0.11 Power-Down

1 = Power-down mode 0 = Normal operation If software reset (Register 0.15) is used to exit power-down mode (Register 0.11 = 1), two software reset writes (Register 0.15 = 1) are required. The first write clears power-down mode; the second write resets the chip and re- latches the pin strapping pin values. RW 0

0.10 Isolate

1 = Electrical isolation of PHY from MII/RMII 0 = Normal operation RW Set by the ISO strapping pin. See the Strapping Options – KSZ8081MNX section for details.

0.9 Restart Auto-

1 = Restart auto-negotiation process 0 = Normal operation. This bit is self-cleared after a ‘1’ is written to it. RW/SC 0

0.8 Duplex Mode

1 = Full-duplex 0 = Half-duplex RW The inverse of the DUPLEX strapping pin value. See the Strapping Options – KSZ8081MNX section for details.

0.7 Collision Test

1 = Enable COL test 0 = Disable COL test RW 0 0.6:0 Reserved Reserved RO 000_0000 Note: 10. RW = Read/Write. RO = Read only. SC = Self-cleared. LH = Latch high. LL = Latch low.

Micrel, Inc. KSZ8081MNX/KSZ8081RNB August 19, 2015 43 Revision 1.4 Register Description (Continued) Address Name Description Mode(10) Default Register 1h – Basic Status 1.15 100Base-T4 1 = T4 capable 0 = Not T4 capable RO 0 1.14 100Base-TX Full-Duplex 1 = Capable of 100Mbps full-duplex 0 = Not capable of 100Mbps full-duplex RO 1 1.13 100Base-TX Half-Duplex 1 = Capable of 100Mbps half-duplex 0 = Not capable of 100Mbps half-duplex RO 1 1.12 10Base-T Full-Duplex 1 = Capable of 10Mbps full-duplex 0 = Not capable of 10Mbps full-duplex RO 1 1.11 10Base-T Half-Duplex 1 = Capable of 10Mbps half-duplex 0 = Not capable of 10Mbps half-duplex RO 1 1.10:7 Reserved Reserved RO 000_0

1.6 No Preamble

1 = Preamble suppression 0 = Normal preamble RO 1 1.5 Auto- Negotiation Complete 1 = Auto-negotiation process completed 0 = Auto-negotiation process not completed RO 0

1.4 Remote Fault

1 = Remote fault 0 = No remote fault RO/LH 0 1.3 Auto- Negotiation Ability 1 = Can perform auto-negotiation 0 = Cannot perform auto-negotiation RO 1

1.2 Link Status

1 = Link is up 0 = Link is down RO/LL 0

1.1 Jabber Detect

1 = Jabber detected 0 = Jabber not detected (default is low) RO/LH 0

1.0 Extended

Capability 1 = Supports extended capability registers RO 1 Register 2h – PHY Identifier 1 2.15:0 PHY ID Number Assigned to the 3rd through 18th bits of the Organizationally Unique Identifier (OUI). KENDIN Communication’s OUI is 0010A1 (hex). RO 0022h Register 3h – PHY Identifier 2 3.15:10 PHY ID Number Assigned to the 19th through 24th bits of the Organizationally Unique Identifier (OUI). KENDIN Communication’s OUI is 0010A1 (hex). RO 0001_01 3.9:4 Model Number Six-bit manufacturer’s model number RO 01_0110 3.3:0 Revision Number Four-bit manufacturer’s revision number RO Indicates silicon revision

Micrel, Inc. KSZ8081MNX/KSZ8081RNB August 19, 2015 44 Revision 1.4 Register Description (Continued) Address Name Description Mode(10) Default Register 4h – Auto-Negotiation Advertisement

4.15 Next Page

1 = Next page capable 0 = No next page capability RW 0

4.14 Reserved Reserved RO 0

4.13 Remote Fault

1 = Remote fault supported 0 = No remote fault RW 0

4.12 Reserved Reserved RO 0

4.11:10 Pause [00] = No pause [10] = Asymmetric pause [01] = Symmetric pause [11] = Asymmetric and symmetric pause RW 00 4.9 100Base-T4 1 = T4 capable 0 = No T4 capability RO 0 4.8 100Base-TX Full-Duplex 1 = 100Mbps full-duplex capable 0 = No 100Mbps full-duplex capability RW Set by the SPEED strapping pin. See the Strapping Options – KSZ8081MNX section for details. 4.7 100Base-TX Half-Duplex 1 = 100Mbps half-duplex capable 0 = No 100Mbps half-duplex capability RW Set by the SPEED strapping pin. See the Strapping Options – KSZ8081MNX section for details. 4.6 10Base-T Full-Duplex 1 = 10Mbps full-duplex capable 0 = No 10Mbps full-duplex capability RW 1 4.5 10Base-T Half-Duplex 1 = 10Mbps half-duplex capable 0 = No 10Mbps half-duplex capability RW 1 4.4:0 Selector Field [00001] = IEEE 802.3 RW 0_0001 Register 5h – Auto-Negotiation Link Partner Ability

5.15 Next Page

1 = Next page capable 0 = No next page capability RO 0

5.14 Acknowledge

1 = Link code word received from partner 0 = Link code word not yet received RO 0

5.13 Remote Fault

1 = Remote fault detected 0 = No remote fault RO 0

5.12 Reserved Reserved RO 0

5.11:10 Pause [00] = No pause [10] = Asymmetric pause [01] = Symmetric pause [11] = Asymmetric and symmetric pause RO 00 5.9 100Base-T4 1 = T4 capable 0 = No T4 capability RO 0 5.8 100Base-TX Full-Duplex 1 = 100Mbps full-duplex capable 0 = No 100Mbps full-duplex capability RO 0

Micrel, Inc. KSZ8081MNX/KSZ8081RNB August 19, 2015 45 Revision 1.4 Register Description (Continued) Address Name Description Mode(10) Default Register 5h – Auto-Negotiation Link Partner Ability 5.7 100Base-TX Half-Duplex 1 = 100Mbps half-duplex capable 0 = No 100Mbps half-duplex capability RO 0 5.6 10Base-T Full-Duplex 1 = 10Mbps full-duplex capable 0 = No 10Mbps full-duplex capability RO 0 5.5 10Base-T Half-Duplex 1 = 10Mbps half-duplex capable 0 = No 10Mbps half-duplex capability RO 0 5.4:0 Selector Field [00001] = IEEE 802.3 RO 0_0001 Register 6h – Auto-Negotiation Expansion 6.15:5 Reserved Reserved RO 0000_0000_000

6.4 Parallel

1 = Fault detected by parallel detection 0 = No fault detected by parallel detection RO/LH 0 6.3 Link Partner Next Page Able 1 = Link partner has next page capability 0 = Link partner does not have next page capability RO 0

6.2 Next Page

1 = Local device has next page capability 0 = Local device does not have next page capability RO 1

6.1 Page Received

1 = New page received 0 = New page not received yet RO/LH 0 6.0 Link Partner Auto- Negotiation Able 1 = Link partner has auto-negotiation capability 0 = Link partner does not have auto-negotiation capability RO 0 Register 7h – Auto-Negotiation Next Page

7.15 Next Page

1 = Additional next pages will follow 0 = Last page RW 0

7.14 Reserved Reserved RO 0

7.13 Message Page

1 = Message page 0 = Unformatted page RW 1

7.12 Acknowledge2

1 = Will comply with message 0 = Cannot comply with message RW 0

7.11 Toggle

1 = Previous value of the transmitted link code word equaled logic 1 0 = Logic 0 RO 0 7.10:0 Message Field 11-bit wide field to encode 2048 messages RW 000_0000_0001

Micrel, Inc. KSZ8081MNX/KSZ8081RNB August 19, 2015 46 Revision 1.4 Register Description (Continued) Address Name Description Mode(10) Default Register 8h – Link Partner Next Page Ability

8.15 Next Page 1 = Additional next pages will follow

0 = Last page RO 0

8.14 Acknowledge 1 = Successful receipt of link word

0 = No successful receipt of link word RO 0

8.13 Message Page 1 = Message page

0 = Unformatted page RO 0

8.12 Acknowledge2 1 = Can act on the information

0 = Cannot act on the information RO 0

8.11 Toggle

1 = Previous value of transmitted link code word equal to logic 0 0 = Previous value of transmitted link code word equal to logic 1 RO 0 8.10:0 Message Field 11-bit wide field to encode 2048 messages RO 000_0000_0000 Register 10h – Digital Reserved Control 10.15:5 Reserved Reserved RW 0000_0000_000

10.4 PLL Off

1 = Turn PLL off automatically in EDPD mode 0 = Keep PLL on in EDPD mode. See also Register 18h, Bit [11] for EDPD mode RW 0 10.3:0 Reserved Reserved RW 0000 Register 11h – AFE Control 1 11.15:6 Reserved Reserved RW 0000_0000_00

11.5 Slow-Oscillator

Slow-oscillator mode is used to disconnect the input reference crystal/clock on the XI pin and select the on-chip slow oscillator when the KSZ8081MNX/RNB device is not in use after power-up. 1 = Enable 0 = Disable This bit automatically sets software power-down to the analog side when enabled. RW 0 11.4:0 Reserved Reserved RW 0_0000 Register 15h – RXER Counter 15.15:0 RXER Counter Receive error counter for symbol error frames RO/SC 0000h Register 16h – Operation Mode Strap Override 16.15 Reserved Factory Mode 0 = Normal operation 1 = Factory test mode If TXC (Pin 22) latches in a pull-up value at the de-assertion of reset, write a ‘0’ to this bit to clear Reserved Factory Mode. This bit applies only to KSZ8081MNX. RW Set by the pull-up/pull-down value of TXC (Pin 22). 16.14:11 Reserved Reserved RW 000_0

16.10 Reserved Reserved RO 0

16.9 B-CAST_OFF

1 = Override strap-in for B-CAST_OFF If bit is ‘1’, PHY Address 0 is non-broadcast. RW 0

Micrel, Inc. KSZ8081MNX/KSZ8081RNB August 19, 2015 47 Revision 1.4 Register Description (Continued) Address Name Description Mode(10) Default Register 16h – Operation Mode Strap Override

16.8 Reserved Reserved RW 0

16.7 MII B-to-B

1 = Override strap-in for MII back-to-back mode (also set Bit 0 of this register to ‘1’) This bit applies only to KSZ8081MNX. RW 0

16.6 RMII B-to-B

1 = Override strap-in for RMII Back-to-Back mode (also set Bit 1 of this register to ‘1’) This bit applies only to KSZ8081RNB. RW 0

16.5 NAND Tree

Override 1 = Override strap-in for NAND tree mode RW 0 16.4:2 Reserved Reserved RW 0_00

16.1 RMII Override

1 = Override strap-in for RMII mode This bit applies only to KSZ8081RNB. RW 0

16.0 MII Override

1 = Override strap-in for MII mode This bit applies only to KSZ8081MNX. RW 1 Register 17h – Operation Mode Strap Status 17.15:13 PHYAD[2:0] Strap-In Status [000] = Strap to PHY Address 0 [001] = Strap to PHY Address 1 [010] = Strap to PHY Address 2 [011] = Strap to PHY Address 3 [100] = Strap to PHY Address 4 [101] = Strap to PHY Address 5 [110] = Strap to PHY Address 6 [111] = Strap to PHY Address 7 RO 17.12:10 Reserved Reserved RO

17.9 B-CAST_OFF

1 = Strap to B-CAST_OFF If bit is ‘1’, PHY Address 0 is non-broadcast. RO

17.8 Reserved Reserved RO

17.7 MII B-to-B

1 = Strap to MII back-to-back mode This bit applies only to KSZ8081MNX. RO

17.6 RMII B-to-B

1 = Strap to RMII Back-to-Back mode This bit applies only to KSZ8081RNB. RO

17.5 NAND Tree

Strap-In Status 1 = Strap to NAND tree mode RO 17.4:2 Reserved Reserved RO

17.1 RMII Strap-In

1 = Strap to RMII mode This bit applies only to KSZ8081RNB. RO

17.0 MII Strap-In

1 = Strap to MII mode This bit applies only to KSZ8081MNX. RO

Micrel, Inc. KSZ8081MNX/KSZ8081RNB August 19, 2015 48 Revision 1.4 Register Description (Continued) Address Name Description Mode(10) Default Register 18h – Expanded Control 18.15:12 Reserved Reserved RW 0000

18.11 EDPD

Energy-detect power-down mode 1 = Disable 0 = Enable See also Register 10h, Bit [4] for PLL off. RW 1 18.10 100Base-TX Latency 1 = MII output is random latency 0 = MII output is fixed latency For both settings, all bytes of received preamble are passed to the MII output. This bit applies only to KSZ8081MNX. RW 0 18.9:7 Reserved Reserved RW 00_0 18.6 10Base-T Preamble Restore 1 = Restore received preamble to MII output 0 = Remove all seven bytes of preamble before sending frame (starting with SFD) to MII output This bit applies only to KSZ8081MNX, RW 0 18.5:0 Reserved Reserved RW 00_0000 Register 1Bh – Interrupt Control/Status 1B.15 Jabber Interrupt Enable 1 = Enable jabber interrupt 0 = Disable jabber interrupt RW 0 1B.14 Receive Error Interrupt Enable 1 = Enable receive error interrupt 0 = Disable receive error interrupt RW 0 1B.13 Page Received Interrupt Enable 1 = Enable page received interrupt 0 = Disable page received interrupt RW 0 1B.12 Parallel Detect Fault Interrupt Enable 1 = Enable parallel detect fault interrupt 0 = Disable parallel detect fault interrupt RW 0 1B.11 Link Partner Acknowledge Interrupt Enable 1 = Enable link partner acknowledge interrupt 0 = Disable link partner acknowledge interrupt RW 0 1B.10 Link-Down Interrupt Enable 1= Enable link-down interrupt 0 = Disable link-down interrupt RW 0 1B.9 Remote Fault Interrupt Enable 1 = Enable remote fault interrupt 0 = Disable remote fault interrupt RW 0 1B.8 Link-Up Interrupt Enable 1 = Enable link-up interrupt 0 = Disable link-up interrupt RW 0

Micrel, Inc. KSZ8081MNX/KSZ8081RNB August 19, 2015 49 Revision 1.4 Register Description (Continued) Address Name Description Mode(10) Default Register 1Bh – Interrupt Control/Status 1B.7 Jabber Interrupt 1 = Jabber occurred 0 = Jabber did not occur RO/SC 0 1B.6 Receive Error Interrupt 1 = Receive error occurred 0 = Receive error did not occur RO/SC 0 1B.5 Page Receive Interrupt 1 = Page receive occurred 0 = Page receive did not occur RO/SC 0 1B.4 Parallel Detect Fault Interrupt 1 = Parallel detect fault occurred 0 = Parallel detect fault did not occur RO/SC 0 1B.3 Link Partner Acknowledge Interrupt 1 = Link partner acknowledge occurred 0 = Link partner acknowledge did not occur RO/SC 0 1B.2 Link-Down Interrupt 1 = Link-down occurred 0 = Link-down did not occur RO/SC 0 1B.1 Remote Fault Interrupt 1 = Remote fault occurred 0 = Remote fault did not occur RO/SC 0 1B.0 Link-Up Interrupt 1 = Link-up occurred 0 = Link-up did not occur RO/SC 0 Register 1Dh – LinkMD Control/Status 1D.15 Cable Diagnostic Test Enable 1 = Enable cable diagnostic test. After test has completed, this bit is self-cleared. 0 = Indicates cable diagnostic test (if enabled) has completed and the status information is valid for read. RW/SC 0 1D.14:13 Cable Diagnostic Test Result [00] = Normal condition [01] = Open condition has been detected in cable [10] = Short condition has been detected in cable [11] = Cable diagnostic test has failed RO 00 1D.12 Short Cable Indicator 1 = Short cable (<10 meter) has been detected by LinkMD RO 0 1D.11:9 Reserved Reserved RW 000 1D.8:0 Cable Fault Counter Distance to fault RO 0_0000_0000

Micrel, Inc. KSZ8081MNX/KSZ8081RNB August 19, 2015 50 Revision 1.4 Register Description (Continued) Address Name Description Mode(10) Default Register 1Eh – PHY Control 1 1E.15:10 Reserved Reserved RO 0000_00 1E.9 Enable Pause (Flow Control) 1 = Flow control capable 0 = No flow control capability RO 0 1E.8 Link Status 1 = Link is up 0 = Link is down RO 0 1E.7 Polarity Status 1 = Polarity is reversed 0 = Polarity is not reversed RO 1E.6 Reserved Reserved RO 0 1E.5 MDI/MDI-X State 1 = MDI-X 0 = MDI RO 1E.4 Energy Detect 1 = Signal present on receive differential pair 0 = No signal detected on receive differential pair RO 0 1E.3 PHY Isolate 1 = PHY in isolate mode 0 = PHY in normal operation RW 0 1E.2:0 Operation Mode Indication [000] = Still in auto-negotiation [001] = 10Base-T half-duplex [010] = 100Base-TX half-duplex [011] = Reserved [100] = Reserved [101] = 10Base-T full-duplex [110] = 100Base-TX full-duplex [111] = Reserved RO 000 Register 1Fh – PHY Control 2 1F.15 HP_MDIX 1 = HP Auto MDI/MDI-X mode 0 = Micrel Auto MDI/MDI-X mode RW 1 1F.14 MDI/MDI-X Select When Auto MDI/MDI-X is disabled, 1 = MDI-X mode Transmit on RXP,RXM (pins 5, 4) and Receive on TXP,TXM (pins 7, 6) 0 = MDI mode Transmit on TXP,TXM (pins 7, 6) and Receive on RXP,RXM (pins 5, 4) RW 0 1F.13 Pair Swap Disable 1 = Disable Auto MDI/MDI-X 0 = Enable Auto MDI/MDI-X RW 0 1F.12 Reserved Reserved RW 0

Micrel, Inc. KSZ8081MNX/KSZ8081RNB August 19, 2015 51 Revision 1.4 Register Description (Continued) Address Name Description Mode(10) Default Register 1Fh – PHY Control 2 1F.11 Force Link 1 = Force link pass 0 = Normal link operation This bit bypasses the control logic and allows the transmitter to send a pattern even if there is no link. RW 0 1F.10 Power Saving 1 = Enable power saving 0 = Disable power saving RW 0 1F.9 Interrupt Level 1 = Interrupt pin active high 0 = Interrupt pin active low RW 0 1F.8 Enable Jabber 1 = Enable jabber counter 0 = Disable jabber counter RW 1 1F.7 RMII Reference Clock Select 1 = RMII 50MHz clock mode; clock input to XI (Pin 9) is 50MHz 0 = RMII 25MHz clock mode; clock input to XI (Pin 9) is 25MHz This bit applies only to KSZ8081RNB. RW 0 1F.6 Reserved Reserved RW 0 1F.5:4 LED Mode [00] = LED1: Speed LED0: Link/Activity [01] = LED1: Activity LED0: Link [10], [11] = Reserved RW 00 1F.3 Disable Transmitter 1 = Disable transmitter 0 = Enable transmitter RW 0 1F.2 Remote Loopback 1 = Remote (analog) loopback is enabled 0 = Normal mode RW 0 1F.1 Enable SQE Test 1 = Enable SQE test 0 = Disable SQE test RW 0 1F.0 Disable Data Scrambling 1 = Disable scrambler 0 = Enable scrambler RW 0

Micrel, Inc. KSZ8081MNX/KSZ8081RNB August 19, 2015 52 Revision 1.4 Absolute Maximum Ratings(11) Supply Voltage (VIN) Operating Ratings(12) Supply Voltage Ambient Temperature Electrical Characteristics(13) Symbol Parameter Condition Min. Typ. Max. Units Supply Current (VDDIO, VDDA_3.3 = 3.3V)(14) IDD1_3.3V 10Base-T Full-duplex traffic @ 100% utilization 41 mA IDD2_3.3V 100Base-TX Full-duplex traffic @ 100% utilization 47 mA IDD3_3.3V EDPD Mode Ethernet cable disconnected (reg. 18h.11 = 0) 20 mA IDD4_3.3V Power-Down Mode Software power-down (reg. 0h.11 = 1) 4 mA CMOS Level Inputs VIH Input High Voltage VDDIO = 3.3V 2.0 V VDDIO = 2.5V 1.8 VDDIO = 1.8V 1.3 VIL Input Low Voltage VDDIO = 3.3V 0.8 V VDDIO = 2.5V 0.7 VDDIO = 1.8V 0.5 |IIN| Input Current VIN = GND ~ VDDIO 10 µA CMOS Level Outputs VOH Output High Voltage VDDIO = 3.3V 2.4 V VDDIO = 2.5V 2.0 VDDIO = 1.8V 1.5 VOL Output Low Voltage VDDIO = 3.3V 0.4 V VDDIO = 2.5V 0.4 VDDIO = 1.8V 0.3 |Ioz| Output Tri-State Leakage 10 µA LED Output ILED Output Drive Current Each LED pin (LED0, LED1) 8 mA Notes: 11. Exceeding the absolute maximum ratings can damage the device. Stresses greater than the absolute maximum rating can cause permanent damage to the device. Operation of the device at these or any other conditions above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability. 12. The device is not guaranteed to function outside its operating ratings. 13. TA = 25°C. Specification for packaged product only. 14. Current consumption is for the single 3.3V supply KSZ8081MNX/RNB device only, and includes the transmit driver current and the 1.2V supply voltage (VDD_1.2) that are supplied by the KSZ8081MNX/RNB.

Micrel, Inc. KSZ8081MNX/KSZ8081RNB August 19, 2015 53 Revision 1.4 Electrical Characteristics(13) (Continued) Symbol Parameter Condition Min. Typ. Max. Units All Pull-Up/Pull-Down Pins (including Strapping Pins) pu Internal Pull-Up Resistance VDDIO = 3.3V 30 45 73 kΩ VDDIO = 2.5V 39 61 102 VDDIO = 1.8V 48 99 178 pd Internal Pull-Down Resistance VDDIO = 3.3V 26 43 79 kΩ VDDIO = 2.5V 34 59 113 VDDIO = 1.8V 53 99 200 100Base-TX Transmit (measured differentially after 1:1 transformer) VO Peak Differential Output Voltage 100Ω termination across differential output 0.95 1.05 V VIMB Output Voltage Imbalance 100Ω termination across differential output 2 % tr, tf Rise/Fall Time 3 5 ns Rise/Fall Time Imbalance 0 0.5 ns Duty Cycle Distortion ±0.25 ns Overshoot 5 % Output Jitter Peak-to-peak 0.7 ns 10Base-T Transmit (measured differentially after 1:1 transformer) VP Peak Differential Output Voltage 100Ω termination across differential output 2.2 2.8 V Jitter Added Peak-to-peak 3.5 ns tr, tf Rise/Fall Time 25 ns 10Base-T Receive VSQ Squelch Threshold 5MHz square wave 400 mV Transmitter – Drive Setting VSET Reference Voltage of ISET R(ISET) = 6.49kΩ 0.65 V REF_CLK Output 50MHz RMII Clock Output Jitter Peak-to-peak. (Applies only to KSZ8081RNB in RMII – 25MHz clock mode) 300 ps 100Mbps Mode – Industrial Applications Parameters Clock Phase Delay – XI Input to MII TXC Output XI (25MHz clock input) to MII TXC (25MHz clock output) delay, referenced to rising edges of both clocks. (Applies only to KSZ8081MNX in MII mode) 15 20 25 ns tllr Link Loss Reaction (Indication) Time Link loss detected at receive differential inputs to PHY signal indication time for each of the following: 1. For LED mode 00, Speed LED output changes from low (100Mbps) to high (10Mbps, default state for link-down). 2. For LED mode 01, Link LED output changes from low (link-up) to high (link-down). 3. INTRP pin asserts for link-down status change. 4.4 µs

Figure 11. MII SQE Timing (10Base-T) Table 13. MII SQE Timing (10Base-T) Parameters

Figure 12. MII Transmit Timing (10Base-T) Table 14. MII Transmit Timing (10Base-T) Parameters

Figure 13. MII Receive Timing (10Base-T) Table 15. MII Receive Timing (10Base-T) Parameters

Figure 14. MII Transmit Timing (100Base-TX) Table 16. MII Transmit Timing (100Base-TX) Parameters

Figure 15. MII Receive Timing (100Base-TX) Table 17. MII Receive Timing (100Base-TX) Parameters

Figure 18. Auto-Negotiation Fast Link Pulse (FLP) Timing Table 20. Auto-Negotiation Fast Link Pulse (FLP) Timing Parameters

Figure 19. MDC/MDIO Timing Table 21. MDC/MDIO Timing Parameters

The KSZ8081MNX/RNB reset timing requirement is summarized in Figure 20 and Table 22. Figure 20. Power-up/Reset Timing Table 22. Power-up/Reset Timing Parameters and updated at the de-assertion of reset. After the de-assertion of reset, wait a minimum of 100µs before starting programming on the MIIM (MDC/ MDIO) interface.

Table 25 lists recommended magnetic characteristics. Table 25. Magnetics Selection Criteria can be used with the KSZ8081MNX/RNB. Table 26. Compatible Single-Port 10/100 Magnetics

Micrel, Inc. KSZ8081MNX/KSZ8081RNB August 19, 2015 68 Revision 1.4 Package Information and Recommended Land Pattern(16) 32-Pin 5mm × 5mm QFN Note:

Micrel, Inc. KSZ8081MNX/KSZ8081RNB August 19, 2015 69 Revision 1.4 MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http://www.micrel.com Micrel, Inc. is a leading global manufacturer of IC solutions for the worldwide high performance linear and power, LAN, and timi ng & communications markets. The Company’s products include advanced mixed -signal, analog & power semiconductors; high- performance communication, clock management, MEMs-based clock oscillators & crystal -less clock generators, Ethernet switches, and physical layer transceiver ICs. Company customers include leading manufacturers of enterprise, consumer, industrial, mobile, telecommunic ations, automotive, and computer products. Corporation headquarters and state -of-the-art wafer fabrication facilities are located in San Jose, CA, with regional sales and support offices and advanced technology design centers situated throughout the Amer icas, Europe, and Asia. Additionally, the Company maintains an extensive network of distributors and reps worldwide. Micrel makes no representations or warranties with respect to the accuracy or completeness of the inf ormation furnished in this datasheet . This information is not intended as a warranty and Micrel does not assume responsibility for its use. Micrel reserves the right to change circuitry, specifications and descriptions at any time without notice. No license, whether express, implied, arisi ng by estoppel or otherwise, to any intellectual property rights is granted by this document. E xcept as provided in Micrel’s terms and conditions of sale for such products, Micrel assumes no liability whatsoever, and Micrel disclaims any express or implied warranty relating to the sale and/or use of Micrel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright, or other intellectual property right. Micrel Products a re not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a pro duct can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a signific ant injury to the user. A Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser’s own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. © 2013 Micrel, Incorporated.