KSZ8051MNLU

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Technical content

Features

• Single-Chip 10BASE-T/1 00BASE-TX IEEE 802.3 Compliant Ethernet Transceiver
• AEC-Q100 Qualified for Automotive Applications
• MII Interface Support (KSZ8051MNL)
• RMII v1.2 Interface Support with a 50 MHz Refer- ence Clock Output to MAC, and an Option to Input a 50 MHz Reference Clock (KSZ8051RNL)
• Back-to-Back Mode Support for a 100 Mbps Cop- per Repeater
• MDC/MDIO Management Interface for PHY Reg- ister Configuration
• Programmable Interrupt Output
• LED Outputs for Link, Activity, and Speed Status Indication
• On-Chip Termination Resistors for the Differential Pairs
• Baseline Wander Correction
• HP Auto MDI/MDI-X to Reliably Detect and Cor- rect Straight-Through and Crossover Cable Con- nections with Disable and Enable Option
• Auto-Negotiation to Automatically Select the Highest Link-Up Speed (10/100 Mbps) and Duplex (Half/Full)
• Power-Down and Power-Saving Modes
• LinkMD ® TDR-Based Cable Diagnostics to Iden- tify Faulty Copper Cabling
• Parametric NAND Tree Support for Fault Detec- tion Between Chip I/Os and the Board
• Loopback Modes for Diagnostics
• Single 3.3V Power Supply with V DD I/O Options for 1.8V, 2.5V, or 3.3V
• Built-In 1.2V Regulator for Core
• Available in 32-pin 5 mm x 5 mm QFN Package Target Applications
• Automotive In-Vehicle Networking KSZ8051MNL/RNL 10BASE-T/100BASE-TX Automotive Physical Layer Transceiver

DS00002310A-page 2  2016 Microchip Technology Inc. TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for cur- rent devices. As device/doc umentation issues become known to us, we will publish an errata s heet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following:

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 2016 Microchip Technology Inc. DS00002310A-page 3 KSZ8051MNL/RNL Table of Contents

DS00002310A-page 4  2016 Microchip Technology Inc.

1.0 INTRODUCTION

1.1 General Description

The KSZ8051 is an AEC-Q100 standard qualified single-supply 10BASE-T/100BASE-TX Ethernet physical-layer trans- ceiver. The KSZ8051 is a highly integrated PHY solution. It reduce s board cost and simplifies board layout by using on-chip termination resistors for the differential pairs and by integrating a low-noise regulator to supply the 1.2V core. The KSZ8051MNL offers the Media Independent Interface (MII) and the KSZ8051RNL offers the Reduced Media Inde- pendent Interface (RMII) for direct connection with MII-/RMII-compliant Ethernet MAC processors and switches. A 25 MHz crystal is used to generate all required clocks, including the 50 MHz RMII reference clock output for the KSZ8051RNL. The KSZ8051 provides diagnostic features to facilitate system bring-up and debugging in production testing and in prod- uct deployment. Parametric NAND tree support enables fault detection between KSZ8051 I/Os and the board. Microchip LinkMD® TDR-based cable diagnostics identify faulty copper cabling. The KSZ8051MNL and KSZ8051RNL are available in 32-pin, lead-free QFN packages. FIGURE 1-1: SYSTEM BLOCK DIAGRAM KSZ8051MNL/ KSZ8051RNL MAGNETICS RJ-45 CONNECTOR MEDIA TYPES: 10BASE-T 100BASE-TX ON-CHIP TERMINATION RESISTORS MII/RMII MDC/ MDIO MANAGEMENT XO XI 25MHz XTAL 22pF 22pF 10/100Mbps MII/RMII MAC 50MHz (KSZ8051RNLU) REF_CLK

 2016 Microchip Technology Inc. DS00002310A-page 5 KSZ8051MNL/RNL

2.0 PIN DESCRIPTION AND CONFIGURATION

FIGURE 2-1: 32-PIN 5 MM X 5 MM QFN ASSIGNMENT, KSZ8051MNL (TOP VIEW) TABLE 2-1: SIGNALS - KSZ8051MNL Pin Number Pin Name Type Note 2-1

Description

1 GND GND Ground. 2 VDD_1.2 P 1.2V core VDD (power supplied by KSZ8051MNL) Decouple with 2.2 µF and 0.1 µF capacitors to ground. 3 VDDA_3.3 P 3.3V analog VDD 4R X M I / O Physical receive or transmit signal (– differential) 5R X P I / O Physical receive or transmit signal (+ differential) 6T X M I / O Physical transmit or receive signal (– differential) GND VDD_1.2 VDDA_3.3 RXM RXP TXM TXP XO RXD3/PHYAD0 MDC MDIO REXT XI RXD2/PHYAD1 RXD1/PHYAD2 RXD0/DUPLEX 91 01 1 1 2 1 3 1 4 15 16 32 31 30 29 28 27 26 25 TXD0 TXEN TXC INTRP/NAND_Tree# RXER/ISO RXC/B-CAST_OFF RXDV/CONFIG2 VDDIO COL/CONFIG0 CRS/CONFIG1 LED0/NWAYEN LED1/SPEED RST# TXD3 TXD2 TXD1 Paddle Ground (on bottom of chip)

DS00002310A-page 6  2016 Microchip Technology Inc. 7T X P I / O Physical transmit or receive signal (+ differential) 8X O O Crystal feedback for 25 MHz crystal This pin is a no connect if an oscillator or external clock source is used. 9X I I Crystal/Oscillator/External Clock input

25 MHz ±50 ppm

10 REXT I Set PHY transmit output current

Connect a 6.49 kΩ resistor to ground on this pin.

11 MDIO Ipu/

Management Interface (MII) Data I/O This pin has a weak pull-up, is open-drain, and requires an external 1.0 kΩ pull-up resistor.

12 MDC Ipu Management Interface (MII) Clock input

This clock pin is synchronous to the MDIO data pin.

13 RXD3/

MII mode: MII Receive Data Output[3] (Note 2-2) Config mode: The pull-up/pull-down value is latched as PHYADDR[0] at the de assertion of reset. See the Strap-In Options - KSZ8051MNL section for details.

14 RXD2/

MII mode: MII Receive Data Output[2] (Note 2-2) Config mode: The pull-up/pull-down value is latched as PHYADDR[1] at the deassertion of reset. See the Strap-In Options - KSZ8051MNL section for details.

15 RXD1/

MII mode: MII Receive Data Output[1] (Note 2-2) Config mode: The pull-up/pull-down value is latched as PHYADDR[2] at the de assertion of reset. See the Strap-In Options - KSZ8051MNL section for details.

16 RXD0/

MII mode: MII Receive Data Output[0] (Note 2-2) Config mode: The pull-up/pull-down value is latched as DUPLEX at the de- assertion of reset. See the Strap-In Options - KSZ8051MNL section for details. 17 VDDIO P 3.3V, 2.5V, or 1.8V digital V DD

18 RXDV/

MII mode: MII Receive Data Valid output Config mode: The pull-up/pull-down value is latched as CONFIG2 at the de- assertion of reset. See the Strap-In Options - KSZ8051MNL section for details.

19 RXC/

B-CAST_OFF Ipd/O MII mode: MII Receive Clock output Config mode: The pull-up/pull-down value is latched as B-CAST_OFF at the de assertion of reset. See the Strap-In Options - KSZ8051MNL section for details.

20 RXER/ISO Ipd/O

MII mode: MII Receive Error output Config mode: The pull-up/pull-down value is latched as ISOLATE at the de- assertion of reset. See the Strap-In Options - KSZ8051MNL section for details. TABLE 2-1: SIGNALS - KSZ8051MNL (CONTINUED) Pin Number Pin Name Type Note 2-1

 2016 Microchip Technology Inc. DS00002310A-page 7 KSZ8051MNL/RNL

21 INTRP/

NAND_Tree# Ipu/ Opu Interrupt output: Programmable interrupt output This pin has a weak pull-up, is open-drain, and requires an external 1.0 kΩ pull-up resistor. Config mode: The pull-up/pull-down value is latched as NAND Tree# at the de-assertion of reset. See the Strap-In Options - KSZ8051MNL section for details.

22 TXC I/O MII mode: MII Transmit Clock output

MII back-to-back mode: MII Transmit Clock input

23 TXEN I MII mode: MII Transmit Enable input

24 TXD0 I MII mode: MII Transmit Data Input[0] ( Note 2-3)

25 TXD1 I MII mode: MII Transmit Data Input[1] ( Note 2-3)

26 TXD2 I MII mode: MII Transmit Data Input[2] ( Note 2-3)

27 TXD3 I MII Mode: MII Transmit Data Input[3] ( Note 2-3)

28 COL/

MII mode: MII Collision Detect output Config mode: The pull-up/pull-down value is latched as CONFIG0 at the de- assertion of reset. See the Strap-In Options - KSZ8051MNL section for details.

29 CRS/

MII mode: MII Carrier Sense output Config mode: The pull-up/pull-down value is latched as CONFIG1 at the de- assertion of reset. See the Strap-In Options - KSZ8051MNL section for details.

30 LED0/

LED output: Programmable LED0 output Config mode: Latched as auto-negotiation enable (Register 0h, bit [12]) at the de-assertion of reset. See the Strap-In Options - KSZ8051MNL section for details. The LED0 pin is programmable using Register 1Fh bits [5:4], and is defined as follows. LED Mode = [00] Link/Activity Pin State LED Definition No Link High OFF Link Low ON Activity Toggle Blinking LED Mode = [01] Link Pin State LED Definition No Link High OFF Link Low ON LED Mode = [10], [11]: Reserved TABLE 2-1: SIGNALS - KSZ8051MNL (CONTINUED) Pin Number Pin Name Type Note 2-1

DS00002310A-page 8  2016 Microchip Technology Inc. Note 2-1 P = power supply GND = ground I = input O = output I/O = bi-directional Ipu = Input with internal pull-up (see Electrical Characteristics for value). Ipu/O = Input with in ternal pull-up (see Electrical Characteristics for value) duri ng power-up/reset; output pin otherwise. Ipd/O = Input with internal pull-down (see Electrical Characteristics for value) during power-up/reset; output pin otherwise. Ipu/Opu = Input with internal pull-up (see Electrical Characteristics for value) and output with internal pull-up (see Electrical Characteristics for value). Note 2-2 MII RX Mode: The RXD[3: 0] bits are synchronous with RXC. When RXDV is asserted, RXD[3:0] presents valid data to the MAC. Note 2-3 MII TX Mode: The TXD[3:0] bits are synchronous with TXC. When TXEN is asserted, TXD[3:0] presents valid data from the MAC.

31 LED1/SPEED Ipu/O

LED output: Programmable LED1 output Config mode: Latched as Speed (register 0h, bit [13]) at the de-assertion of reset. See the Strap-In Options - KSZ8051MNL section for details. The LED1 pin is programmable using register 1Fh bits [5:4], and is defined as follows. LED mode = [00] Speed Pin State LED Definition 10BASE-T High OFF 100BASE-TX Low ON LED mode = [01] Activity Pin State LED Definition No activity High OFF Activity Toggle Blinking LED mode = [10], [11]: Reserved

32 RST# Ipu Chip reset (active low)

TABLE 2-1: SIGNALS - KSZ8051MNL (CONTINUED) Pin Number Pin Name Type Note 2-1

 2016 Microchip Technology Inc. DS00002310A-page 9 KSZ8051MNL/RNL The strap-in pins are latched at the de-assertion of reset. In some systems, the MAC MII receive input pins may drive high/low during power-up or reset, and consequently caus e the PHY strap-in pins on t he MII signals to be latched to unintended high/low states. In this case, external pull-ups (4.7 k Ω) or pull-downs (1.0 k Ω) should be added on these PHY strap-in pins to ensure that the intended values are strapped-in correctly. Note 2-4 Ipu/O = Input with internal pull-up duri ng power-up/reset; output pin otherwise. Ipd/O = Input with internal pull-down du ring power-up/reset; output pin otherwise. Ipu/Opu = Input with internal pull- up and output with internal pull-up. TABLE 2-2: STRAP-IN OPTIONS - KSZ8051MNL Pin Number Pin Name Type Note 2-4 Description

15 PHYAD2 Ipd/O PHYAD[2:0] is latched at de-a ssertion of reset and is configurable to

any value from 0 to 7 with PHY Address 1 as the default value. PHY Address 0 is assigned by default as the broadcast PHY address, but it can be assigned as a unique PHY address after pull- ing the B-CAST_OFF strapping pin high or writing a ‘1’ to Register 16h, bit [9]. PHY Address bits [4:3] are set to 00 by default.

14 PHYAD1 Ipd/O

13 PHYAD0 Ipu/O

18 CONFIG2

The CONFIG[2:0] strap-in pins are latched at the de-assertion of reset.

29 CONFIG1 CONFIG[2:0] Mode

000 MII (default)

28 CONFIG0

110 MII back-to-back

001 – 101,

111 Reserved, not used

20 ISO Ipd/O

Pull-up = Enable Pull-down (default) = Disable At the de-assertion of reset, this pin value is latched into Register 0h, bit [10].

31 SPEED Ipu/O

Pull-up (default) = 100 Mbps Pull-down = 10 Mbps At the de-assertion of reset, this pin value is latched into register 0h, bit [13] as the speed select, and also is latched into register 4h (auto- negotiation advertisement) as the speed capability support.

16 DUPLEX Ipu/O

Duplex Mode: Pull-up (default) = Half-duplex Pull-down = Full-duplex At the de-assertion of reset, this pin value is latched into Register 0h, Bit [8].

30 NWAYEN Ipu/O

Nway Auto-Negotiation Enable: Pull-up (default) = Enable auto-negotiation Pull-down = Disable auto-negotiation At the de-assertion of reset, this pin value is latched into Register 0h, Bit [12].

19 B-CAST_OFF Ipd/O

Broadcast Off – for PHY Address 0: Pull-up = PHY Address 0 is set as an unique PHY address Pull-down (default) = PHY Address 0 is set as a broadcast PHY address At the de-assertion of reset, this pin value is latched by the chip.

21 NAND_Tree# Ipu/Opu

NAND Tree Mode: Pull-up (default) = Disable Pull-down = Enable At the de-assertion of reset, this pin value is latched by the chip.

DS00002310A-page 10  2016 Microchip Technology Inc. FIGURE 2-2: 32-PIN 5 MM X 5 MM QFN ASSIGNMENT, KSZ8051RNL (TOP VIEW) TABLE 2-3: SIGNALS - KSZ8051RNL Pin Number Pin Name Type Note 2-1 Description 1 GND GND Ground. 2 VDD_1.2 P 1.2V core VDD (power supplied by KSZ8091RNB) Decouple with 2.2 µF and 0.1 µF capacitors to ground. 3 VDDA_3.3 P 3.3V analog V DD

4 RXM I/O Physical receive or transmit signal (– differential)

5 RXP I/O Physical receive or transmit signal (+ differential)

6 TXM I/O Physical transmit or receive signal (– differential)

7 TXP I/O Physical transmit or receive signal (+ differential)

8X O O Crystal feedback for 25 MHz crystal This pin is a no connect if an oscillator or external clock source is used. 9X II 25 MHz Mode: 25 MHz ±50 ppm Crystal/Oscillator/External Clock Input

50 MHz Mode: 50 MHz ±50 ppm Oscillator/External Clock Input

Connect a 6.49 kΩ resistor to ground on this pin. GND VDD_1.2 VDDA_3.3 RXM RXP TXM TXP XO PHYAD0 MDC MDIO REXT XI PHYAD1 RXD1/PHYAD2 RXD0/DUPLEX 91 01 1 1 2 1 3 1 4 15 16 32 31 30 29 28 27 26 25 TXD0 TXEN NC INTRP/NAND_Tree# RXER/ISO REF_CLK/B-CAST_OFF CRS_DV/CONFIG2 VDDIO CONFIG0 CONFIG1 LED0/NWAYEN LED1/SPEED RST# NC NC TXD1 Paddle Ground (on bottom of chip)

 2016 Microchip Technology Inc. DS00002310A-page 11 KSZ8051MNL/RNL

11 MDIO Ipu/Opu

Management Interface (MII) Data I/O This pin has a weak pull-up, is open-drain, and requires an external 1.0 kΩ pull-up resistor. This clock pin is synchronous to the MDIO data pin. The pull-up/pull-down value is latched as PHYADDR[0] at the de-assertion of reset. See the Strap-In Options - KSZ8051RNL section for details. The pull-up/pull-down value is latched as PHYADDR[1] at the de-assertion of reset. See the Strap-In Options - KSZ8051RNL section for details. RMII mode: RMII Receive Data Output[1] (Note 2-2) Config mode: The pull-up/pull-down value is latched as PHYADDR[2] at the de-assertion of reset. See the Strap-In Options - KSZ8051RNL section for details. RMII mode: RMII Receive Data Output[0] (Note 2-2) Config mode: The pull-up/pull-down value is latched as DUPLEX at the de- assertion of reset. See the Strap-In Options - KSZ8051RNL section for details. 17 VDDIO P 3.3V, 2.5V, or 1.8V digital V DD

18 CRS_DV/

RMII mode: RMII Carrier Sense/Receive Data Valid output Config mode: The pull-up/pull-down value is latched as CONFIG2 at the de- assertion of reset. See the Strap-In Options - KSZ8051RNL section for details.

19 REF_CLK/

B-CAST_OFF Ipd/O RMII mode: 25 MHz mode: This pin provides the 50 MHz RMII reference clock output to the MAC. See also XI (pin 9). 50 MHz mode: This pin is a no connect. See also XI (pin 9). Config mode: The pull-up/pull-down value is latched as B-CAST_OFF at the de-assertion of reset. See the Strap-In Options - KSZ8051RNL section for details. RMII mode: RMII Receive Error output Config mode: The pull-up/pull-down value is latched as ISOLATE at the de- assertion of reset. See the Strap-In Options - KSZ8051RNL section for details. NAND_Tree# Ipu/Opu Interrupt output: Programmable interrupt output This pin has a weak pull-up, is open-drain, and requires an external 1.0 kΩ pull-up resistor. Config mode: The pull-up/pull-down value is latched as NAND Tree# at the de-assertion of reset. See the Strap-In Options - KSZ8051RNL section for details. 22 NC — No connect – This pin is not bonded and can be left floating.

23 TXEN I RMII Transmit Enable input

24 TXD0 I RMII Transmit Data Input[0] ( Note 2-3)

25 TXD1 I RMII Transmit Data Input[1] ( Note 2-3)

26 NC NC No connect – This pin is not bonded and can be left floating. 27 NC NC No connect – This pin is not bonded and can be left floating.

28 CONFIG0 Ipd/O

The pull-up/pull-down value is latched as CONFIG0 at the de-assertion of reset. See the Strap-In Options - KSZ8051RNL section for details. TABLE 2-3: SIGNALS - KSZ8051RNL (CONTINUED) Pin Number Pin Name Type Note 2-1 Description

DS00002310A-page 12  2016 Microchip Technology Inc. Note 2-1 P = Power supply. GND = Ground. I = Input. O = Output. I/O = Bi-directional. Ipu = Input with internal pull-up (see Electrical Characteristics for value). Ipu/O = Input with in ternal pull-up (see Electrical Characteristics for value) duri ng power-up/reset; output pin otherwise. Ipd/O = Input with internal pull-down (see Electrical Characteristics for value) during power-up/reset; output pin otherwise. Ipu/Opu = Input with internal pull-up (see Electrical Characteristics for value) and output with internal pull-up (see Electrical Characteristics for value). NC = Pin is not bonded to the die.

29 CONFIG1 Ipd/O

The pull-up/pull-down value is latched as CONFIG1 at the de-assertion of reset. See the Strap-In Options - KSZ8051RNL section for details. LED output: Programmable LED0 output Config mode: Latched as auto-negotiation enable (Register 0h, bit [12]) at the de-assertion of reset. See the Strap-In Options - KSZ8051RNL section for details. The LED0 pin is programmable using Register 1Fh bits [5:4], and is defined as follows. LED Mode = [00] Link/Activity Pin State LED Definition No Link High OFF Link Low ON Activity Toggle Blinking LED Mode = [01] Link Pin State LED Definition No Link High OFF Link Low ON LED Mode = [10], [11]: Reserved

31 LED1/

LED output: Programmable LED1 output Config mode: Latched as SPEED (Register 0h, bit [13]) at the de-assertion of reset. See the Strap-In Options - KSZ8051RNL section for details. The LED1 pin is programmable using Register 1Fh bits [5:4], and is defined as follows. LED Mode = [00] Speed Pin State LED Definition 10BASE-T High OFF 100BASE-TX Low ON LED Mode = [01] Activity Pin State LED Definition No Activity High OFF Activity Toggle Blinking LED Mode = [10], [11]: Reserved TABLE 2-3: SIGNALS - KSZ8051RNL (CONTINUED) Pin Number Pin Name Type Note 2-1 Description

 2016 Microchip Technology Inc. DS00002310A-page 13 KSZ8051MNL/RNL Note 2-2 RMII RX Mode: The RXD[1:0] bits are synchronous with the 50 MHz RMII Reference Clock. For each clock period in which CRS_DV is asserted, two bits of recovered data are sent by the PHY to the MAC. Note 2-3 RMII TX Mode: The TXD[ 1:0] bits are synchronous with the 50 MHz RMII Reference Clock. For each clock period in which TXEN is asserted, two bits of data are received by the PHY from the MAC. The strap-in pins are latched at the de-assertion of reset. In some systems, the MAC RMII receive input pins may drive high/low during power-up or reset, and consequently cause the PHY strap-in pins on the RMII signals to be latched to unintended high/low states. In this case, external pull-ups (4.7 k Ω) or pull-downs (1.0 k Ω) should be added on these PHY strap-in pins to ensure that the intended values are strapped-in correctly. TABLE 2-4: STRAP-IN OPTIONS - KSZ8051RNL Pin Number Pin Name Type Note 2-4 Description any value from 0 to 7 with PHY Address 1 as the default value. PHY Address 0 is assigned by default as the broadcast PHY address, but it can be assigned as a unique PHY address after pull- ing the B-CAST_OFF strapping pin high or writing a ‘1’ to Register 16h, bit [9]. PHY Address bits [4:3] are set to 00 by default. The CONFIG[2:0] strap-in pins are latched at the de-assertion of reset.

000 RMII (default)

110 RMII back-to-back

001 – 101, Pull-up = Enable Pull-down (default) = Disable At the de-assertion of reset, this pin value is latched into Register 0h, bit [10]. Pull-up (default) = 100 Mbps Pull-down = 10 Mbps At the de-assertion of reset, this pin value is latched into Register 0h, bit [13] as the speed select, and also is latched into Register 4h (auto-negotiation advertisement) as the speed capability support. Duplex Mode: Pull-up (default) = Half-duplex Pull-down = Full-duplex At the de-assertion of reset, this pin value is latched into Register 0h, Bit [8]. Nway Auto-Negotiation Enable: Pull-up (default) = Enable auto-negotiation Pull-down = Disable auto-negotiation At the de-assertion of reset, this pin value is latched into Register 0h, Bit [12]. Broadcast Off – for PHY Address 0: Pull-up = PHY Address 0 is set as an unique PHY address Pull-down (default) = PHY Address 0 is set as a broadcast PHY address At the de-assertion of reset, this pin value is latched by the chip.

DS00002310A-page 14  2016 Microchip Technology Inc. Note 2-4 Ipu/O = Input with internal pull-up duri ng power-up/reset; output pin otherwise. Ipd/O = Input with internal pull-down du ring power-up/reset; output pin otherwise. Ipu/Opu = Input with internal pull- up and output with internal pull-up. NAND Tree Mode: Pull-up (default) = Disable Pull-down = Enable At the de-assertion of reset, this pin value is latched by the chip. TABLE 2-4: STRAP-IN OPTIONS - KSZ8051RNL (CONTINUED) Pin Number Pin Name Type Note 2-4 Description

 2016 Microchip Technology Inc. DS00002310A-page 15 KSZ8051MNL/RNL

3.0 FUNCTIONAL DESCRIPTION

The KSZ8051 is an in tegrated single 3.3V supply Fast Ethernet transceiver. It is fully compliant with the IEEE 802.3 Specification, and reduces board cost and simplifies board layout by using on-chip termination resistors for the two dif- ferential pairs and by integrating the regulator to supply the 1.2V core. On the copper media side, the KSZ8051 supports 10Base-T and 100Base-TX fo r transmission and reception of data over a standard CAT-5 unshielded twisted pair (UTP) cable, and HP Auto MDI/MDI-X for reliable detection of and cor- rection for straight-through and crossover cables. On the MAC processor side, the KSZ8051MNL offers the Media Independent Interface (MII) and the KSZ8051RNL offers the Reduced Media Independent Interface (RMII) for direct connection with MII and RMII compliant Ethernet MAC processors and switches, respectively. The MII management bus option gives the MAC processor comp lete access to the KSZ8051 control and status regis- ters. Additionally, an interrupt pin eliminates the need for the processor to poll for PHY status change. KSZ8051MNL/RNL is used in this data sheet to refer to both the KSZ8051MNL and the KSZ8051RNL devices. 3.1 10BASE-T/100BASE-TX Transceiver 3.1.1 100BASE-TX TRANSMIT The 100Base-TX transmit function perfo rms parallel-to-serial conversion, 4B /5B encoding, scrambling, NRZ-to-NRZI conversion, and MLT3 encoding and transmission. The circuitry starts with a parallel-to-serial conversion, which converts the MII data from the MAC into a 125 MHz serial bit stream. The data and control stream is then converted into 4B/5B coding and followed by a scrambler. The serialized data is further converted from NRZ-to-NRZI format, and then transmitted in MLT3 current output. The output current is set by an external 6.49 kΩ 1% resistor for the 1:1 transformer ratio. The output signal has a typical rise/fall time of 4ns and complies with the ANSI TP-PMD standard regarding amplitude balance, overshoot, and timing jitter. The wave-shaped 10Base-T output is also incorporated into the 100Base-TX trans- mitter. 3.1.2 100BASE-TX RECEIVE The 100Base-TX receiver function performs adaptive equalization, DC restoration, MLT3-to-NRZI conversion, data and clock recovery, NRZI-to-NRZ conversion, de-scrambling, 4B/5B decoding, and serial-to-parallel conversion. The receiving side starts with the equalization filter to com pensate for inter-symbol interference (ISI) over the twisted pair cable. Because the amplitude loss and phase distortion is a function of the cable length, the equalizer must adjust its characteristics to optimize performance. In this design, the variable equaliz er makes an initial estimation based on comparisons of incoming signal strength against some known cable characteristics, then tunes itself for optimization. This is an ongoing process and self-adjusts against environmental changes such as temperature variations. Next, the equalized signal goes through a DC-restoration and data-conversion block. The DC-restoration circuit com- pensates for the effect of baseline wander and improves the dynamic range. The differential data-conversion circuit con- verts MLT3 format back to NRZI. The slicing threshold is also adaptive. The clock-recovery circuit extracts the 125 MHz clock from the edges of the NRZI signal. This recovered clock is then used to convert the NRZI signal to NRZ format. This signal is sent through the de-scrambler, then the 4B/5B decoder. Finally, the NRZ serial data is converted to MII format and provided as the input data to the MAC.

3.1.3 SCRAMBLER/DE-SCRAMBLER (100BASE-TX ONLY)

The scrambler spreads the power spectrum of the transmitted signal to reduce electromagnetic interference (EMI) and baseline wander. The de-scrambler recovers the scrambled signal. 3.1.4 10BASE-T TRANSMIT The 10Base-T drivers are incorporated with the 100Base-TX drivers to allow for transmission using the same magnetic. The drivers perform internal wave-shaping and pre-emphasis, and output 10Base-T signals with a typical amplitude of 2.5V peak. The 10Base-T signals have harmonic contents that are at least 27 dB below the fundamental frequency when driven by an all-ones Manchester-encoded signal.

DS00002310A-page 16  2016 Microchip Technology Inc. 3.1.5 10BASE-T RECEIVE On the receive side, input buffer and level detecting squelch circuits are used. A differential input receiver circuit and a phase-locked loop (PLL) performs the decoding function. The Manchester-encoded data stream is separated into clock signal and NRZ data. A squelch circuit rejects signals with levels less than 400 mV, or with short pulse widths, to prevent noise at the RXP and RXM inputs from falsely triggering the decoder. When the input exceeds the squelch limit, the PLL locks onto the incoming signal and the KSZ8051MNL/RNL decodes a data frame. The receive clock is kept active during idle periods between data receptions.

3.1.6 SQE AND JABBER FUNCTION (10BASE-T ONLY)

In 10Base-T operation, a short pulse is put out on the COL pin after each frame is transmitted. This SQE test is needed to test the 10Base-T transmit/receive pa th. If transmit enable (TXEN) is high for more than 20 ms (jabbering), the 10Base-T transmitter is disabled and COL is asserted high . If TXEN is then driven low for more than 250 ms, the 10Base-T transmitter is re-enabled and COL is de-asserted (returns to low).

3.1.7 PLL CLOCK SYNTHESIZER

The KSZ8051MNL/RNL generates all internal clocks and all external clocks for system timing from an external 25 MHz crystal, oscillator, or reference clock. For the KSZ8051 RNL in RMII 50 MHz clock mode, these clocks are generated from an external 50 MHz oscillator or system clock.

3.1.8 AUTO-NEGOTIATION

The KSZ8051MNL/RNL conforms to the auto-negotiation protocol, defined in Clause 28 of the IEEE 802.3 specification. Auto-negotiation allows unshielded twisted pair (UTP) link partners to select the highest common mode of operation. During auto-negotiation, link partners advertise capabilities across the UTP link to each other and then compare their own capabilities with those they received from their link partners. The highest speed and duplex setting that is common to the two link partners is selected as the mode of operation. The following list shows the speed and duplex operation mode from highest to lowest priority.

• Priority 1: 100BASE-TX, full-duplex
• Priority 2: 100BASE-TX, half-duplex
• Priority 3: 10BASE-T, full-duplex
• Priority 4: 10BASE-T, half-duplex If auto-negotiation is not supported or the KSZ8051MNL/RNL link partner is forced to bypass auto-negotiation, then the KSZ8051MNL/RNL sets its operating mode by observing the signal at its receiver. This is known as parallel detection, which allows the KSZ8051MNL/RNL to establish a link by listening for a fixed signal protocol in the absence of the auto- negotiation advertisement protocol. Auto-negotiation is enabled by either hardware pin strapping (NWAYEN, pin 30) or software (register 0h, bit [12]). By default, auto-negotiation is enabled after power-up or hardware reset. After that, auto-negotiation can be enabled or disabled by register 0h, bit [12]. If auto-negotiation is disabled, the speed is set by register 0h, bit [13], and the duplex is set by register 0h, bit [8]. The auto-negotiation link-up process is shown in Figure 3-1.

 2016 Microchip Technology Inc. DS00002310A-page 17 KSZ8051MNL/RNL FIGURE 3-1: AUTO-NE GOTIATION FLOW CHART

3.2 MII Data Interface (KSZ8051MNL Only)

The Media Independent Interface (MII) is compliant with the IEEE 802.3 Specification. It provides a common interface between MII PHYs and MACs, and has the following key characteristics:

• Pin count is 15 pins (6 pins for data transmission, 7 pins for data reception, and 2 pins for carrier and collision indi- cation).
• 10 Mbps and 100 Mbps data rates are supported at both half- and full-duplex.
• Data transmission and reception are independent and belong to separate signal groups.
• Transmit data and receive data are each 4 bits wide, a nibble. By default, the KSZ8051MNL is configured to MII mode after it is powered up or hardware reset with the following:
• A 25 MHz crystal connected to XI, XO (pins 9, 8), or an external 25 MHz clock source (oscillator) connected to XI.
• The CONFIG[2:0] strapping pins (pins 18, 29, 28) set to 000 (default setting). START AUTO-NEGOTIATION FORCE LINK SETTING LISTEN FOR 10BASE-T LINK PULSES LISTEN FOR 100BASE-TX IDLES ATTEMPT AUTO- NEGOTIATION LINK MODE SET BYPASS AUTO-NEGOTIATION AND SET LINK MODE LINK MODE SET? PARALLEL OPERATIONNO YES YES NO JOIN FLOW

DS00002310A-page 18  2016 Microchip Technology Inc.

3.2.1 MII SIGNAL DEFINITION

Table 3-1 describes the MII signals. Refer to Clause 22 of the IEEE 802.3 Specification for detailed information.

3.2.1.1 Transmit Clock (TXC)

TXC is sourced by the PHY. It is a continuous clock that provides the timing reference for TXEN, TXD[3:0], and TXER. TXC is 2.5 MHz for 10 Mbps operation and 25 MHz for 100 Mbps operation.

3.2.1.2 Transmit Enable (TXEN)

TXEN indicates that the MAC is presenting nibbles on TXD[3:0] for transmission. It is asserted synchronously with the first nibble of the preamble and remains asserted while all nibbles to be transmitted are presented on the MII. It is negated before the first TXC following the final nibble of a frame. TXEN transitions synchronously with respect to TXC.

3.2.1.3 Transmit Data[3:0] (TXD[3:0])

TXD[3:0] transitions synchronously with respect to TXC. When TXEN is as serted, TXD[3:0] are accepted by the PHY for transmission. TXD[3:0] is 00 to indicate idle when TXEN is de-asserted. Values other than 00 on TXD[3:0] while TXEN is de-asserted are ignored by the PHY.

3.2.1.4 Receive Clock (RXC)

RXC provides the timing reference for RXDV, RXD[3:0], and RXER. In 10 Mbps mode, RXC is recovered from the line while the carri er is active. When the line is idle or the link is down, RXC is derived from the PHY’s reference clock. In 100 Mbps mode, RXC is continuously recovered from the line. If the link is down, RX C is derived from the PHY’s reference clock. RXC is 2.5 MHz for 10 Mbps operation and 25 MHz for 100 Mbps operation.

3.2.1.5 Receive Data Valid (RXDV)

RXDV is driven by the PHY to indicate that the PHY is presenting recovered and decoded nibbles on RXD[3:0]. In 10 Mbps mode, RXDV is asserted with the first nibble of the start-of-frame delimiter (SFD), 5D, and remains asserted until the end of the frame. In 100 Mbps mode, RXDV is asserted from the first nibble of the preamble to the last nibble of the frame. RXDV transitions synchronously with respect to RXC. TABLE 3-1: MII SIGNAL DEFINITION MII Signal Name Direction with Respect to PHY, KSZ8051MNL Signal Direction with Respect to MAC Description TXC Output Input Transmit Clock (2.5 MHz for 10 Mbps; 25 MHz for 100 Mbps) TXEN Input Output Transmit Enable TXD[3:0] Input Output Transmit Data[3:0] RXC Output Input Receive Clock (2.5 MHz for 10 Mbps; 25 MHz for 100 Mbps) RXDV Output Input Receive Data Valid RXD[3:0] Output Input Receive Data[3:0] RXER Output Input or not required Receive Error CRS Output Input Carrier Sense COL Output Input Collision Detection

 2016 Microchip Technology Inc. DS00002310A-page 19 KSZ8051MNL/RNL

3.2.1.6 Receive Data[3:0] (RXD[3:0])

RXD[3:0] transitions synchronously with respect to RXC. For each clock period in which RXDV is asserted, RXD[3:0] transfers a nibble of recovered data from the PHY.

3.2.1.7 Receive Error (RXER)

RXER is asserted for one or more RXC periods to indicate that a symbol error (for example, a coding error that a PHY can detect that may otherwise be undetectable by the MAC sub-layer) was detected somewhere in the frame being transferred from the PHY . RXER transitions synchronously with respect to RXC. While RXDV is de-asserted, RXER has no effect on the MAC.

3.2.1.8 Carrier Sense (CRS)

CRS is asserted and de-asserted as follows:

• In 10 Mbps mode, CRS assertion is based on the reception of valid preambles. CRS de-assertion is based on the reception of an end-of-frame (EOF) marker.
• In 100 Mbps mode, CRS is asserted when a start-of-stream delimiter or /J/K symbol pair is detected. CRS is de- asserted when an end-of-stream delimiter or /T/R symbol pair is detected. Additionally, the PMA layer de-asserts CRS if IDLE symbols are received without /T/R.

3.2.1.9 Collision Detection (COL)

COL is asserted in half-duplex mode whenever the transmitter and receiver are simultaneously active on the line. This informs the MAC that a collision has occurred during its transmission to the PHY. COL transitions asynchronously with respect to TXC and RXC.

3.2.2 MII SIGNAL DIAGRAM

The KSZ8051MNL MII pin connections to the MAC are shown in Figure 3-2. FIGURE 3-2: KSZ8051MNL MII INTERFACE KSZ8051MNL MII Ethernet MAC TXC TXEN TXD[3:0] RXC RXDV RXD[3:0] RXER CRS COL TXC TXEN TXD[3:0] RXC RXDV RXD[3:0] RXER CRS COL

DS00002310A-page 20  2016 Microchip Technology Inc.

3.3 RMII Data Interface (KSZ8051RNL Only)

The Reduced Media Independent Interface (RMII) specifies a low pin count Media Independent Interface (MII). It pro- vides a common interface between physical layer and MAC layer devices, and has the following key characteristics:

• Pin count is 8 pins (3 pins for data transmission, 4 pins for data reception, and 1 pin for the 50 MHz reference clock).
• 10 Mbps and 100 Mbps data rates are supported at both half- and full-duplex.
• Data transmission and reception are independent and belong to separate signal groups.
• Transmit data and receive data are each 2 bits wide, a dibit.

3.3.1 RMII - 25 MHZ CLOCK MODE

The KSZ8051RNL is configured to RMII - 25 MHz clock mode after it is powered up or hardware reset with the following:

• A 25 MHz crystal connected to XI, XO (pins 9, 8), or an external 25 MHz clock source (oscillator) connected to XI.
• The CONFIG[2:0] strap-in pins (pins 18, 29, 28) set to 001.
• Register 1Fh, bit [7] is set to 0 (defau lt value) to select 25 MHz clock mode.

3.3.2 RMII - 50 MHZ CLOCK MODE

The KSZ8051RNL is configured to RMII - 50 MHz clock mode after it is powered up or hardware reset with the following:

• An external 50 MHz clock source (oscillator) connected to XI (pin 9).
• The CONFIG[2:0] strap-in pins (pins 18, 29, 28) set to 001.
• Register 1Fh, bit [7] is set to 1 to select 50 MHz clock mode.

3.3.3 RMII SIGNAL DEFINITION

Table 3-2 describes the RMII signals. Refer to RMII Specification v1.2 for detailed information.

3.3.4 REFERENCE CLOCK (REF_CLK)

REF_CLK is a continuous 50 MHz clock that provides the timing reference for TXEN, TXD[1:0], CRS_DV, RXD[1:0] and RX_ER. For 25 MHz clock mode, the KSZ8051RNL generates and outputs the 50 MHz RMII REF_CLK to the MAC at REF_CLK (pin 19). For 50 MHz clock mode, the KSZ8051RNL takes in the 50 MHz RMII REF_CLK from the MAC or system board at XI (pin 9) and leaves the REF_CLK (pin 19) as a no connect.

3.3.5 TRANSMIT ENABLE (TXEN)

TXEN indicates that the MAC is presenting dibits on TXD[1:0] for transmission. It is asserted synchronously with the first dibit of the preamble and remains asserted while all dibits to be transmitted are presen ted on the RMII. It is negated before the first REF_CLK following the final dibit of a frame. TXEN transitions synchronously with respect to REF_CLK. TABLE 3-2: RMII SIGNAL DEFINITION RMII Signal Name Direction with Respect to PHY KSZ8051RNL Signal Direction with Respect to MAC Description REF_CLK Output (25 MHz clock mode)/<no connect> (50 MHz clock mode) Input/Input or <no connect> Synchronous 50 MHz reference clock for receive, transmit, and control interface TXEN Input Output Transmit Enable TXD[1:0] Input Output Transmit Data[1:0] CRS_DV Output Input Carrier Sense/Receive Data Valid RXD[1:0] Output Input Receive Data[1:0] RXER Output Input or not required Receive Error

 2016 Microchip Technology Inc. DS00002310A-page 21 KSZ8051MNL/RNL

3.3.6 TRANSMIT DATA[1:0] (TXD[1:0])

TXD[1:0] transitions synchronously with respect to REF_CLK. When TXEN is asserted, the PHY accepts TXD[1:0] for transmission. TXD[1:0] is 00 to indicate idle when TXEN is de-asserted. The PHY ignores va lues other than 00 on TXD[1:0] while TXEN is de-asserted.

3.3.7 CARRIER SENSE/RECEIVE DATA VALID (CRS_DV)

The PHY asserts CRS_DV when the receive medium is non-idle. It is asserted asynchronously when a carrier is detected. This happens when squelch is passed in 10 Mbps mode, and w hen two non-contiguous 0s in 10 bits are detected in 100 Mbps mode. Loss of carrier results in the de-assertion of CRS_DV. While carrier detection criteria are met, CRS_DV remains asse rted continuously from the first recovered dibit of the frame through the final recovered dibit. It is negated before the first REF_CLK th at follows the final dibit. The data on RXD[1:0] is considered valid after CRS_DV is asserted. However, because the assertion of CRS_DV is asynchronous relative to REF_CLK, the data on RXD[1:0] is 00 until receive signals are properly decoded.

3.3.8 RECEIVE DATA[1:0] (RXD[1:0])

RXD[1:0] transitions synchronously with respect to REF_ CLK. For each clock period in which CRS_DV is asserted, RXD[1:0] transfers two bits of recovered data from the PHY. RXD[1:0] is 00 to indicate idle when CRS_DV is de-asserted. The MAC ignores values other than 00 on RXD[1:0] while CRS_DV is de-asserted.

3.3.9 RECEIVE ERROR (RXER)

RXER is asserted for one or more REF_CLK periods to indicate that a symbol error (for example, a coding error that a PHY can detect that may otherwise be undetectable by the MAC sub-layer) was detected somewhere in the frame being transferred from the PHY . RXER transitions synchronously with respect to REF_CLK. While CRS_DV is de-asserted, RXER has no effect on the MAC.

3.3.10 COLLISION DETECTION (COL)

The MAC regenerates the COL signal of the MII from TXEN and CRS_DV.

3.3.11 RMII SIGNAL DIAGRAM

The KSZ8051RNL RMII pin connections to the MAC for 25 MHz clock mode are shown in Figure 3-3. The connections for 50 MHz clock mode are shown in Figure 3-4.

 2016 Microchip Technology Inc. DS00002310A-page 23 KSZ8051MNL/RNL

3.4 Back-to-Back Mode – 100 Mbps Copper Repeater

Two KSZ8051MNL/RNL devices can be connected back-to-back to form a 100BASE-TX copper repeater.

3.4.1 MII BACK-TO-BACK MO DE (KSZ8051MNL ONLY)

In MII back-to-back mode, a KSZ8051MNL interfaces with another KSZ8051MNL to provide a complete 100 Mbps cop- per repeater solution. The KSZ8051MNL devices are configured to MII back-to-back mode after power-up or reset with the following:

• Strap-in pin CONFIG[2:0] (pins 18, 29, 28) set to 110.
• A common 25 MHz reference clock connected to XI (Pin 9) of both KSZ8051MNL devices.
• MII signals connected as shown in Table 3-3. FIGURE 3-5: KSZ8051MNL/RNL TO KSZ8051MNL/RNL BACK-TO-BACK COPPER REPEATER TABLE 3-3: MII SIGNAL CONNECTION FOR MI I BACK-TO-BACK MODE (100BASE-TX COPPER REPEATER) KSZ8051MNL (100BASE-TX Copper) [Device 1] KSZ8051MNL (100BASE-TX Copper) [Device 2] Pin Name Pin Number Pin Type Pin Name Pin Number Pin Type RXDV 18 Output TXEN 23 Input RXD3 13 Output TXD3 27 Input RXD2 14 Output TXD2 26 Input RXD1 15 Output TXD1 25 Input RXD0 16 Output TXD0 24 Input TXEN 23 Input RXDV 18 Output TXD3 27 Input RXD3 13 Output TXD2 26 Input RXD2 14 Output TXD1 25 Input RXD1 15 Output

DS00002310A-page 24  2016 Microchip Technology Inc.

3.4.2 RMII BACK-TO-BACK MO DE (KSZ8051RNL ONLY)

In RMII back-to-back mode, a KSZ8051RNL interfaces with another KSZ8051RNL to provide a complete 100 Mbps cop- per repeater solution. The KSZ8051RNL devices are configured to RMII back-to-back mode after power-up or reset with the following:

• Strap-in pin CONFIG[2:0] (pins 18, 29, 28) set to 101.
• A common 50 MHz reference clock connected to XI (pin 9) of both KSZ8051RNL devices.
• RMII signals connected as shown in Table 3-4.

3.5 MII Management (MIIM) Interface

The KSZ8051MNL/RNL supports the IEEE 8 02.3 MII management interface, also known as the Management Data Input/Output (MDIO) interface. This interface allows an uppe r-layer device, such as a MAC processor, to monitor and control the state of the KSZ8051MNL/RNL. An external device with MIIM capability is used to read the PHY status and/ or configure the PHY settings. More details about the MIIM interface can be found in Clause 22.2.4 of the IEEE 802.3 Specification. The MIIM interface consists of the following:

• A physical connection that incorporates th e clock line (MDC) and the data line (MDIO).
• A specific protocol that o perates across the physical connection mentioned earlier, which allows the external con- troller to communicate with one or more PHY devices.
• A set of 16-bit MDIO registers. Registers [0:8] are st andard registers, and their functions are defined in the IEEE 802.3 Specification. The additional registers are provided for expanded functionality. See the Register Descrip- tions section. As the default, the KSZ8051MNL/RNL supports unique PHY addresses 1 to 7, and broadcast PHY address 0. The latter is defined in the IEEE 802.3 Specification, and can be used to read/write to a single KSZ8051MNL/RNL device, or write to multiple KSZ8051MNL/RNL devices simultaneously. PHY address 0 can optionally be disabled as the broadcas t address by either hardware pin strapping (B-CAST_OFF, pin 19) or software (Register 16h, bit [9]), and assigned as a unique PHY address. The PHYAD[2:0] strap-in pins are used to assign a unique PHY address between 0 and 7 to each KSZ8051MNL/RNL device. The MIIM interface can operates up to a maximum clock speed of 10 MHz MAC clock. Table 3-5 shows the MII management frame format for the KSZ8051MNL/RNL. TXD0 24 Input RXD0 16 OutputTABLE 3-4: RMII SIGNAL CONNECTION FO R RMII BACK-TO-BACK MODE (100BASE-TX COPPER REPEATER) KSZ8051RNL (100BASE-TX Copper) [Device 1] KSZ8051RNL (100BASE-TX Copper) [Device 2] Pin Name Pin Number Pin Type Pin Name Pin Number Pin Type CRSDV 18 Output TXEN 23 Input RXD1 15 Output TXD1 25 Input RXD0 16 Output TXD0 24 Input TXEN 23 Input CRSDV 18 Output TXD1 25 Input RXD1 15 Output TXD0 24 Input RXD0 16 Output TABLE 3-3: MII SIGNAL CONNECTION FOR MI I BACK-TO-BACK MODE (100BASE-TX COPPER REPEATER) (CONTINUED) KSZ8051MNL (100BASE-TX Copper) [Device 1] KSZ8051MNL (100BASE-TX Copper) [Device 2] Pin Name Pin Number Pin Type Pin Name Pin Number Pin Type

 2016 Microchip Technology Inc. DS00002310A-page 25 KSZ8051MNL/RNL

3.6 Interrupt (INTRP)

INTRP (pin 21) is an optional interrupt signal that is used to inform the external controller that there has been a status update to the KSZ8051MNL/RNL PHY Register. Bits [15:8] of Register 1Bh are the interrupt control bits to enable and disable the conditions for asserting the INTRP signal. Bits [7:0] of Register 1Bh are the interrupt status bits to indicate which interrupt conditions have occurred. The interrupt status bits are cleared after reading Register 1Bh. Bit [9] of Register 1Fh sets the interrupt level to active high or active low. The default is active low. The MII management bus option gives the MAC processor complete access to the KSZ8051MNL/RNL control and sta- tus registers. Additionally, an interrupt pin eliminates the need for the processor to poll the PHY for status change.

3.7 HP Auto MDI/MDI-X

HP Auto MDI/MDI-X configuration eliminates the need to decide whether to use a straight cable or a crossover cable between the KSZ8051MNL/RNL and its li nk partner. This feature allows the KSZ8051MNL/RNL to use either type of cable to connect with a link partner that is in either MDI or MDI-X mode. The auto-sense function detects transmit and receive pairs from the link partner and assigns transmit and receive pairs to the KSZ8051MNL/RNL accordingly. HP Auto MDI/MDI-X is enabled by default. It is disabled by writing a ‘1’ to Register 1Fh, bit [13]. MDI and MDI-X mode is selected by Register 1Fh, bit [14] if HP Auto MDI/MDI-X is disabled. An isolation transformer with symmetrical transmit and receive data paths is recommended to support Auto MDI/MDI-X. Table 3-6 shows how the IEEE 802.3 Standard defines MDI and MDI-X.

3.7.1 STRAIGHT CABLE

A straight cable connects an MDI device to an MDI-X device, or an MDI-X device to an MDI device. Figure 3-6 shows a typical straight cable connection between a NIC card (MDI device) and a switch or hub (MDI-X device). TABLE 3-5: MII MANAGEMENT FRAME FORMAT FOR THE KSZ8051MNL/RNL Preamble Start of Frame Read/ Write OP Code PHY Address Bits[4:0] REG Address Bits[4:0] TA Data Bits[15:0] Idle Read 32 1’s 01 10 00AAA RRRRR Z0 DDDDDDDD_DDDDDDDD Z Write 32 1’s 01 01 00AAA RRRRR 10 DDDDDDDD_DDDDDDDD Z TABLE 3-6: MDI/MDI- X PIN DESCRIPTION MDI MDI-X RJ-45 Pin Signal RJ-45 Pin Signal

1 TX+ 1 RX+

2T X –2R X –

3 RX+ 3 TX+

6 RX– 6 TX–

DS00002310A-page 26  2016 Microchip Technology Inc.

3.7.2 CROSSOVER CABLE

A crossover cable connects an MDI device to another MDI device, or an MDI-X device to another MDI-X device. Figure 3-7 shows a typical crossover cable connection between two switches or hubs (two MDI-X devices). FIGURE 3-6: TYPICAL STRAIGHT CABLE CONNECTION FIGURE 3-7: TYPICAL CROSSOVER CABLE CONNECTION RECEIVE PAIR TRANSMIT PAIR RECEIVE PAIR TRANSMIT PAIR MODULAR CONNECTOR (RJ-45) NIC STRAIGHT CABLE 10/100 ETHERNET MEDIA DEPENDENT INTERFACE 10/100 ETHERNET MEDIA DEPENDENT INTERFACE MODULAR CONNECTOR (RJ-45) HUB (REPEATER OR SWITCH) RECEIVE PAIR RECEIVE PAIR TRANSMIT PAIR TRANSMIT PAIR 10/100 ETHERNET MEDIA DEPENDENT INTERFACE 10/100 ETHERNET MEDIA DEPENDENT INTERFACE MODULAR CONNECTOR (RJ-45) HUB (REPEATER OR SWITCH) CROSSOVER CABLE MODULAR CONNECTOR (RJ-45) HUB (REPEATER OR SWITCH)

 2016 Microchip Technology Inc. DS00002310A-page 27 KSZ8051MNL/RNL

3.8 Loopback Mode

The KSZ8051MNL/RNL supports the following loopback operations to verify analog and/or digital data paths.

• Local (digital) loopback
• Remote (analog) loopback

3.8.1 LOCAL (DIG ITAL) LOOPBACK

This loopback mode checks the MII/RMII transmit and re ceive data paths between the KSZ8051MNL/RNL and the external MAC, and is supported for both speeds (10/100 Mbps) at full-duplex. The loopback data path is shown in Figure 3-8. 1. The MII/RMII MAC transmits fr ames to the KSZ8051MNL/RNL. 2. Frames are wrapped around inside the KSZ8051MNL/RNL. 3. The KSZ8051MNL/RNL transmits fr ames back to the MII/RMII MAC. 4. Except the frames back to the RMII MAC, the tr ansmit frames also go out from the copper port. The following programming action and register settings are used for local loopback mode: For 10/100 Mbps loopback: Set Register 0h, Bit [14] = 1 // Enable local loopback mode Bit [13] = 0/1 // Select 10 Mbps/100 Mbps speed Bit [12] = 0 // Disable auto-negotiation Bit [8] = 1 // Select full-duplex mode

3.8.2 REMOTE (ANALOG) LOOPBACK

This loopback mode checks the line (differential pairs, tran sformer, RJ-45 connector, Et hernet cable) transmit and receive data paths between the KSZ8051MNL/RNL and its li nk partner, and is supported for 100BASE-TX full-duplex mode only. The loopback data path is shown in Figure 3-9. 1. The Fast Ethernet (1 00BASE-TX) PHY link partner transmits frames to the KSZ8051MNL/RNL. 2. Frames are wrapped around inside the KSZ8051MNL/RNL. 3. The KSZ8051MNL/RNL transmits frames back to the Fast Ethernet (100BASE-TX) PHY link partner. FIGURE 3-8: LOCAL (DIGITAL) LOOPBACK MII/RMII MAC MII/ RMII AFE (ANALOG) KSZ8051MNL/RNL PCS (DIGITAL)

DS00002310A-page 28  2016 Microchip Technology Inc. The following programming steps and register settings are used for remote loopback mode: 1. Set Register 0h, Bits [13] = 1 // Select 100 Mbps speed Bit [12] = 0 // Disable auto-negotiation Bit [8] = 1 // Select full-duplex mode Or just auto-negotiate and link up at 100BASE-TX full-duplex mode with the link partner. 2. Set Register 1Fh, Bit [2] = 1 // Enable remote loopback mode

3.9 LinkMD ® Cable Diagnostic

The LinkMD function uses time-domain reflectometry (TDR) to analyze the cabling plant for common cabling problems. These include open circuits, short circuits, and impedance mismatches. LinkMD works by sending a pulse of known amplitude and duration down the MDI or MDI-X pair, then analyzing the shape of the reflected signal to determine the type of fault. The time duration for the reflected signal to return provides the approximate distance to the cabling fault. The LinkMD function processes this TDR information and presents it as a numerical value that can be translated to a cable distance. LinkMD is initiated by accessing register 1Dh, the LinkMD Cable Diagnostic register, in conjunction with Register 1Fh, the PHY Control 2 Register. The latter register is used to disable Auto MDI/MDI-X and to select either MDI or MDI-X as the cable differential pair for testing.

3.9.1 USAGE

The following is a sample procedure for using LinkMD with Registers 1Dh and 1Fh: 1. Disable auto MDI/MDI-X by writing a ‘1’ to Register 1Fh, bit [13]. 2. Start cable diagnostic test by writing a ‘1’ to Regist er 1Dh, bit [15]. This enable bit is self-clearing. 3. Wait (poll) for Register 1Dh, bit [15] to return a ‘0’, and indicating cable diagnostic test is completed. 4. Read cable diagnostic test results in Register 1Dh, bits [14:13]. The results are as follows: 00 = normal condition (valid test) 01 = open condition detected in cable (valid test) 10 = short condition detected in cable (valid test) FIGURE 3-9: REMOTE (ANALOG) LOOPBACK RJ-45 RJ-45 CAT-5 (UTP) KSZ8051MNL/RNL 100BASE-TX LINK PARTNER AFE (ANALOG) PCS (DIGITAL) MII/ RMII

 2016 Microchip Technology Inc. DS00002310A-page 29 KSZ8051MNL/RNL 11 = cable diagnostic test failed (invalid test) The ‘11’ case, invalid test, occurs when the device is unable to shut down the link partner. In this instance, the test is not run because it would be impossible for the device to determine if the detected signal is a reflection of the signal generated or a signal from another source. 5. Get distance to fault by concatenati ng Register 1Dh, bits [8:0] and multiplying the result by a constant of 0.38. The distance to the cable fault can be determined by the following formula: EQUATION 3-1: Concatenated value of Registers 1Dh bits [8:0] should be converted to decimal before multiplying by 0.38. The constant (0.38) may be calibrated for different cabling conditions, including cables with a velocity of propagation that varies significantly from the norm.

3.10 NAND Tree Support

The KSZ8051MNL/RNL provides parametric NAND tree support for fault detection between chip I/Os and board. The NAND tree is a chain of nested NAND gates in which each KSZ8051MNL/RNL digital I/O (NAND tree input) pin is an input to one NAND gate along the chain. At the end of t he chain, the CRS/CONFIG1 pin provides the output for the nested NAND gates. The NAND tree test process includes:

• Enabling NAND tree mode
• Pulling all NAND tree input pins high
• Driving each NAND tree input pin low, sequentially, according to the NAND tree pin order
• Checking the NAND tree output to make sure there is a toggle high-to-low or low-to-high for each NAND tree input driven low Table 3-7 and Table 3-8 list the NAND tree pin orders for KSZ8051MNL and KSZ8051RNL, respectively. TABLE 3-7: NAND TREE TEST PIN ORDER FOR KSZ8051MNL Pin Number Pin Name NAND Tree Description

11 MDIO Input

12 MDC Input

13 RXD3 Input

14 RXD2 Input

15 RXD1 Input

16 RXD0 Input

18 RXDV Input

19 RXC Input

20 RXER Input

21 INTRP Input

22 TXC Input

23 TXEN Input

24 TXD0 Input

25 TXD1 Input

26 TXD2 Input

27 TXD3 Input

DD i s c etan· to cable fault in meters 0.38 Register 1Dh, bits[8:0]=

DS00002310A-page 30  2016 Microchip Technology Inc.

3.10.1 NAND TREE I/O TESTING

Use the following procedure to check for faults on the KSZ8051MNL/RNL digital I/O pin connections to the board: 1. Enable NAND tree mode using either a hardware strap-in pin (NAND_Tree#, Pin 21) or software (Register 16h, Bit [5]). 2. Use board logic to drive all KSZ8051MNL/RNL NAND tree input pins high. 3. Use board logic to drive each NAND tree input pin, in KSZ8051MNL/RNL NAND tree pin order, as follows: a) Toggle the first pin (MDIO) from high to low, and verify that the CRS/CONFIG1 pin switches from high to low to indicate that the first pin is connected properly. b) Leave the first pin (MDIO) low. c) Toggle the second pin (MDC) from high to low, and verify that the CRS/CONFIG1 pin switches from low to high to indicate that the second pin is connected properly. d) Leave the first pin (MDIO) and the second pin (MDC) low. e) Toggle the third pin (RXD3/PHYAD0) from high to lo w, and verify that the CRS/CONFIG1 pin switches from high to low to indicate that the third pin is connected properly. f) Continue with this sequence until all KSZ8051M NL/RNL NAND tree input pins have been toggled. Each KSZ8051MNL/RNL NAND tree input pin must cause the CRS /CONFIG1 output pin to toggle high-to-low or low- to-high to indicate a good connection. If the CRS/CONFIG1 pin fails to to ggle when the KSZ8051MNL/RNL input pin toggles from high to low, the input pin has a fault.

30 LED0 Input

31 LED1 Input

28 COL Input

29 CRS Output

TABLE 3-8: NAND TREE TEST PIN ORDER FOR KSZ8051RNL Pin Number Pin Name NAND Tree Description

13 PHYAD0 Input

14 PHYAD1 Input

18 CRS_DV Input

19 REF_CLK Input

28 CONFIG0 Input

29 CONFIG1 Output

TABLE 3-7: NAND TREE TEST PIN ORDER FOR KSZ8051MNL (CONTINUED) Pin Number Pin Name NAND Tree Description

 2016 Microchip Technology Inc. DS00002310A-page 31 KSZ8051MNL/RNL

3.11 Power Management

The KSZ8051MNL/RNL incorporates a number of power-management modes and features that provide methods to consume less energy. These are discussed in the following sections.

3.11.1 POWER-SAVING MODE

Power-saving mode is used to reduce the transceiver power consumption when the cable is unplugged. It is enabled by writing a ‘1’ to Register 1Fh, bit [10], and is in effect when auto-negotiation mode is enabled and the cable is discon- nected (no link). In this mode, the KSZ8051MNL/RNL shuts down all transceiver blocks, except for the transmitter, energy detect, and PLL circuits. By default, power-saving mode is disabled after power-up.

3.11.2 ENERGY-DETECT POWER-DOWN MODE

Energy-detect power-down (EDPD) mode is used to furthe r reduce transceiver power consumption when the cable is unplugged. It is enabled by writing a ‘0’ to Register 18h, bit [11], and is in effect when auto-negotiation mode is enabled and the cable is disconnected (no link). EDPD mode works with the PLL off (set by writing a ‘1’ to Register 10h, bit [4] to automatically turn the PLL off in EDPD mode) to turn off all KSZ8051MNL/RNL transceiver blocks except the transmitter and energy-detect circuits. Power can be reduced further by extending the time interval between transmissions of link pulses to check for the pres- ence of a link partner. The periodic transmission of link pulses is needed to ensure the KSZ8051MNL/RNL and its link partner, when operating in the same low-power state and with Auto MDI/MDI-X disabled, can wake up when the cable is connected between them. By default, energy-detect power-down mode is disabled after power-up.

3.11.3 POWER-DOWN MODE

Power-down mode is used to power down the KSZ8051MNL/RNL device when it is not in use after power-up. It is enabled by writing a ‘1’ to Register 0h, bit [11]. In this mode, the KSZ8051MNL/RNL disables all internal functions except the MII management interface. The KSZ8051MNL/RNL exits (disables) power-down mode after Register 0h, bit [11] is set back to ‘0’.

3.11.4 SLOW-OSCILLATOR MODE

Slow-oscillator mode is used to disconnect the input refe rence crystal/clock on XI (pin 9) and select the on-chip slow oscillator when the KSZ8051MNL/RNL device is not in use after power-up. It is enabled by writing a ‘1’ to Register 11h, bit [5]. Slow-oscillator mode works in conjunction with power-down mode to put the KSZ8051MNL/RNL device in the lowest power state, with all internal functions disabled except the MII management interf ace. To properly exit this mode and return to normal PHY operation, use the following programming sequence: 1. Disable slow-oscillator mode by writing a ‘0’ to Register 11h, Bit [5]. 2. Disable power-down mode by writing a ‘0’ to Register 0h, Bit [11]. 3. Initiate software reset by writin g a ‘1’ to Register 0h, Bit [15].

3.12 Reference Circuit for Power and Ground Connections

The KSZ8051MNL/RNL is a single 3.3V supply device with a built-in regulator to supply the 1.2V core. The power and ground connections are shown in Figure 3-10 and Table 3-9 for 3.3V VDDIO.

DS00002310A-page 32  2016 Microchip Technology Inc.

3.13 Typical Current/Power Consumption

Table 3-10, Table 3-11, and Table 3-12 show typical values for current consumption by the transceiver (VDDA_3.3) and digital I/O (VDDIO) power pins, and typical values for power consumption by the KSZ8051MNL/RNL device for the indi- cated nominal operating voltages. These current and power consumption values include the transmit driver current and on-chip regulator current for the 1.2V core. FIGURE 3-10: KSZ8051MNL/RNL POWER AND GROUND CONNECTIONS TABLE 3-9: KSZ8051MNL/RNL POWER PIN DESCRIPTION Power Pin Pin Number Description VDD_1.2 2 Decouple with 2.2 µF and 0.1 µF capacitors to ground. VDDA_3.3 3 Connect to board’s 3.3V supply through a ferrite bead. Decouple with 22 µF and 0.1 µF capacitors to ground. VDDIO 17 Connect to board’s 3.3V supply for 3.3V V DDIO. Decouple with 22 µF and 0.1 µF capacitors to ground. TABLE 3-10: TYPICAL CURRENT/POWER CONSUM PTION (VDDA_3.3 = 3.3V, VDDIO = 3.3V) Condition 3.3V Transceiver (VDDA_3.3) 3.3V Digital I/Os (VDDIO) Total Chip Power 100BASE-TX Link-up (no traffic) 34 mA 12 mA 152 mW 100BASE-TX Full-duplex @ 100% utilization 34 mA 13 mA 155 mW 10BASE-T Link-up (no traffic) 14 mA 11 mA 82.5 mW 10BASE-T Full-duplex @ 100% utilization 30 mA 11 mA 135 mW Power-saving mode (Reg. 1Fh, Bit [10] = 1) 14 mA 10 mA 79.2 mW EDPD mode (Reg. 18h, Bit [11] = 0) 10 mA 10 mA 66 mW EDPD mode (Reg. 18h, Bit [11] = 0) and PLL off (Reg. 10h, Bit [4] = 1) 3.77 mA 1.54 mA 17.5 mW Software power-down mode (Reg. 0h, Bit [11] =1) 2.59 mA 1.51 mA 13.5 mW VDDIO KSZ8051MNL/RNL VDD_1.2 0.1uF2.2uF GND 3.3V VDDA_3.3 Ferrite Bead Paddle 0.1uF22uF 0.1uF22uF

 2016 Microchip Technology Inc. DS00002310A-page 33 KSZ8051MNL/RNL Software power-down mode (Reg. 0h, Bit [11] =1) and slow-oscillator mode (Reg. 11h, Bit [5] =1) 1.36 mA 0.45 mA 5.97 mW TABLE 3-11: TYPICAL CURRENT/POWER CONSUM PTION (VDDA_3.3 = 3.3V, VDDIO = 2.5V) Condition 3.3V Transceiver (VDDA_3.3) 2.5V Digital I/Os (VDDIO) Total Chip Power 100BASE-TX Link-up (no traffic) 34 mA 11 mA 140 mW 100BASE-TX Full-duplex @ 100% utilization 34 mA 12 mA 142 mW 10BASE-T Link-up (no traffic) 15 mA 10 mA 74.5 mW 10BASE-T Full-duplex @ 100% utilization 27 mA 10 mA 114 mW Power-saving mode (Reg. 1Fh, Bit [10] = 1) 15 mA 10 mA 74.5 mW EDPD mode (Reg. 18h, Bit [11] = 0) 11 mA 10 mA 61.3 mW EDPD mode (Reg. 18h, Bit [11] = 0) and PLL off (Reg. 10h, Bit [4] = 1) 3.55 mA 1.35 mA 15.1 mW Software power-down mode (Reg. 0h, Bit [11] =1) 2.29 mA 1.34 mA 10.9 mW Software power-down mode (Reg. 0h, Bit [11] =1) and slow-oscillator mode (Reg. 11h, Bit [5] =1) 1.15 mA 0.29 mA 4.52 mW TABLE 3-12: TYPICAL CURRENT/POWER CONSUM PTION (VDDA_3.3 = 3.3V, VDDIO = 1.8V) Condition 3.3V Transceiver (VDDA_3.3) 1.8V Digital I/Os (VDDIO) Total Chip Power 100BASE-TX Link-up (no traffic) 34 mA 11 mA 132 mW 100BASE-TX Full-duplex @ 100% utilization 34 mA 12 mA 134 mW 10BASE-T Link-up (no traffic) 15 mA 9 mA 65.7 mW 10BASE-T Full-duplex @ 100% utilization 27 mA 9 mA 105 mW Power-saving mode (Reg. 1Fh, Bit [10] = 1) 15 mA 9 mA 65.7 mW EDPD mode (Reg. 18h, Bit [11] = 0) 11 mA 9 mA 52.5 mW EDPD mode (Reg. 18h, Bit [11] = 0) and PLL off (Reg. 10h, Bit [4] = 1) 4.05 mA 1.21 mA 15.5 mW Software power-down mode (Reg. 0h, Bit [11] =1) 2.79 mA 1.21 mA 11.4 mW Software power-down mode (Reg. 0h, Bit [11] =1) and slow-oscillator mode (Reg. 11h, Bit [5] =1) 1.65 mA 0.19 mA 5.79 mW TABLE 3-10: TYPICAL CURRENT/POWER CONSUM PTION (VDDA_3.3 = 3.3V, VDDIO = 3.3V) Condition 3.3V Transceiver (VDDA_3.3) 3.3V Digital I/Os (VDDIO) Total Chip Power

DS00002310A-page 34  2016 Microchip Technology Inc.

4.0 REGISTER DESCRIPTIONS

4.1 Register Map

TABLE 4-1: REGISTERS SUPPORTED BY KSZ8051MNL/RNL Register Number (hex) Description 0h Basic Control 1h Basic Status 2h PHY Identifier 1 3h PHY Identifier 2 4h Auto-Negotiation Advertisement 5h Auto-Negotiation Link Partner Ability 6h Auto-Negotiation Expansion 7h Auto-Negotiation Next Page 8h Auto-Negotiation Link Partner Next Page Ability 9h Reserved 10h Digital Reserved Control 11h AFE Control 1 12h - 14h Reserved 15h RXER Counter 16h Operation Mode Strap Override 17h Operation Mode Strap Status 18h Expanded Control 19h - 1Ah Reserved 1Bh Interrupt Control/Status 1Ch Reserved 1Dh LinkMD Control/Status 1Eh PHY Control 1 1Fh PHY Control 2

 2016 Microchip Technology Inc. DS00002310A-page 35 KSZ8051MNL/RNL

4.2 Register Descriptions

TABLE 4-2: REGISTER DESCRIPTIONS Address Name Description Mode Note 4-1 Default Register 0h – Basic Control

0.15 Reset

1 = Software reset 0 = Normal operation This bit is self-cleared after a ‘1’ is written to it. RW/SC 0

0.14 Loopback 1 = Loopback mode

0 = Normal operation RW 0

0.13 Speed Select

1 = 100 Mbps 0 = 10 Mbps This bit is ignored if auto-negotiation is enabled (Register 0.12 = 1). RW Set by the SPEED strap-in pin. See the Strap-In Options - KSZ8051MNL section for details.

0.12 Auto-Negoti-

1 = Enable auto-negotiation process 0 = Disable auto-negotiation process If enabled, the auto-negotiation result overrides the settings in Registers 0.13 and 0.8. RW Set by the NWAYEN strap-in pin. See the Strap-In Options - KSZ8051MNL section for details.

0.11 Power-Down

1 = Power-down mode 0 = Normal operation If software reset (Register 0.15) is used to exit power-down mode (Register 0.11 = 1), two soft- ware reset writes (Register 0.15 = 1) are required. The first write clears power-down mode; the sec- ond write resets the chip and re-latches the pin strapping pin values. RW 0

0.10 Isolate 1 = Electrical isolation of PHY from MII/RMII

0 = Normal operation RW Set by the ISO strap- in pin. See the Strap-In Options - KSZ8051MNL section for details.

0.9 Restart Auto-

1 = Restart auto-negotiation process 0 = Normal operation. This bit is self-cleared after a ‘1’ is written to it. RW/SC 0

0.8 Duplex Mode 1 = Full-duplex

0 = Half-duplex RW The inverse of the DUPLEX strap-in pin value. See the Strap-In Options - KSZ8051MNL section for details.

0.7 Collision Test 1 = Enable COL test

0 = Disable COL test RW 0 0.6:0 Reserved Reserved RO 000_0000 Register 1h - Basic Status 1.15 100BASE-T4 1 = T4 capable 0 = Not T4 capable RO 0 1.14 100BASE-TX Full-Duplex 1 = Capable of 100 Mbps full-duplex 0 = Not capable of 100 Mbps full-duplex RO 1

DS00002310A-page 36  2016 Microchip Technology Inc. 1.13 100BASE-TX Half-Duplex 1 = Capable of 100 Mbps half-duplex 0 = Not capable of 100 Mbps half-duplex RO 1 1.12 10BASE-T Full-Duplex 1 = Capable of 10 Mbps full-duplex 0 = Not capable of 10 Mbps full-duplex RO 1 1.11 10BASE-T Half-Duplex 1 = Capable of 10 Mbps half-duplex 0 = Not capable of 10 Mbps half-duplex RO 1 1.10:7 Reserved Reserved RO 000_0

1.6 No Preamble 1 = Preamble suppression

0 = Normal preamble RO 1 1.5 Auto-Negoti- ation Com- plete 1 = Auto-negotiation process completed 0 = Auto-negotiation process not completed RO 0

1.4 Remote Fault 1 = Remote fault

0 = No remote fault RO/LH 0

1.3 Auto-Negoti-

1 = Can perform auto-negotiation 0 = Cannot perform auto-negotiation RO 1

1.2 Link Status 1 = Link is up

0 = Link is down RO/LL 0

1.1 Jabber

1 = Jabber detected 0 = Jabber not detected (default is low) RO/LH 0

1.0 Extended

Capability 1 = Supports extended capability registers RO 1 Register 2h - PHY Identifier 1 2.15:0 PHY ID Number Assigned to the 3rd through 18th bits of the Organi- zationally Unique Identifier (OUI). KENDIN Com- munication’s OUI is 0010A1 (hex). RO 0022h Register 3h - PHY Identifier 2 3.15:10 PHY ID Num- ber Assigned to the 19th through 24th bits of the Orga- nizationally Unique Identifier (OUI). KENDIN Com- munication’s OUI is 0010A1 (hex). RO 0001_01 3.9:4 Model Num- ber Six-bit manufacturer’s model number RO 01_0110 3.3:0 Revision Number Four-bit manufacturer’s revision number RO Indicates silicon revision. Register 4h - Auto-Negotiation Advertisement

4.15 Next Page 1 = Next page capable

0 = No next page capability RW 0

4.14 Reserved Reserved RO 0

4.13 Remote Fault 1 = Remote fault supported

0 = No remote fault RW 0

4.12 Reserved Reserved RO 0

4.11:10 Pause [00] = No pause [10] = Asymmetric pause [01] = Symmetric pause [11] = Asymmetric and symmetric pause RW 00 4.9 100BASE-T4 1 = T4 capable 0 = No T4 capability RO 0 TABLE 4-2: REGISTER DESC RIPTIONS (CONTINUED) Address Name Description Mode Note 4-1 Default

 2016 Microchip Technology Inc. DS00002310A-page 37 KSZ8051MNL/RNL 4.8 100BASE-TX Full-Duplex 1 = 100 Mbps full-duplex capable 0 = No 100 Mbps full-duplex capability RW Set by the SPEED strap-in pin. See the Strap-In Options - KSZ8051MNL section for details. 4.7 100BASE-TX Half-Duplex 1 = 100 Mbps half-duplex capable 0 = No 100 Mbps half-duplex capability RW Set by the SPEED strap-in pin. See the Strap-In Options - KSZ8051MNL section for details. 4.6 10BASE-T Full-Duplex 1 = 10 Mbps full-duplex capable 0 = No 10 Mbps full-duplex capability RW 1 4.5 10BASE-T Half-Duplex 1 = 10 Mbps half-duplex capable 0 = No 10 Mbps half-duplex capability RW 1 4.4:0 Selector Field [00001] = IEEE 802.3 RW 0_0001 Register 5h - Auto-Negotiation Link Partner Ability

5.15 Next Page 1 = Next page capable

0 = No next page capability RO 0

5.14 Acknowledge 1 = Link code word received from partner

0 = Link code word not yet received RO 0

5.13 Remote Fault 1 = Remote fault detected

0 = No remote fault RO 0

5.12 Reserved Reserved RO 0

5.11:10 Pause [00] = No pause [10] = Asymmetric pause [01] = Symmetric pause [11] = Asymmetric and symmetric pause RO 00 5.9 100BASE-T4 1 = T4 capable 0 = No T4 capability RO 0 5.8 100BASE-TX Full-Duplex 1 = 100 Mbps full-duplex capable 0 = No 100 Mbps full-duplex capability RO 0 5.7 100BASE-TX Half-Duplex 1 = 100 Mbps half-duplex capable 0 = No 100 Mbps half-duplex capability RO 0 5.6 10BASE-T Full-Duplex 1 = 10 Mbps full-duplex capable 0 = No 10 Mbps full-duplex capability RO 0 5.5 10BASE-T Half-Duplex 1 = 10 Mbps half-duplex capable 0 = No 10 Mbps half-duplex capability RO 0 5.4:0 Selector Field [00001] = 802.3 after AN completes. RO 0_0000 Register 6h - Auto-Negotiation Expansion 6.15:5 Reserved Reserved RO 0000_0000_000 6.4 Parallel Detection Fault 1 = Fault detected by parallel detection 0 = No fault detected by parallel detection RO/LH 0 6.3 Link Partner Next Page Able 1 = Link partner has next page capability 0 = Link partner does not have next page capability RO 0 TABLE 4-2: REGISTER DESCRIPTIONS (CONTINUED) Address Name Description Mode Note 4-1 Default

DS00002310A-page 38  2016 Microchip Technology Inc.

6.2 Next Page

1 = Local device has next page capability 0 = Local device does not have next page capabil- ity RO 1

6.1 Page

1 = New page received 0 = New page not received yet RO/LH 0 6.0 Link Partner Auto-Negoti- ation Able 1 = Link partner has auto-negotiation capability 0 = Link partner does not have auto-negotiation capability RO 0 Register 7h - Auto-Negotiation Next Page

7.15 Next Page 1 = Additional next pages will follow

0 = Last page RW 0

7.14 Reserved Reserved RO 0

7.13 Message

1 = Message page 0 = Unformatted page RW 1

7.12 Acknowl-

1 = Will comply with message 0 = Cannot comply with message RW 0

7.11 Toggle

1 = Previous value of the transmitted link code word equaled logic 1 0 = Logic 0 RO 0 7.10:0 Message Field 11-bit wide field to encode 2048 messages RW 000_0000_0001 Register 8h - Link Partner Next Page Ability

8.15 Next Page 1 = Additional next pages will follow

0 = Last page RO 0

8.14 Acknowledge 1 = Successful receipt of link word

0 = No successful receipt of link word RO 0

8.13 Message

1 = Message page 0 = Unformatted page RO 0

8.12 Acknowl-

1 = Can act on the information 0 = Cannot act on the information RO 0

8.11 Toggle

1 = Previous value of transmitted link code word equal to logic 0 0 = Previous value of transmitted link code word equal to logic 1 RO 0 8.10:0 Message Field 11-bit wide field to encode 2048 messages RO 000_0000_0000 Register 10h – Digital Reserved Control 10.15:5 Reserved Reserved RW 0000_0000_000

10.4 PLL Off

1 = Turn PLL off automatically in EDPD mode 0 = Keep PLL on in EDPD mode. See also Register 18h, Bit [11] for EDPD mode RW 0 10.3:0 Reserved Reserved RW 0000 Register 11h – AFE Control 1 11.15:6 Reserved Reserved RW 0000_0000_00 TABLE 4-2: REGISTER DESC RIPTIONS (CONTINUED) Address Name Description Mode Note 4-1 Default

 2016 Microchip Technology Inc. DS00002310A-page 39 KSZ8051MNL/RNL 11.5 Slow-Oscilla- tor Mode Enable Slow-oscillator mode is used to disconnect the input reference crystal/clock on the XI pin and select the on-chip slow oscillator when the KSZ8051MNL/RNL device is not in use after power-up. 1 = Enable 0 = Disable This bit automatically sets software power-down to the analog side when enabled. RW 0 11.4:0 Reserved Reserved RW 0_0000 Register 15h – RXER Counter 15.15:0 RXER Counter Receive error counter for symbol error frames RO/SC 0000h Register 16h – Operation Mode Strap Override 16.15:11 Reserved Reserved RW 0000_0

16.10 Reserved Reserved RO 0

16.9 CAST_OFF Override 1 = Override strap-in for B-CAST_OFF If bit is ‘1’, PHY Address 0 is non-broadcast. RW 0

16.8 Reserved Reserved RW 0

16.7 MII B-to-B

1 = Override strap-in for MII back-to-back mode (also set bit 0 of this register to ‘1’) This bit applies only to KSZ8051MNL. RW 0

16.6 RMII B-to-B

1 = Override strap-in for RMII back-to-back mode (also set bit 1 of this register to ‘1’) This bit applies only to KSZ8051RNL. RW 0

16.5 NAND Tree

Override 1 = Override strap-in for NAND tree mode RW 0 16.4:2 Reserved Reserved RW 0_00

16.1 RMII

1 = Override strap-in for RMII mode This bit applies only to KSZ8051RNL. RW 0

16.0 MII Override 1 = Override strap-in for MII mode

This bit applies only to KSZ8051MNL. RW 1 Register 17h - Operation Mode Strap Status 17.15:13 PHYAD[2:0] Strap-In Sta- tus [000] = Strap to PHY Address 0 [001] = Strap to PHY Address 1 [010] = Strap to PHY Address 2 [011] = Strap to PHY Address 3 [100] = Strap to PHY Address 4 [101] = Strap to PHY Address 5 [110] = Strap to PHY Address 6 [111] = Strap to PHY Address 7 RO — 17.12:10 Reserved Reserved RO — 17.9 CAST_OFF Strap-In Status 1 = Strap to B-CAST_OFF If bit is ‘1’, PHY Address 0 is non-broadcast. RO —

17.8 Reserved Reserved RO —

TABLE 4-2: REGISTER DESCRIPTIONS (CONTINUED) Address Name Description Mode Note 4-1 Default

DS00002310A-page 40  2016 Microchip Technology Inc. 17.7 MII B-to-B Strap-In Status 1 = Strap to MII back-to-back mode This bit applies only to KSZ8051MNL. RO — 17.6 RMII B-to-B Strap-In Status 1 = Strap to RMII back-to-back mode This bit applies only to KSZ8051RNL. RO — 17.5 NAND Tree Strap-In Status 1 = Strap to NAND tree mode RO — 17.4:2 Reserved Reserved RO —

17.1 RMII Strap-In

1 = Strap to RMII mode This bit applies only to KSZ8051RNL. RO —

17.0 MII Strap-In

1 = Strap to MII mode This bit applies only to KSZ8051MNL. RO — Register 18h - Expanded Control 18.15:12 Reserved Reserved RW 0000

18.11 EDPD

Energy-detect power-down mode 1 = Disable 0 = Enable See also Register 10h, Bit [4] for PLL off. RW 1 18.10 100BASE-TX Latency 1 = MII output is random latency 0 = MII output is fixed latency For both settings, all bytes of received preamble are passed to the MII output. This bit applies only to the KSZ8051MNL. RW 0 18.9:7 Reserved Reserved RW 00_0 18.6 10BASE-T Preamble Restore 1 = Restore received preamble to MII output 0 = Remove all seven bytes of preamble before sending frame (starting with SFD) to MII output This bit applies only to the KSZ8051MNL. RW 0 18.5:0 Reserved Reserved RW 00_0001 Register 1Bh – Interrupt Control/Status 1B.15 Jabber Inter- rupt Enable 1 = Enable jabber interrupt 0 = Disable jabber interrupt RW 0 1B.14 Receive Error Inter- rupt Enable 1 = Enable receive error interrupt 0 = Disable receive error interrupt RW 0 1B.13 Page Received Interrupt Enable 1 = Enable page received interrupt 0 = Disable page received interrupt RW 0 1B.12 Parallel Detect Fault Interrupt Enable 1 = Enable parallel detect fault interrupt 0 = Disable parallel detect fault interrupt RW 0 1B.11 Link Partner Acknowl- edge Inter- rupt Enable 1 = Enable link partner acknowledge interrupt 0 = Disable link partner acknowledge interrupt RW 0 TABLE 4-2: REGISTER DESC RIPTIONS (CONTINUED) Address Name Description Mode Note 4-1 Default

 2016 Microchip Technology Inc. DS00002310A-page 41 KSZ8051MNL/RNL 1B.10 Link-Down Interrupt Enable 1= Enable link-down interrupt 0 = Disable link-down interrupt RW 0 1B.9 Remote Fault Interrupt Enable 1 = Enable remote fault interrupt 0 = Disable remote fault interrupt RW 0 1B.8 Link-Up Interrupt Enable 1 = Enable link-up interrupt 0 = Disable link-up interrupt RW 0 1B.7 Jabber Interrupt 1 = Jabber occurred 0 = Jabber did not occur RO/SC 0 1B.6 Receive Error Interrupt 1 = Receive error occurred 0 = Receive error did not occur RO/SC 0 1B.5 Page Receive Interrupt 1 = Page receive occurred 0 = Page receive did not occur RO/SC 0 1B.4 Parallel Detect Fault Interrupt 1 = Parallel detect fault occurred 0 = Parallel detect fault did not occur RO/SC 0 1B.3 Link Partner Acknowl- edge Inter- rupt 1 = Link partner acknowledge occurred 0 = Link partner acknowledge did not occur RO/SC 0 1B.2 Link-Down Interrupt 1 = Link-down occurred 0 = Link-down did not occur RO/SC 0 1B.1 Remote Fault Interrupt 1 = Remote fault occurred 0 = Remote fault did not occur RO/SC 0 1B.0 Link-Up Interrupt 1 = Link-up occurred 0 = Link-up did not occur RO/SC 0 Register 1Dh – LinkMD Control/Status 1D.15 Cable Diag- nostic Test Enable 1 = Enable cable diagnostic test. After test has completed, this bit is self-cleared. 0 = Indicates cable diagnostic test (if enabled) has completed and the status information is valid for read. RW/SC 0 1D.14:13 Cable Diag- nostic Test Result [00] = Normal condition [01] = Open condition has been detected in cable [10] = Short condition has been detected in cable [11] = Cable diagnostic test has failed RO 00 1D.12 Short Cable Indicator 1 = Short cable (<10 meter) has been detected by LinkMD RO 0 1D.11:9 Reserved Reserved RW 000 1D.8:0 Cable Fault Counter Distance to fault RO 0_0000_0000 Register 1Eh – PHY Control 1 1E.15:10 Reserved Reserved RO 0000_00 1E.9 Enable Pause (Flow Control) 1 = Flow control capable 0 = No flow control capability RO 0 TABLE 4-2: REGISTER DESCRIPTIONS (CONTINUED) Address Name Description Mode Note 4-1 Default

DS00002310A-page 42  2016 Microchip Technology Inc. 1E.8 Link Status 1 = Link is up 0 = Link is down RO 0 1E.7 Polarity Status 1 = Polarity is reversed 0 = Polarity is not reversed RO — 1E.6 Reserved Reserved RO 0 1E.5 MDI/MDI-X State 1 = MDI-X 0 = MDI RO — 1E.4 Energy Detect 1 = Signal present on receive differential pair 0 = No signal detected on receive differential pair RO 0 1E.3 PHY Isolate 1 = PHY in isolate mode 0 = PHY in normal operation RW 0 1E.2:0 Operation Mode Indication [000] = Still in auto-negotiation [001] = 10BASE-T half-duplex [010] = 100BASE-TX half-duplex [011] = Reserved [100] = Reserved [101] = 10BASE-T full-duplex [110] = 100BASE-TX full-duplex [111] = Reserved RO 000 Register 1Fh – PHY Control 2 1F.15 HP_MDIX 1 = HP Auto MDI/MDI-X mode 0 = Microchip Auto MDI/MDI-X mode RW 1 1F.14 MDI/MDI-X Select When Auto MDI/MDI-X is disabled, 1 = MDI-X mode Transmit on RXP, RXM (Pins 5, 4) and Receive on TXP , TXM (Pins 7, 6) 0 = MDI mode Transmit on TXP , TXM (Pins 7, 6) and Receive on RXP , RXM (Pins 5, 4) RW 0 1F.13 Pair Swap Disable 1 = Disable Auto MDI/MDI-X 0 = Enable Auto MDI/MDI-X RW 0 1F.12 Reserved Reserved RW 0 1F.11 Force Link 1 = Force link pass 0 = Normal link operation This bit bypasses the control logic and allows the transmitter to send a pattern even if there is no link. RW 0 1F.10 Power Saving 1 = Enable power saving 0 = Disable power saving RW 0 1F.9 Interrupt Level 1 = Interrupt pin active high 0 = Interrupt pin active low RW 0 1F.8 Enable Jabber 1 = Enable jabber counter 0 = Disable jabber counter RW 1 1F.7 RMII Refer- ence Clock Select 1 = RMII 50 MHz clock mode; clock input to XI (pin 9) is 50 MHz 0 = RMII 25 MHz clock mode; clock input to XI (pin 9) is 25 MHz This bit applies only to KSZ8051RNL. RW 0 1F.6 Reserved Reserved RW 0 TABLE 4-2: REGISTER DESC RIPTIONS (CONTINUED) Address Name Description Mode Note 4-1 Default

 2016 Microchip Technology Inc. DS00002310A-page 43 KSZ8051MNL/RNL Note 4-1 RW = Read/Write; RO = Read Only; SC = Self-Cleared; LH = Latch High; LL = Latch Low. 1F.5:4 LED Mode [00] = LED1: Speed LED0: Link/Activity [01] = LED1: Activity LED0: Link [10], [11] = Reserved RW 00 1F.3 Disable Transmitter 1 = Disable transmitter 0 = Enable transmitter RW 0 1F.2 Remote Loopback 1 = Remote (analog) loopback is enabled 0 = Normal mode RW 0 1F.1 Enable SQE Test 1 = Enable SQE test 0 = Disable SQE test RW 0 1F.0 Disable Data Scrambling 1 = Disable scrambler 0 = Enable scrambler RW 0 TABLE 4-2: REGISTER DESCRIPTIONS (CONTINUED) Address Name Description Mode Note 4-1 Default

DS00002310A-page 44  2016 Microchip Technology Inc.

5.0 OPERATIONAL CHARACTERISTICS

5.1 Absolute Maximum Ratings*

Supply Voltage (VIN) *Exceeding the absolute maximum rating may damage the device. Stresses greater than the absolute maximum rating may cause permanent damage to the device. Operation of the device at these or any other conditions above those spec- ified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability.

5.2 Operating Ratings**

Ambient Temperature (TA) **The device is not guaranteed to function outside its operating ratings. Note: Do not drive input signals without power supplied to the device.

 2016 Microchip Technology Inc. DS00002310A-page 45 KSZ8051MNL/RNL

6.0 ELECTRICAL CHARACTERISTICS

TA = 25°C. Specification is for packaged product only. TABLE 6-1: ELECTRICAL CHARACTERISTICS Parameters Symbol Min. Typ. Max. Units Note Supply Current (VDDIO, VDDA_3.3 = 3.3V), Note 6-1 10BASE-T I DD1_3.3V — 41 — mA Full-duplex traffic @ 100% utilization 100BASE-TX I DD2_3.3V — 47 — mA Full-duplex traffic @ 100% utilization EDPD Mode I DD3_3.3V —2 0— m A Ethernet cable disconnected (Reg. 18h.11 = 0) Power-Down Mode I DD4_3.3V —4— m A Software power-down (Reg. 0h.11 = 1) CMOS Level Inputs Input High Voltage V IH 2.0 — — V V DDIO = 3.3V 1.8 — — V V DDIO = 2.5V 1.3 — — V V DDIO = 1.8V Input Low Voltage V IL —— 0 . 8V V DDIO = 3.3V —— 0 . 7V V DDIO = 2.5V —— 0 . 5V V DDIO = 1.8V Input Current |I IN|— — 1 0 µ A V IN = GND ~ VDDIO CMOS Level Outputs Output High Voltage V OH 2.4 — — V V DDIO = 3.3V 2.0 — — V V DDIO = 2.5V 1.5 — — V V DDIO = 1.8V Output Low Voltage V OL —— 0 . 4V V DDIO = 3.3V —— 0 . 4V V DDIO = 2.5V —— 0 . 3V V DDIO = 1.8V Output Tri-State Leakage |I OZ|— — 1 0 µ A — LED Output Output Drive Current I LED — 8 — mA Each LED pin (LED0, LED1) All Pull-Up/Pull-Down Pins (including Strap-In Pins) Internal Pull-Up Resistance pu 30 45 73 k Ω VDDIO = 3.3V 39 61 102 k Ω VDDIO = 2.5V 48 99 178 k Ω VDDIO = 1.8V Internal Pull-Down Resistance pd 26 43 79 k Ω VDDIO = 3.3V 34 59 113 k Ω VDDIO = 2.5V 53 99 200 k Ω VDDIO = 1.8V 100BASE-TX Transmit (measured differentially after 1:1 transformer) Peak Differential Output Voltage VO 0.95 — 1.05 V 100Ω termination across differential output Output Voltage Imbalance V IMB —— 2 % 100Ω termination across differential output Rise/Fall Time t r/tf 3—5n s — Rise/Fall Time Imbalance — 0 — 0.5 ns — Duty Cycle Distortion — — — ±0.25 ns — Overshoot — — — 5 % — Output Jitter — — 0.7 — ns Peak-to-peak

DS00002310A-page 46  2016 Microchip Technology Inc. Note 6-1 Current consumption is for the single 3.3V supply KSZ8051MNL/RNL device only, and includes the transmit driver current and the 1.2V supply voltage (V DD_1.2) that are supplied by the KSZ8051MNL/ RNL. 10BASE-T Transmit (measured differentially after 1:1 transformer) Peak Differential Output Voltage VP 2.2 — 2.8 V 100Ω termination across differential output Jitter Added — — — 3.5 ns Peak-to-peak Rise/Fall Time t r/tf —2 5—n s — 10BASE-T Receive Squelch Threshold V SQ — 400 — mV 5 MHz square wave Transmitter - Drive Setting Reference Voltage of ISET VSET —0 . 6 5— V R ( I SET) = 6.49 kΩ REF_CLK Output

50 Mhz RMII Clock Output

Jitter —— 3 0 0 — p s Peak-to-peak (Applies only to KSZ8051RNL in RMII - 25 MHz Clock Mode)

100 Mbps Mode - Industrial Applications Parameters

Clock Phase Delay – XI Input to MII TXC Output — 1 52 02 5n s XI (25 MHz clock input) to MII TXC (25 MHz clock output) delay, refer- enced to rising edges of both clocks. (Applies only to KSZ8051MNL in MII mode) Link Loss Reaction (Indication) Time tllr —4 . 4— µ s Link loss detected at receive differen- tial inputs to PHY signal indication time for each of the following: 1. For LED mode 00, Speed LED out- put changes from low (100 Mbps) to high (10 Mbps, default state for link- down). 2. For LED mode 01, Link LED output changes from low (link-up) to high (link-down). 3. INTRP pin asserts for link-down status change. TABLE 6-1: ELECTRICAL CHARACTERISTICS (CONTINUED) Parameters Symbol Min. Typ. Max. Units Note

 2016 Microchip Technology Inc. DS00002310A-page 47 KSZ8051MNL/RNL

7.0 TIMING DIAGRAMS

7.1 MII SQE Timing (10BASE-T)

FIGURE 7-1: MII SQE TIMING (10BASE-T) TABLE 7-1: MII SQE TIMING (10BASE-T) PARAMETERS Parameter Description Min. Typ. Max. Units tP TXC period — 400 — ns tWL TXC pulse width low — 200 — ns tWH TXC pulse width high — 200 — ns tSQE COL (SQE) delay after TXEN de-asserted — 2.2 — µs tSQEP COL (SQE) pulse duration — 1.0 — µs tWL tWH tP tSQE tSQEP TXC TXEN COL

DS00002310A-page 48  2016 Microchip Technology Inc.

7.2 MII Transmit Timing (10BASE-T)

FIGURE 7-2: MII TRANSM IT TIMING (10BASE-T) TABLE 7-2: MII TRANSMIT TIMING (10BASE-T) PARAMETERS Parameter Description Min. Typ. Max. Units tP TXC period — 400 — ns tWL TXC pulse width low — 200 — ns tWH TXC pulse width high — 200 — ns tSU1 TXD[3:0] setup to rising edge of TXC 120 — — ns tSU2 TXEN setup to rising edge of TXC 120 — — ns tHD1 TXD[3:0] hold from rising edge of TXC 0 — — ns tHD2 TXEN hold from rising edge of TXC 0 — — ns tCRS1 TXEN high to CRS asserted latency — 600 — ns tCRS2 TXEN low to CRS de-asserted latency — 1.0 — µs CRS TXEN TXD[3:0] TXC tCRS1 tWL tP tHD2 tCRS2 tWH tHD1 tSU2 tSU1

 2016 Microchip Technology Inc. DS00002310A-page 49 KSZ8051MNL/RNL

7.3 MII Receive Timing (10BASE-T)

FIGURE 7-3: MII RECEIVE TIMING (10BASE-T) TABLE 7-3: MII RECEIVE TIMING (10BASE-T) PARAMETERS Parameter Description Min. Typ. Max. Units tP RXC period — 400 — ns tWL RXC pulse width low — 200 — ns tWH RXC pulse width high — 200 — ns tOD (RXDV, RXD[3:0], RXER) output delay from rising edge of RXC —2 0 5— ns tRLAT CRS to (RXDV, RXD[3:0]) latency — 7.2 — µs CRS RXDV RXD[3:0] RXER RXC tRLAT tOD tP tWL tWH

DS00002310A-page 50  2016 Microchip Technology Inc.

7.4 MII Transmit Timing (100BASE-TX)

FIGURE 7-4: MII TRANSMIT TIMING (100BASE-TX) TABLE 7-4: MII TRANSMIT TIMING (100BASE-TX) PARAMETERS Parameter Description Min. Typ. Max. Units tP TXC period — 40 — ns tWL TXC pulse width low — 20 — ns tWH TXC pulse width high — 20 — ns tSU1 TXD[3:0] setup to rising edge of TXC 10 — — ns tSU2 TXEN setup to rising edge of TXC 10 — — ns tHD1 TXD[3:0] hold from rising edge of TXC 0 — — ns tHD2 TXEN hold from rising edge of TXC 0 — — ns tCRS1 TXEN high to CRS asserted latency — 72 — ns tCRS2 TXEN low to CRS de-asserted latency — 72 — ns CRS TXEN TXD[3:0] TXC tCRS1 tWL tP tHD1 tSU1 tCRS2 DATA IN tWH tHD2tSU2

 2016 Microchip Technology Inc. DS00002310A-page 51 KSZ8051MNL/RNL

7.5 MII Receive Timing (100BASE-TX)

FIGURE 7-5: MII RECEIVE TIMING (100BASE-TX) TABLE 7-5: MII RECEIVE TIMING (10BASE-T) PARAMETERS Parameter Description Min. Typ. Max. Units tP RXC period — 40 — ns tWL RXC pulse width low — 20 — ns tWH RXC pulse width high — 20 — ns tOD (RXDV, RXD[3:0], RXER) output delay from rising edge of RXC —2 5— ns tRLAT CRS to (RXDV, RXD[3:0]) latency — 170 — ns CRS RXDV RXD[3:0] RXER RXC tRLAT tOD tP tWL tWH

DS00002310A-page 52  2016 Microchip Technology Inc.

7.6 RMII Timing

Note 7-1 25 MHz input to XI pin, 50 MHz output from REF_CLK pin. Note 7-1 50 MHz input to XI pin. FIGURE 7-6: RMII TIMING - DATA RECEIVED FROM RMII FIGURE 7-7: RMII TIMING - DATA INPUT TO RMII TABLE 7-6: RMII TIMING PARAMETERS - KSZ8051RNL ( Note 7-1) Timing Parameter Description Min. Typ. Max. Units tCYC Clock cycle — 20 — ns t1 Setup time 4 — — ns t2 Hold time 2 — — ns tOD Output delay 7 10 13 ns TABLE 7-7: RMII TIMING PARAMETERS - KSZ8051RNL ( Note 7-1) Timing Parameter Description Min. Typ. Max. Units tCYC Clock cycle — 20 — ns t1 Setup time 4 — — ns t2 Hold time 2 — — ns tOD Output delay 8 11 13 ns tCYC REF_CLK TXEN TXD[1:0] TRANSMIT TIMING tCYC REF_CLK CRS_DV RXD[1:0] RXER tOD RECEIVE TIMING

 2016 Microchip Technology Inc. DS00002310A-page 53 KSZ8051MNL/RNL

7.7 Auto-Negotiation Timing

FIGURE 7-8: AUTO-NEGOTIATION FAST LINK PULSE (FLP) TIMING TABLE 7-8: AUTO-NEGOTIATION FAST LINK PULSE TIMING PARAMETERS Parameter Description Min. Typ. Max. Units tBTB FLP burst to FLP burst 8 16 24 ms tFLPW FLP burst width — 2 — ms tPW Clock/Data pulse width — 100 — ns tCTD Clock pulse to data pulse 55.5 64 69.5 µs tCTC Clock pulse to clock pulse 111 128 139 µs — Number of clock/data pulses per FLP burst 17 — 33 — AUTO -NEGOTIATION FAST LINK PULSE (FLP) TIMING tPW TX+/TX- CLOCK PULSE DATA PULSE CLOCK PULSE tPW tCTD tCTC tFLPW tBTB TX+/TX- DATA PULSE FLP BURST FLP BURST

DS00002310A-page 54  2016 Microchip Technology Inc.

7.8 MDC/MDIO Timing

FIGURE 7-9: MDC/MDIO TIMING TABLE 7-9: MDC/MDIO TIMING PARAMETERS Parameter Description Min. Typ. Max. Units tP MDC period — 400 — ns tMD1 MDIO (PHY input) setup to rising edge of MDC 10 — — ns tMD2 MDIO (PHY input) hold from rising edge of MDC 4 — — ns tMD3 MDIO (PHY output) delay from rising edge of MDC 5 — — ns tMD1 VALID DATA MDIO (PHY INPUT) VALID DATA MDC tMD2 MDIO (PHY OUTPUT) VALID DATA tMD3 tP

 2016 Microchip Technology Inc. DS00002310A-page 55 KSZ8051MNL/RNL

7.9 Power-Up/Reset Timing

The KSZ8051MNL/RNL reset timing requirement is summarized in Figure 7-10 and Table 7-10. The supply voltage (VDDIO and VDDA_3.3) power-up waveform should be monotonic. The 300 µs minimum rise time is from 10% to 90%. For warm reset, the reset (RST#) pin should be asserted low for a minimum of 500 µs. The strap-in pin values are read and updated at the de-assertion of reset. After the de-assertion of reset, wait a minimum of 100 µs before starting programming on the MIIM (MDC/MDIO) inter- face. If the clock source to XI is something other than a crystal, the clock must be present for a minimum of 1 ms prior to the rising edge of RST#. FIGURE 7-10: POWER-UP/RESET TIMING TABLE 7-10: POWER-UP/RESET TIMING PARAMETERS Parameter Description Min. Typ. Max. Units tVR Supply voltage (VDDIO, VDDA_3.3) rise time 300 — — µs tSR Stable supply voltage (VDDIO, VDDA_3.3) to reset high 10 — — ms tCS Configuration setup time 5 — — ns tCH Configuration hold time 5 — — ns tRC Reset to strap-in pin output 6 — — ns SUPPLY VOLTAGES RST# STRAP-IN VALUE STRAP-IN / OUTPUT PIN tVR tSR tCS tCH tRC

DS00002310A-page 56  2016 Microchip Technology Inc.

8.0 RESET CIRCUIT

Figure 8-1 shows a reset circuit recommended for powering up the KSZ8051MNL/RNL if reset is triggered by the power supply. FIGURE 8-1: RECOMMENDED RESET CIRCUIT Figure 8-2 shows a reset circuit recommended for applications w here reset is driven by another device (for example, the CPU or an FPGA). At power-on-reset, R, C, and D1 provide the necessary ramp rise time to reset the KSZ8051MNL/ RNL device. The RST_OUT_N from the CPU/FPGA provides the warm reset after power-up. FIGURE 8-2: RECOMMENDED RESET CIR CUIT FOR CPU/FPGA RESET OUTPUT KSZ8051MNL/ KSZ8051RNL VDDIO D1: 1N4148 R 10K C 10μF RST# KSZ8051MNL/ KSZ8051RNL CPU/FPGA VDDIO C 10μF R 10K RST_OUT_n D1, D2: 1N4148 RST#

 2016 Microchip Technology Inc. DS00002310A-page 57 KSZ8051MNL/RNL

9.0 REFERENCE CIRCUITS — LED STRAP-IN PINS

The pull-up, float, and pull-down reference circuits for the LED1/SPEED and LED0/NWAYEN strap-in pins are shown in Figure 9-1 for 3.3V and 2.5V VDDIO. FIGURE 9-1: REFERENCE CIRCUITS FOR LED STRAP-IN PINS For 1.8V VDDIO, LED indication support is not recommended due to the low voltage. Without the LED indicator, the SPEED and NWAYEN strapping pins are functional with a 4.7 kΩ pull-up to 1.8V VDDIO or float for a value of ‘1’, and with a 1.0 kΩ pull-down to ground for a value of ‘0’. LED PIN VDDIO = 3.3V, 2.5V PULL-UP KSZ8051MNL/ KSZ8051RNL FLOAT PULL-DOWN LED PIN NŸ Ÿ VDDIO = 3.3V, 2.5V KSZ8051MNL/ KSZ8051RNL VDDIO = 3.3V, 2.5V LED PIN KSZ8051MNL/ KSZ8051RNL

DS00002310A-page 58  2016 Microchip Technology Inc.

10.0 REFERENCE CLOCK - CONNECTION AND SELECTION

A crystal or external clock source, such as an oscillator, is used to provide the reference clock for the KSZ8051MNL/ RNL. For the KSZ8051MNL in all operating modes and for the KSZ8051RNL in RMII – 25 MHz Clock Mode, the refer- ence clock is 25 MHz. The reference clock connections to XI (pin 9) and XO (pin 8), and the reference clock selection criteria, are provided in Figure 10-1 and Table 10-1. FIGURE 10-1: 25 MHZ CRYSTAL/OSCILLATOR REFERENCE CLOCK CONNECTION For the KSZ8051RNL in RMII - 50 MHz Clock Mode, the refe rence clock is 50 MHz. The reference clock connections to XI (Pin 9), and the reference clock selection criteria are provided in Figure 10-2 and Table 10-2. TABLE 10-1: 25 MHZ CRYSTAL/REFER ENCE CLOCK SELECTION CRITERIA Characteristics Value Frequency 25 MHz Frequency Tolerance (max.) ±50 ppm FIGURE 10-2: 50 MHZ OSCILLATOR REFERENCE CLOCK CONNECTION TABLE 10-2: 50 MHZ OSCILLATOR/REF ERENCE CLOCK SELECTION CRITERIA Characteristics Value Frequency 50 MHz Frequency Tolerance (max.) ±50 ppm NC XI XO 25MHz OSC ±50ppm XI XO 25MHz XTAL ±50ppm 22pF 22pF NC XI XO 50MHz OSC ±50PPM

 2016 Microchip Technology Inc. DS00002310A-page 59 KSZ8051MNL/RNL

11.0 MAGNETIC - CONNEC TION AND SELECTION

A 1:1 isolation transformer is required at the line interface. Use one with integrated common-mode chokes for designs exceeding FCC requirements. The KSZ8051MNL/RNL design incorporates voltage-mode transmit drivers and on-chip terminations. With the voltage-mode implementation, the transmit drivers supply the common-mode voltages to the two differential pairs. Therefore, the two transformer center tap pins on the KSZ8051MNL/ RNL side should not be connected to any power supply source on the board; instead, the center tap pins should be separated from one another and connected through separate 0.1 µF common-mode capacitors to ground. Separation is required because the common-mode volt- age is different between transmitting and receiving differential pairs. Figure 11-1 shows the typical magnetic interface circuit for the KSZ8051MNL/RNL. FIGURE 11-1: TYPICAL MAGNETIC INTERFACE CIRCUIT Table 11-1 lists recommended magnetic characteristics. TABLE 11-1: MAGNETICS SELECTION CRITERIA Parameter Value Test Conditions Turns Ratio 1 CT : 1 CT — Open-Circuit Inductance (min.) 350 µH 100 mV, 100 kHz, 8 mA Insertion Loss (max.) –1.1 dB 100 kHz to 100 MHz HIPOT (min.) 1500 V RMS — 4 x 75Ÿ 1000pF/2kV RJ-45 CONNECTOR CHASSIS GROUND (2 x 0.1μF) TXP TXM RXP RXM KSZ8051MNL/RNL SIGNAL GROUND

DS00002310A-page 60  2016 Microchip Technology Inc. Table 11-2 is a list of compatible single-port magnetics with separated transformer center tap pins on the PHY chip side that can be used with the KSZ8051MNL/RNL. TABLE 11-2: COMPATIBLE SING LE-PORT 10/100 MAGNETICS Manufacturer Part Number Temperature Range Magnetic + RJ-45 Bel Fuse S558-5999-U7 0°C to 70°C No Bel Fuse SI-46001-F 0°C to 70°C Yes Bel Fuse SI-50170-F 0°C to 70°C Yes Delta LF8505 0°C to 70°C No HALO HFJ11-2450E 0°C to 70°C Yes HALO TG110-E055N5 –40°C to 85°C No LANKom LF-H41S-1 0°C to 70°C No Pulse H1102 0°C to 70°C No Pulse H1260 0°C to 70°C No Pulse HX1188 –40°C to 85°C No Pulse J00-0014 0°C to 70°C Yes Pulse JX0011D21NL –40°C to 85°C Yes TDK TLA-6T718A 0°C to 70°C Yes Transpower HB726 0°C to 70°C No Wurth/Midcom 000-7090-37R-LF1 –40°C to 85°C No

 2016 Microchip Technology Inc. DS00002310A-page 61 KSZ8051MNL/RNL

12.0 PACKAGE OUTLINE

FIGURE 12-1: 32-LEAD QFN 5 MM X 5 MM PACKAGE Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging.

DS00002310A-page 62  2016 Microchip Technology Inc. APPENDIX A: DATA SHEET REVISION HISTORY TABLE A-1: REVISION HISTORY Revision Section/Figure/Entry Correction DS00002310A (11-15-16) Converted Micrel data sheet KSZ8051MNL/RNL to Microchip DS00002310A. Minor text changes throughout. This document combines Micrel’s auto- motive-qualified KSZ8051MNLU/RNLU and KSZ8051MNLV/RNLV data sheets. It also replaces the non-automotive KSZ8051MNL/RNL, which has been EoL. Table 3-3 Removed references to TXC and RXC pins. LinkMD® Cable Diagnostic section Added usage example.

 2016 Microchip Technology Inc. DS00002310A-page 63 KSZ8051MNL/RNL THE MICROCHIP WEB SITE Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site con- tains the following information:

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• Field Application Engineer (FAE)
• Technical Support Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this docu- ment. Technical support is available through the web site at: http://microchip.com/support

DS00002310A-page 64  2016 Microchip Technology Inc. PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. Device: KSZ8051 Interface: M = MII R = RMII Package: N = 32-pin QFN Supply Voltage: L = Single 3.3V Supply Temperature: U = –40C to +85C (Automotive Grade 3) UB = –40C to +85C (Automotive Grade 3) V = –40C to +105C (Automotive Grade 2) Media Type: blank = Tray TR = Tape & Reel Automotive Option: VAO = Automotive Option Examples: a) KSZ8051MNLU MII Interface 32-pin QFN Single 3.3V Supply Automotive Grade 3 Temperature Tray b) KSZ8051MNLV MII Interface 32-pin QFN Single 3.3V Supply Automotive Grade 2 Temperature Tray c) KSZ8051RNLUB-VAO ( Note 1) RMII Interface 32-pin QFN Single 3.3V Supply Automotive Grade 3 Temperature Tray, Automotive Option d) KSZ8051RNLU ( Note 1) RMII Interface 32-pin QFN Single 3.3V Supply Automotive Grade 3 Temperature Tray e) KSZ8051MNLU-TR MII Interface 32-pin QFN Single 3.3V Supply Automotive Grade 3 Temperature Tape & Reel f) KSZ8051MNLV-TR MII Interface 32-pin QFN Single 3.3V Supply Automotive Grade 2 Temperature Tape & Reel g) KSZ8051RNLUB-TR-VAO ( Note 1) RMII Interface 32-pin QFN Single 3.3V Supply Automotive Grade 3 Temperature Tape & Reel, Automotive Option h) KSZ8051RNLU-TR ( Note 1) RMII Interface 32-pin QFN Single 3.3V Supply Automotive Grade 3 Temperature Tape & Reel PART NO. X X PackageInterfaceDevice XX Temperature X Special Attribute XX Media Note 1: KSZ8051RNLUB corrects an erratum in the KSZ8051RNLU (see Module #1 in the KSZ8051 Errata document). KSZ8051RNLUB is recommended for all new designs and is a 100% functional and pin equivalent replacement for KSZ8051RNLU. Type XXX Automotive Option

 2016 Microchip Technology Inc. DS00002310A-page 65 Information contained in this publication regarding device applications and the like is provided on ly for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY , PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Micro- chip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless otherwise stated. Trademarks The Microchip name and logo, the Microchip logo, AnyRate, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KeeLoq, KeeLoq logo, Kleer, LANCheck, LINK MD, MediaLB, MOST, MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC, SST, SST Logo, SuperFlash and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. ClockWorks, The Embedded Control Solutions Company, ETHERSYNCH, Hyper Speed Control, HyperLight Load, IntelliMOS, mTouch, Precision Edge, and QUIET-WIRE are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP , Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PureSilicon, RightTouch logo, REAL ICE, Ripple Blocker, Serial Quad I/O, SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. GestIC is a registered trademarks of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2016, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. ISBN: 978-1-5224-1080-5 Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification cont ained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the mo st secure families of its kind on the market today, when used in the intended manner and under normal conditions.
• There are dishonest and possibly illegal meth ods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC ® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV == ISO/TS 16949 ==

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