KSZ8041TL_09 MICREL | Alldatasheet
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10Base-T/100Base-TX/100Base-FX Physical Layer Transceiver Data Sheet Rev. 1.2 LinkMD is a registered trademark of Micrel, Inc. Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com December 2009 M9999-120909-1.2 General Description The KSZ8041TL is a single supply 10Base-T/100Base-TX Physical Layer Transceiver, which provides MII/RMII/SMII interfaces to transmit and receive data. It utilizes a unique mixed-signal design to extend signaling distance while reducing power consumption. HP Auto MDI/MDI-X provides the most robust solution for eliminating the need to differentiate between crossover and straight-through cables. Micrel LinkMD ® TDR-based cable diagnostics permit identification of faulty copper cabling. The KSZ8041TL represents a new level of features and performance and is an ideal choice of physical layer transceiver for 10Base-T/100Base-TX applications. The KSZ8041FTL has all the identical rich features of the KSZ8041TL plus 100Base-FX support for fiber and media converter applications. The KSZ8041MLL is the basic 10Base-T/100Base-TX Physical Layer Transceiver version with MII support. The KSZ8041TL and KSZ8041FTL are available in 48-pin, lead-free TQFP packages. The KSZ8041MLL is provided in the 48-pin, lead-free LQFP package (See Ordering Information). Data sheets and support documentation can be found on Micrel’s web site at: www.micrel.com. Functional Diagram KSZ8041TL/FTL KSZ8041MLL
Micrel, Inc. KSZ8041TL/FTL/MLL December 2009 2 M9999-120909-1.2
Features
/g120 Single-chip 10Base-T/100Base-TX physical layer solution /g120 Fully compliant to IEEE 802.3u Standard /g120 Low power CMOS design, power consumption of <180mW /g120 HP auto MDI/MDI-X for reliable detection and correction for straight-through and crossover cables with disable and enable option /g120 Robust operation over standard cables /g120 LinkMD ® TDR-based cable diagnostics for identification of faulty copper cabling /g120 Fiber support: 100Base-FX (KSZ8041FTL only), /g120 Back-to-Back mode support for 100Mbps repeater or media converter /g120 MII interface support /g120 RMII interface support with external 50MHz system clock (KSZ8041TL/FTL only) /g120 SMII interface support with external 125MHz system clock and 12.5MHz sync clock from MAC (KSZ8041TL/FTL only) /g120 MIIM (MDC/MDIO) management bus to 12.5MHz for rapid PHY register configuration /g120 Interrupt pin option /g120 Programmable LED outputs for link, activity and speed /g120 Power down and power saving modes /g120 Single power supply (3.3V) /g120 Built-in 1.8V regulator for core /g120 Available packages: 48-pin LQFP (KSZ8041MLL) 48-pin TQFP (KSZ8041TL/FTL)
Applications
/g120 Printer /g120 LOM /g120 Game Console /g120 IPTV /g120 IP Phone /g120 IP Set-top Box /g120 Media Converter
Ordering Information
(marking) Ordering Number Temp. Range Package Lead Finish
Description
KSZ8041MLL KSZ8041MLL 0°C to 70°C 48-Pin LQFP Pb-Free MII, 10/100 Copper, C-Temp, 48-LQFP KSZ8041TL KSZ8041TL 0°C to 70°C 48-Pin TQFP Pb-Free MII / RMII, 10/100 Copper, C-Temp, 48-TQFP KSZ8041TLI (1) KSZ8041TLI -40°C to 85°C 48-Pin TQFP Pb-Free MII / RMII, 10/100 Copper, I-Temp, 48-TQFP KSZ8041FTL KSZ8041FTL 0°C to 70°C 48-Pin TQFP Pb-Fre e MII / RMII, 100Base-FX Fiber, C-Temp, 48-TQFP KSZ8041FTLI (1) KSZ8041FTLI -40°C to 85°C 48-Pin TQFP Pb-Free MII / RMII, 100Base-FX Fiber, I-Temp, 48-TQFP KSZ8041TL (1) KSZ8041TL-S 0°C to 70°C 48-Pin TQFP Pb-Free SMII, 10/100 Copper, C-Temp, 48-TQFP KSZ8041TLI (1) KSZ8041TLI-S -40°C to 85°C 48-Pin TQFP Pb-Free SMII, 10/100 Copper, I-Temp, 48-TQFP KSZ8041FTL (1) KSZ8041FTL-S 0°C to 70°C 48-Pin TQFP Pb-Free SMII, 100Base-FX Fiber, C-Temp, 48-TQFP KSZ8041FTLI (1) KSZ8041FTLI-S -40°C to 85°C 48-Pin TQFP Pb-Free SMII, 100Base-FX Fiber, I-Temp, 48-TQFP Note: 1. Contact factory for lead time.
Micrel, Inc. KSZ8041TL/FTL/MLL December 2009 3 M9999-120909-1.2
Revision History
Revision Date Summary of Changes 1.0 12/21/06 Data sheet created. 1.1 4/27/07 Added maximum MDC clock speed. Added 40K +/-30% to note 1 of Pin Description and Strapping Options tables for internal pull-ups/pull- downs. Changed Model Number in Register 3h – PHY Identifier 2. Changed polarity (swapped definition) of DUPLEX strapping pin. Removed DUPLEX strapping pin update to Register 4h – Auto-Negotiation Advertisement bits [8, 6]. Added Back-to-Back mode for KSZ8041TL. Added Symbol Error to MII/RMII Receive Error description and Register 15h – RXER Counter. Added a 100pF capacitor on REXT (pin 16) in Pin Description table. 1.2 12/9/09 Updated Ordering Information. Changed MDIO hold time (min) from 10ns to 4ns. Added thermal resistance (/g455JC). Added chip maximum current consumption. Added LED drive current. Renamed Register 3h bits [3:0] to “manufacturer’s revision number” and changed default value to “Indicates silicon revision.” Updated RMII output delay for CRSDV and RXD[1:0] output pins. Added support for Asymmetric PAUSE in register 4h bit [11]. Added control bits for 100Base-TX preamble restore (register 14h bit [7]) and 10Base-T preamble restore (register 14h bit [6]). Changed strapping pin definition for CONFIG[2:0] = 100 from “PCS Loopback” to “MII 100Mbps Preamble Restore.” Corrected MII timing for t RLAT, tCRS1, tCRS2. Added SMII timing. Added KSZ8041MLL device and updated entire data sheet accordingly. Added 48-Pin LQFP package information.
Micrel, Inc. KSZ8041TL/FTL/MLL December 2009 5 M9999-120909-1.2
Micrel, Inc. KSZ8041TL/FTL/MLL December 2009 8 M9999-120909-1.2 Pin Configuration – KSZ8041TL NC NC TXC RST# INTRP REXT GND RXER / RX_ER / ISO GND VDD_1.8 GND GND GND GND XO VDDA_3.3 NC TXD1 / TXD[1] / SYNC TXD0 / TXD[0] / TX TXEN / TX_EN LED1 / SPEED LED0 / NWAYEN CRS / CONFIG1 NC 13 14 16 17 4142434445464748 RX+ TX- RX-9 GND TXD3 TXD2 GND COL / CONFIG0 37383940 RXC VDDIO_3.3 VDDIO_3.3 RXDV / CRSDV / CONFIG2 RXD2 / PHYAD1 RXD1 / RXD[1] / PHYAD2 RXD0 / RXD[0] / RX DUPLEX 21 22 23 MDIO MDC RXD3 / PHYAD0 18 19 20 XI / REFCLK / CLOCK TX+12 VDDA_1.8 VDDA_1.8 V1.8_OUT VDDA_3.3 KSZ8041TL 48-Pin TQFP
Micrel, Inc. KSZ8041TL/FTL/MLL December 2009 9 M9999-120909-1.2 Pin Configuration – KSZ8041FTL NC NC TXC RST# INTRP REXT GND RXER / RX_ER / ISO GND VDD_1.8 GND GND GND GND XO VDDA_3.3 FXSD / FXEN TXD1 / TXD[1] / SYNC TXD0 / TXD[0] / TX TXEN / TX_EN LED1 / SPEED / no FEF LED0 / NWAYEN CRS / CONFIG1 NC 13 14 16 17 4142434445464748 RX+ TX- RX-9 GND TXD3 TXD2 GND COL / CONFIG0 37383940 RXC VDDIO_3.3 VDDIO_3.3 RXDV / CRSDV / CONFIG2 RXD2 / PHYAD1 RXD1 / RXD[1] / PHYAD2 RXD0 / RXD[0] / RX DUPLEX 21 22 23 MDIO MDC RXD3 / PHYAD0 18 19 20 XI / REFCLK / CLOCK TX+12 VDDA_1.8 VDDA_1.8 V1.8_OUT VDDA_3.3 KSZ8041FTL 48-Pin TQFP
Micrel, Inc. KSZ8041TL/FTL/MLL December 2009 10 M9999-120909-1.2 Pin Description- KSZ8041TL/FTL Pin Number Pin Name Type(1) Pin Function
1 GND Gnd Ground
2 GND Gnd Ground
3 GND Gnd Ground
4 VDDA_1.8 P 1.8V analog V DD 5 VDDA_1.8 P 1.8V analog V DD 6 V1.8_OUT P 1.8V output voltage from chip 7 VDDA_3.3 P 3.3V analog V DD 8 VDDA_3.3 P 3.3V analog V DD
9 RX- I/O Physical receive or transmit signal (- differential)
10 RX+ I/O Physical receive or transmit signal (+ differential)
11 TX- I/O Physical transmit or receive signal (- differential)
12 TX+ I/O Physical transmit or receive signal (+ differential)
13 GND Gnd Ground
14 XO O Crystal feedback
This pin is used only in MII mode when a 25MHz crystal is used. This pin is a no connect if oscillator or external clock source is used, or if RMII mode or SMII mode is selected.
15 XI /
I Crystal / Oscillator / External Clock Input MII Mode: 25MHz +/-50ppm (crystal, oscillator, or external clock) RMII Mode: 50MHz +/-50ppm (oscillator, or external clock only) SMII Mode: 125MHz +/-100ppm (oscillator, or external clock only)
16 REXT I/O Set physical transmit output current
Connect a 6.49K/g58 resistor in parallel with a 100pF capacitor to ground on this pin. See KSZ8041TL-FTL reference schematics.
17 GND Gnd Ground
18 MDIO I/O Management Interface (MII) Data I/O
This pin requires an external 4.7K/g58 pull-up resistor.
19 MDC I Management Interface (MII) Clock Input
This pin is synchronous to the MDIO data interface.
20 RXD3 /
Ipu/O MII Mode: Receive Data Output[3] (2) / Config. Mode: The pull-up/pull-down value is latched as PHYADDR[0] during power-up / reset. See “Strapping Options” section for details.
21 RXD2 /
Ipd/O MII Mode: Receive Data Output[2] (2) / Config. Mode: The pull-up/pull-down value is latched as PHYADDR[1] during power-up / reset. See “Strapping Options” section for details.
22 RXD1 /
RXD[1] / PHYAD2 Ipd/O MII Mode: Receive Data Output[1] (2) / RMII Mode: Receive Data Output[1] (3) / Config. Mode: The pull-up/pull-down value is latched as PHYADDR[2] during power-up / reset. See “Strapping Options” section for details.
Micrel, Inc. KSZ8041TL/FTL/MLL December 2009 11 M9999-120909-1.2 Pin Number Pin Name Type(1) Pin Function
23 RXD0 /
RXD[0] / RX DUPLEX Ipu/O MII Mode: Receive Data Output[0] (2) / RMII Mode: Receive Data Output[0] (3) / SMII Mode: Receive Data and Control (4) / Config. Mode: Latched as DUPLEX (register 0h, bit 8) during power-up / reset. See “Strapping Options” section for details.
24 GND Gnd Ground
25 VDDIO_3.3 P 3.3V digital V DD 26 VDDIO_3.3 P 3.3V digital V DD
27 RXDV /
Ipd/O MII Mode: Receive Data Valid Output / RMII Mode: Carrier Sense/Receive Data Valid Output / Config. Mode: The pull-up/pull-down value is latched as CONFIG2 during power-up / reset. See “Strapping Options” section for details. 28 RXC O MII Mode: Receive Clock Output.
29 RXER /
RX_ER / ISO Ipd/O MII Mode: Receive Error Output / RMII Mode: Receive Error Output / Config. Mode: The pull-up/pull-down value is latched as ISOLATE during power-up / reset. See “Strapping Options” section for details.
30 GND Gnd Ground
31 VDD_1.8 P 1.8V digital V DD
32 INTRP Opu Interrupt Output: Programmable Interrupt Output
Register 1Bh is the Interrupt Control/Status Register for programming the interrupt conditions and reading the interrupt status. Register 1Fh bit 9 sets the interrupt output to active low (default) or active high.
33 TXC I/O MII Mode: Transmit Clock Output
MII Back-to Back Mode: Transmit Clock Input
34 TXEN /
TX_EN I MII Mode: Transmit Enable Input / RMII Mode: Transmit Enable Input
35 TXD0 /
TXD[0] / TX I MII Mode: Transmit Data Input[0] (5) / RMII Mode: Transmit Data Input[0] (6) / SMII Mode: Transmit Data and Control (7)
36 TXD1 /
TXD[1] / SYNC I MII Mode: Transmit Data Input[1] (5) / RMII Mode: Transmit Data Input[1] (6) / SMII Mode: SYNC Clock Input
37 GND Gnd Ground
38 TXD2 I MII Mode: Transmit Data Input[2] (5) /
39 TXD3 I MII Mode: Transmit Data Input[3] (5) /
40 COL /
Ipd/O MII Mode: Collision Detect Output / Config. Mode: The pull-up/pull-down value is latched as CONFIG0 during power-up / reset. See “Strapping Options” section for details.
41 CRS /
Ipd/O MII Mode: Carrier Sense Output / Config. Mode: The pull-up/pull-down value is latched as CONFIG1 during power-up / reset. See “Strapping Options” section for details.
Micrel, Inc. KSZ8041TL/FTL/MLL December 2009 12 M9999-120909-1.2 Pin Number Pin Name Type(1) Pin Function (KSZ8041TL) LED0 / NWAYEN Ipu/O LED Output: Programmable LED0 Output / Config. Mode: Latched as Auto-Negotiati on Enable (register 0h, bit 12) during power-up / reset. See “Strapping Options” section for details. The LED0 pin is programmable via register 1Eh bits [15:14], and is defined as follows. LED mode = [00] Link/Activity Pin State LED Definition No Link H OFF Link L ON Activity Toggle Blinking LED mode = [01] Link Pin State LED Definition No Link H OFF Link L ON LED mode = [10] Reserved LED mode = [11] Reserved (KSZ8041FTL) LED0 / NWAYEN Ipu/O LED Output: Programmable LED0 Output / Config. Mode: If copper mode (FXEN= 0), latched as Auto-Negotiation Enable (register 0h, bit 12) during power-up / reset. If fiber mode (FXEN=1), this pin configuration is always strapped to disable Auto-Negotiation. See “Strapping Options” section for details. The LED0 pin is programmable via register 1Eh bits [15:14], and is defined as follows. LED mode = [00] Link/Activity Pin State LED Definition No Link H OFF Link L ON Activity Toggle Blinking LED mode = [01] Link Pin State LED Definition No Link H OFF Link L ON LED mode = [10] Reserved LED mode = [11] Reserved
Micrel, Inc. KSZ8041TL/FTL/MLL December 2009 13 M9999-120909-1.2 Pin Number Pin Name Type(1) Pin Function (KSZ8041TL) LED1 / SPEED Ipu/O LED Output: Programmable LED1 Output / Config. Mode: Latched as SPEED (register 0h, bit 13) during power-up / reset. See “Strapping Options” section for details. The LED1 pin is programmable via register 1Eh bits [15:14], and is defined as follows. LED mode = [00] Speed Pin State LED Definition 10BT H OFF 100BT L ON LED mode = [01] Activity Pin State LED Definition No Activity H OFF Activity Toggle Blinking LED mode = [10] Reserved LED mode = [11] Reserved (KSZ8041FTL) LED1 / SPEED / no FEF Ipu/O LED Output: Programmable LED1 Output / Config. Mode: If copper mode (FXEN=0), latched as SPEED (register 0h, bit 13) during power-up / reset. If fiber mode (FXEN=1), latched as no FEF (no Far-End Fault) during power-up / reset. See “Strapping Options” section for details. The LED1 pin is programmable via register 1Eh bits [15:14], and is defined as follows. LED mode = [00] Speed Pin State LED Definition 10BT H OFF 100BT L ON LED mode = [01] Activity Pin State LED Definition No Activity H OFF Activity Toggle Blinking LED mode = [10] Reserved LED mode = [11] Reserved
44 NC - No connect
45 NC - No connect
46 NC - No connect
Micrel, Inc. KSZ8041TL/FTL/MLL December 2009 14 M9999-120909-1.2 Pin Number Pin Name Type(1) Pin Function
47 RST# I Chip Reset (active low)
(KSZ8041TL) NC - No connect (KSZ8041FTL) FXSD / FXEN Ipd FXSD: Signal Detect for 100Base-FX fiber mode FXEN: Fiber Enable for 100Base-FX fiber mode If FXEN=0, fiber mode is disabled. PHY is in copper mode. The default is “0”. See “100Base-FX Operation” section for details. Notes: 1. P = Power supply. Gnd = Ground. I = Input. O = Output. I/O = Bi-directional. Ipd = Input with internal pull-down (40K +/-30%). Ipu = Input with internal pull-up (40K +/-30%). Opu = Output with internal pull-up (40K +/-30%). Ipu/O = Input with internal pull-up (40K +/-30%) during power-up/reset; output pin otherwise. Ipd/O = Input with internal pull-down (40K +/-30%) during power-up/reset; output pin otherwise. RXD[3..0] is invalid when RXDV is de-asserted. 3. RMII Rx Mode: The RXD[1:0] bits are synchronous with REF_CLK. For each clock period in which CRS_DV is asserted, two bits of recovered data are sent from the PHY. 4. SMII Rx Mode: Receive data and control information are sent in 10 bit segments. In 100MBit mode, each segment represents a new byte of data. In 10MBit mode, each segment is repeated ten times; therefore, every ten segments represent a new byte of data. The MAC can sample any one of every 10 segments in 10MBit mode. the MII. TXD[3..0] has no effect when TXEN is de-asserted. 6. RMII Tx Mode: The TXD[1:0] bits are synchronous with REF_CLK. For each clock period in which TX_EN is asserted, two bits o f data are received by the PHY from the MAC. 7. SMII Tx Mode: Transmit data and control information are received in 10 bit segments. In 100MBit mode, each segment represe nts a new byte of data. In 10MBit mode, each segment is repeated ten times; therefore, every ten segments represent a new byte of data. The PHY can sample any one of every 10 segments in 10MBit mode.
Micrel, Inc. KSZ8041TL/FTL/MLL December 2009 15 M9999-120909-1.2 Strapping Options- KSZ8041TL/FTL Pin Number Pin Name Type(1) Pin Function PHYAD2 PHYAD1 PHYAD0 Ipd/O Ipd/O Ipu/O The PHY Address is latched at power-up / reset and is configurable to any value from 1 to 7. The default PHY Address is 00001. PHY Address bits [4:3] are always set to ‘00’. CONFIG2 CONFIG1 CONFIG0 Ipd/O Ipd/O Ipd/O The CONFIG[2:0] strap-in pins are latched at power-up / reset and are defined as follows: CONFIG[2:0] Mode
000 MII (default)
001 RMII
010 SMII
011 Reserved – not used
100 MII 100Mbps Preamble Restore
101 RMII back-to-back
110 MII back-to-back
111 Reserved – not used
29 ISO Ipd/O ISOLATE mode
Pull-up = Enable Pull-down (default) = Disable During power-up / reset, this pin value is latched into register 0h bit 10. (KSZ8041TL) SPEED Ipu/O SPEED mode Pull-up (default) = 100Mbps Pull-down = 10Mbps During power-up / reset, this pin value is latched into register 0h bit 13 as the Speed Select, and also is latched into register 4h (Auto-Negotiation Advertisement) as the Speed capability support. SPEED / If copper mode (FXEN=0), pin strap-in is SPEED mode. Pull-up (default) = 100Mbps Pull-down = 10Mbps During power-up / reset, this pin value is latched into register 0h bit 13 as the Speed Select, and also is latched into register 4h (Auto-Negotiation Advertisement) as the Speed capability support. (KSZ8041FTL) no FEF Ipu/O If fiber mode (FXEN=1), pin strap-in is no FEF. Pull-up (default) = Enable Far-End Fault Pull-down = Disable Far-End Fault This pin value is latched during power-up / reset.
Micrel, Inc. KSZ8041TL/FTL/MLL December 2009 16 M9999-120909-1.2 Pin Number Pin Name Type(1) Pin Function
23 DUPLEX Ipu/O DUPLEX mode
Pull-up (default) = Half Duplex Pull-down = Full Duplex During power-up / reset, this pin value is latched into register 0h bit 8 as the Duplex Mode. (KSZ8041TL) NWAYEN Ipu/O Nway Auto-Negotiation Enable Pull-up (default) = Enable Auto-Negotiation Pull-down = Disable Auto-Negotiation During power-up / reset, this pin value is latched into register 0h bit 12. If copper mode (FXEN=0), pin strap-in is Nway Auto-Negotiation Enable. Pull-up (default) = Enable Auto-Negotiation Pull-down = Disable Auto-Negotiation During power-up / reset, this pin value is latched into register 0h bit 12. (KSZ8041FTL) NWAYEN Ipu/O If fiber mode (FXEN=1), this pin configuration is always strapped to disable Auto- Negotiation. Note: 1. Ipu/O = Input with internal pull-up (40K +/-30%) during power-up/reset; output pin otherwise. Ipd/O = Input with internal pull-down (40K +/-30%) during power-up/reset; output pin otherwise. Pin strap-ins are latched during power-up or reset. In some systems, the MAC receive input pins may drive high during power-up or reset, and consequently cause the PHY strap-in pins on the MII/RMII/SMII signals to be latched high. In this case, it is recommended to add 1K pull-downs on these PHY strap-in pins to ensure the PHY does not strap-in to ISOLATE mode, or is not configured with an incorrect PHY Address.
Micrel, Inc. KSZ8041TL/FTL/MLL December 2009 17 M9999-120909-1.2 Pin Configuration –KSZ8041MLL NC NC TXC RST# INTRP REXT GND RXER / ISO GND VDD_1.8 GND GND GND GND XO VDDA_3.3 NC TXD1 TXD0 TXEN LED1 / SPEED LED0 / NWAYEN CRS / CONFIG1 NC 13 14 16 17 4142434445464748 RX+ TX- RX-9 GND TXD3 TXD2 GND COL / CONFIG0 37383940 RXC VDDIO_3.3 VDDIO_3.3 RXDV / CONFIG2 RXD2 / PHYAD1 RXD1 / PHYAD2 RXD0 / DUPLEX 21 22 23 MDIO MDC RXD3 / PHYAD0 18 19 20 XI TX+12 VDDA_1.8 VDDA_1.8 V1.8_OUT VDDA_3.3 KSZ8041MLL 48-Pin LQFP
Micrel, Inc. KSZ8041TL/FTL/MLL December 2009 18 M9999-120909-1.2 Pin Description– KSZ8041MLL Pin Number Pin Name Type(1) Pin Function 4 VDDA_1.8 P 1.8V analog V DD 5 VDDA_1.8 P 1.8V analog V DD 6 V1.8_OUT P 1.8V output voltage from chip 7 VDDA_3.3 P 3.3V analog V DD 8 VDDA_3.3 P 3.3V analog V DD This pin is used only when a 25 MHz crystal is used. This pin is a no connect if oscillator or external clock source is used.
15 XI I Crystal / Oscillator / External Clock Input
Connect a 6.49K/g159 resistor in parallel with a 100pF capacitor to ground on this pin. See KSZ8041MLL reference schematic. This pin requires an external 4.7K/g159pull-up resistor. This pin is synchronous to the MDIO data interface. Ipu/O MII Mode: Receive Data Output[3] (2) / Config. Mode: The pull-up/pull-down value is latched as PHYADDR[0] during power-up / reset. See “Strapping Options” section for details. Ipd/O MII Mode: Receive Data Output[2] (2) / Config. Mode: The pull-up/pull-down value is latched as PHYADDR[1] during power-up / reset. See “Strapping Options” section for details. Ipd/O MII Mode: Receive Data Output[1] (2) / Config. Mode: The pull-up/pull-down value is latched as PHYADDR[2] during power-up / reset. See “Strapping Options” section for details. Ipu/O MII Mode: Receive Data Output[0] (2) / Config Mode: Latched as DUPLEX (register 0h, bit 8) during power-up / reset. See “Strapping Options” section for details. 25 VDDIO_3.3 P 3.3V digital V DD 26 VDDIO_3.3 P 3.3V digital V DD
Micrel, Inc. KSZ8041TL/FTL/MLL December 2009 19 M9999-120909-1.2 Pin Number Pin Name Type(1) Pin Function Ipd/O MII Mode: Receive Data Valid Output / Config. Mode: The pull-up/pull-down value is latched as CONFIG2 during power-up / reset. See “Strapping Options” section for details.
28 RXC O MII Receive Clock Output
Ipd/O MII Mode: Receive Error Output / Config. Mode: The pull-up/pull-down value is latched as ISOLATE during power-up / reset. See “Strapping Options” section for details. 31 VDD_1.8 P 1.8V digital V DD Register 1Bh is the Interrupt Control/Status Register for programming the interrupt conditions and reading the interrupt status. Register 1Fh bit 9 sets the interrupt output to active low (default) or active high.
33 TXC I/O MII Transmit Clock Output
34 TXEN I MII Transmit Enable Input
35 TXD0 I MII Transmit Data Input0
36 TXD1 I MII Transmit Data Input1
38 TXD2 I MII Transmit Data Input2 /
39 TXD3 I MII Transmit Data Input3 /
Ipd/O MII Mode: Collision Detect Output / Config. Mode: The pull-up/pull-down value is latched as CONFIG0 during power-up / reset. See “Strapping Options” section for details. Ipd/O MII Mode: Carrier Sense Output / Config. Mode: The pull-up/pull-down value is latched as CONFIG1 during power-up / reset. See “Strapping Options” section for details.
42 LED0 /
Ipu/O LED Output: Programmable LED0 Output / Config. Mode: Latched as Auto-Negotiati on Enable (register 0h, bit 12) during power-up / reset. See “Strapping Options” section for details. The LED0 pin is programmable via register 1Eh bits [15:14], and is defined as follows. LED mode = [00] Link/Activity Pin State LED Definition No Link H OFF Link L ON Activity Toggle Blinking LED mode = [01] Link Pin State LED Definition No Link H OFF Link L ON LED mode = [10] Reserved LED mode = [11] Reserved
Micrel, Inc. KSZ8041TL/FTL/MLL December 2009 20 M9999-120909-1.2 Pin Number Pin Name Type(1) Pin Function
43 LED1 /
Ipu/O LED Output: Programmable LED1 Output / Config. Mode: Latched as SPEED (register 0h, bit 13) during power-up / reset. See “Strapping Options” section for details. The LED1 pin is programmable via register 1Eh bits [15:14], and is defined as follows. LED mode = [00] Speed Pin State LED Definition 10BT H OFF 100BT L ON LED mode = [01] Activity Pin State LED Definition No Activity H OFF Activity Toggle Blinking LED mode = [10] Reserved LED mode = [11] Reserved
48 NC - No connect
Notes: 1. P = Power supply. Gnd = Ground. I = Input. O = Output. I/O = Bi-directional. Ipd = Input with internal pull-down (40K +/-30%). Ipu = Input with internal pull-up (40K +/-30%). Opu = Output with internal pull-up (40K +/-30%). Ipu/O = Input with internal pull-up (40K +/-30%) during power-up/reset; output pin otherwise. Ipd/O = Input with internal pull-down (40K +/-30%) during power-up/reset; output pin otherwise. RXD[3..0] is invalid when RXDV is de-asserted. the MII. TXD[3..0] has no effect when TXEN is de-asserted.
Micrel, Inc. KSZ8041TL/FTL/MLL December 2009 21 M9999-120909-1.2 Strapping Options – KSZ8041MLL Pin Number Pin Name Type(1) Pin Function PHYAD2 PHYAD1 PHYAD0 Ipd/O Ipd/O Ipu/O The PHY Address is latched at power-up / reset and is configurable to any value from 1 to 7. The default PHY Address is 00001. PHY Address bits [4:3] are always set to ‘00’. CONFIG2 CONFIG1 CONFIG0 Ipd/O Ipd/O Ipd/O The CONFIG[2:0] strap-in pins are latched at power-up / reset and are defined as follows: CONFIG[2:0] Mode
001 Reserved – not used
010 Reserved – not used
101 Reserved – not used
Pull-up = Enable Pull-down (default) = Disable During power-up / reset, this pin value is latched into register 0h bit 10.
43 SPEED Ipu/O SPEED mode
Pull-up (default) = 100Mbps Pull-down = 10Mbps During power-up / reset, this pin value is latched into register 0h bit 13 as the Speed Select, and also is latched into register 4h (Auto-Negotiation Advertisement) as the Speed capability support. Pull-up (default) = Half Duplex Pull-down = Full Duplex During power-up / reset, this pin value is latched into register 0h bit 8 as the Duplex Mode.
42 NWAYEN Ipu/O Nway Auto-Negotiation Enable
Pull-up (default) = Enable Auto-Negotiation Pull-down = Disable Auto-Negotiation During power-up / reset, this pin value is latched into register 0h bit 12. Note: 1. Ipu/O = Input with internal pull-up (40K +/-30%) during power-up/reset; output pin otherwise. Ipd/O = Input with internal pull-down (40K +/-30%) during power-up/reset; output pin otherwise. Pin strap-ins are latched during power-up or reset. In some systems, the MAC receive input pins may drive high during power-up or reset, and consequently ca use the PHY strap-in pins on the MII signals to be latched high. In this case, it is recommended to add 1K pull-downs on these PHY strap-in pins to ensure the PHY does not strap-in to ISOLATE mode, or is not configured with an incorrect PHY Address.
Micrel, Inc. KSZ8041TL/FTL/MLL December 2009 22 M9999-120909-1.2 Functional Description The KSZ8041TL is a single 3.3V supply Fast Ethernet transceiver. It is fully compliant with the IEEE 802.3u specification. On the media side, the KSZ8041TL supports 10Base-T and 100Base-TX with HP auto MDI/MDI-X for reliable detection of and correction for straight-through and crossover cables. The KSZ8041TL offers a choice of MII, RMII, or SMII data interface connection to a MAC processor. The MII management bus option gives the MAC processor complete access to the KSZ8041TL control and status registers. Additionally, an interrupt pin eliminates the need for the processor to poll for PHY status change. Physical signal transmission and reception are enhanced through the use of patented analog circuitries that make the design more efficient and allow for lower power consumption and smaller chip die size. The KSZ8041FTL has all the identical rich features of the KSZ8041TL plus 100Base-FX fiber support. The KSZ8041MLL is the basic 10Base-T/100Base-TX copper version with MII support. 100Base-TX Transmit The 100Base-TX transmit function performs para llel-to-serial conversion, 4B/5B coding, scrambling, NRZ-to-NRZI conversion, and MLT3 encoding and transmission. The circuitry starts with a parallel-to-serial conversion, which converts the MII data from the MAC into a 125MHz serial bit stream. The data and control stream is then converted into 4B/5B coding, followed by a scrambler. The serialized data is further converted from NRZ-to-NRZI format, and then transmitted in MLT3 current output. The output current is set by an external 6.49 K /g58 1% resistor for the 1:1 transformer ratio. It has typical rise/fall times of 4 ns and complies with the ANSI TP-PMD standard regarding amplitude balance, overshoot and timing jitter. The wave- shaped 10Base-T output drivers are also incorporated into the 100Base-TX drivers. 100Base-TX Receive The 100Base-TX receiver function performs adaptive equalization, DC restoration, MLT3-to-NRZI conversion, data and clock recovery, NRZI-to-NRZ conversion, de-scrambling, 4B/5B decoding, and serial-to-parallel conversion. The receiving side starts with the equalization filter to compensate for inter-symbol interference (ISI) over the twisted pair cable. Since the amplitude loss and phase distortion is a function of the cable length, the equalizer must adjust its characteristics to optimize performance. In this design, the variable equalizer makes an initial estimation based upon comparisons of incoming signal strength against some known cable characteristics, and then tunes itself for optimization. This is an ongoing process and self-adjusts against environmental changes such as temperature variations. Next, the equalized signal goes through a DC restoration and data conversion block. The DC restoration circuit is used to compensate for the effect of baseline wander and to improve the dynamic range. The differential data conversion circuit converts the MLT3 format back to NRZI. The slicing threshold is also adaptive. The clock recovery circuit extracts the 125MHz clock from the edges of the NRZI signal. This recovered clock is then used to convert the NRZI signal into the NRZ format. This signal is sent through the de-scrambler followed by the 4B/5B decoder. Finally, the NRZ serial data is converted to the MII format and provided as the input data to the MAC. PLL Clock Synthesizer The KSZ8041TL/FTL/MLL generates 125MHz, 25MHz and 20MHz clocks for system timing. In MII mode, internal clocks are generated from an external 25MHz crystal or oscillator. For the KSZ8041TL/FTL, in RMII and SMII modes, these internal clocks are generated from external 50MHz and 125MHz oscillators or system clocks, respectively. Scrambler/De-scrambler (100Base-TX only) The purpose of the scrambler is to spread the power spectrum of the signal in order to reduce EMI and baseline wander. 10Base-T Transmit The 10Base-T drivers are incorporated with the 100Base-TX drivers to allow for transmission using the same magnetic. The drivers also perform internal wave-shaping and pre-emphasize, and output 10Base-T signals with a typical amplitude of 2.5V peak. The 10Base-T signals have harmonic contents that are at least 27dB below the fundamental frequency when driven by an all-ones Manchester-encoded signal.
Micrel, Inc. KSZ8041TL/FTL/MLL December 2009 23 M9999-120909-1.2 10Base-T Receive On the receive side, input buffer and level detecting squelch circuits are employed. A differential input receiver circuit and a PLL performs the decoding function. The Manchester-encoded data stream is separated into clock signal and NRZ data. A squelch circuit rejects signals with levels less than 400mV or with short pulse widths to prevent noise at the RX+ and RX- inputs from falsely trigger the decoder. When the input exceeds the squelch limit, the PLL locks onto the incoming signal and the KSZ8041TL/FTL/MLL decodes a data frame. The receive clock is kept active during idle periods in between data reception. SQE and Jabber Function (10Base-T only) In 10Base-T operation, a short pulse is put out on the COL pin after each frame is transmitted. This SQE Test is required as a test of the 10Base-T transmit/receive path. If transmit enable (TXEN) is high for more than 20ms (jabbering), the 10Base-T transmitter is disabled and COL is asserted high. If TXEN is then driven low for more than 250ms, the 10Base- T transmitter is re-enabled and COL is de-asserted (returns to low). Auto-Negotiation The KSZ8041TL/FTL/MLL conforms to the auto-negotiation protocol, defined in Clause 28 of the IEEE 802.3u specification. Auto-negotiation is enabled by either hardware pin strapping (pin 42) or software (register 0h bit 12). Auto-negotiation allows unshielded twisted pair (UTP) link partners to select the highest common mode of operation. Link partners advertise their capabilities to each other, and then compare their own capabilities with those they received from their link partners. The highest speed and duplex setting that is common to the two link partners is selected as the mode of operation. The following list shows the speed and duplex operation mode from highest to lowest. /g120 Priority 1: 100Base-TX, full-duplex /g120 Priority 2: 100Base-TX, half-duplex /g120 Priority 3: 10Base-T, full-duplex /g120 Priority 4: 10Base-T, half-duplex If auto-negotiation is not supported or the KSZ8041TL/FTL/MLL link partne r is forced to bypass auto-negotiation, the KSZ8041TL/FTL/MLL sets its operating mode by observing the signal at its receiver. This is known as parallel detection, and allows the KSZ8041TL/FTL/MLL to establish link by listening for a fixed signal protocol in the absence of auto- negotiation advertisement protocol. The auto-negotiation link up process is shown in the following flow chart.
Figure 1. Auto-Negotiation Flow Chart
/g120 A physical connection that incorporates the clock line (MDC) and the data line (MDIO). single KSZ8041TL/FTL/MLL device, or write to multiple KSZ8041TL/FTL/MLL devices simultaneously. Specification. The additional registers are provided for expanded functionality. The following table shows the MII Management frame format for the KSZ8041TL/FTL/MLL. Table 1. MII Management Frame Format Bit 9 of register 1Fh sets the interrupt level to active high or active low. /g120 Supports 10Mbps and 100Mbps data rates. /g120 Uses a 25MHz reference clock, sourced by the PHY. /g120 Provides independent 4-bit wide (nibble) transmit and receive data paths. /g120 Contains two distinct groups of signals: one for transmission and the other for reception. /g120 CONFIGURATION[2:0] (pins 27, 41, 40) set to ‘000’ (default setting).
The following table describes the MII signals. Refer to Clause 22 of the IEEE 802.3 Specification for detailed information. Table 2. MII Signal Definition TXC is sourced by the PHY. It is a continuous clock that provides the timing reference for TXEN and TXD[3:0]. TXC is 2.5MHz for 10Mbps operation and 25MHz for 100Mbps operation. prior to the first TXC following the final nibble of a frame. TXEN transitions synchronously with respect to TXC. is de-asserted are ignored by the PHY. RXC provides the timing reference for RXDV, RXD[3:0], and RXER. clock when the line is idle, or link is down. RXC is 2.5MHz for 10Mbps operation and 25MHz for 100Mbps operation.
Micrel, Inc. KSZ8041TL/FTL/MLL December 2009 27 M9999-120909-1.2 Receive Data Valid (RXDV) RXDV is driven by the PHY to indicate that the PHY is presenting recovered and decoded nibbles on RXD[3:0]. /g120 In 10Mbps mode, RXDV is asserted with the first nibble of the SFD (Start of Frame Delimiter), “5D”, and remains asserted until the end of the frame. /g120 In 100Mbps mode, RXDV is asserted from the first nibble of the preamble to the last nibble of the frame. RXDV transitions synchronously with respect to RXC. Receive Data [3:0] (RXD[3:0]) RXD[3:0] transitions synchronously with respect to RXC. For each clock period in which RXDV is asserted, RXD[3:0] transfers a nibble of recovered data from the PHY. Receive Error (RXER) RXER is asserted for one or more RXC periods to indicate that a Symbol Error (e.g. a coding error that a PHY is capable of detecting, and that may otherwise be undetectable by the MAC sub-layer) was detected somewhere in the frame presently being transferred from the PHY. RXER transitions synchronously with respect to RXC. While RXDV is de-asserted, RXER has no effect on the MAC. Carrier Sense (CRS) CRS is asserted and de-asserted as follows: /g120 In 10Mbps mode, CRS assertion is based on the reception of valid preambles. CRS de-assertion is based on the reception of an end-of-frame (EOF) marker. /g120 In 100Mbps mode, CRS is asserted when a start-of-stream delimiter, or /J/K symbol pair is detected. CRS is de- asserted when an end-of-stream delimiter, or /T/R symbol pair is detected. Additionally, the PMA layer de-asserts CRS if IDLE symbols are received without /T/R. Collision (COL) COL is asserted in half-duplex mode whenever the transmitter and receiver are simultaneously active on the line. This is used to inform the MAC that a collision has occurred during its transmission to the PHY. COL transitions asynchronously with respect to TXC and RXC. Reduced MII (RMII) Data Interface (KSZ8041TL/FTL only) The Reduced Media Independent Interface (RMII) specifies a low pin count Media Independent Interface (MII). It provides a common interface between physical layer and MAC layer devices, and has the following key characteristics: /g120 Supports 10Mbps and 100Mbps data rates. /g120 Uses a single 50MHz reference clock provided by the MAC or the system board. /g120 Provides independent 2-bit wide (di-bit) transmit and receive data paths. /g120 Contains two distinct groups of signals: one for transmission and the other for reception. The KSZ8041TL/FTL is configured in RMII mode after it is power-up or reset with the following: /g120 A 50 MHz reference clock connected to REFCLK (pin 15). /g120 CONFIG[2:0] (pins 27, 41, 40) set to ‘001’. In RMII mode, unused MII signals, TXD[3:2] (pins 39, 38), are tied to ground.
The following table describes the RMII signals. Refer to RMII Specification for detailed information. Table 3. RMII Signal Description TX_EN, TXD[1:0], CRS_DV, RXD[1:0], and RX_ER. prior to the first REF_CLK following the final di-bit of a frame. TX_EN transitions synchronously with respect to REF_CLK. while TX_EN is de-asserted are ignored by the PHY. 100Mbps mode. Loss of carrier results in the de-assertion of CRS_DV. relative to REF_CLK, the data on RXD[1:0] is "00" until proper receive signal decoding takes place. than “00” on RXD[1:0] while CRS_DV is de-asserted are ignored by the MAC. frame presently being transferred from the PHY.
The MAC regenerates the COL signal of the MII from TX_EN and CRS_DV. /g120 Supports 10Mbps and 100Mbps data rates. /g120 Uses 125MHz reference clock provided by the MAC or the system board. /g120 Uses 12.5MHz sync pulse provided by the MAC. /g120 Provides independent single-bit wide transmit and receive data paths for data and control information. /g120 A 125MHz reference clock connected to CLOCK (pin 15). /g120 A 12.5MHz sync pulse connected to SYNC (pin 36). In SMII mode, unused MII signals, TXD[3:2] (pins 39, 38), are tied to ground. The following table describes the SMII signals. Refer to SMII Specification for detailed information. Table 4. SMII Signal Description each transmit data/control segment, or receive data/control segment. Each segment is comprised of ten bits. SYNC is generated continuously by the MAC at every ten cycles of CLOCK. TX provides transmit data and control information from MAC-to-PHY in 10-bit segments. data. The PHY can sample any one of every ten segments. /g120 In 100Mbps mode, each segment represents a new byte of data.
Figure 2. SMII Transmit Data/Control Segment Table 5. SMII TX Bit Description Table 6. SMII TXD[0:7] Encoding Table RX provides receive data and control information from PHY-to-MAC in 10-bit segments. data. The MAC can sample any one of every ten segments. /g120 In 100Mbps mode, each segment represents a new byte of data.
Figure 3. SMII Receive Data/Control Segment Table 7. SMII RX Bit Description Table 8. SMII RXD[0:7] Encoding Table
receive pairs from the link partner, and then assigns transmit and receive pairs of the KSZ8041TL/FTL/MLL accordingly. selected by register 1F bit 14 if HP Auto MDI/MDI-X is disabled. An isolation transformer with symmetrical transmit and receive data paths is recommended to support auto MDI/MDI-X.
1 TD+ 1 RD+
2 TD- 2 RD-
3 RD+ 3 TD+
6 RD- 6 TD-
Table 9. MDI/MDI-X Pin Definition depicts a typical straight cable connection between a NIC card (MDI) and a switch, or hub (MDI-X). Figure 4. Typical Straight Cable Connection
following diagram depicts a typical crossover cable connection between two switches or hubs (two MDI-X devices). Figure 5. Typical Crossover Cable Connection
Micrel, Inc. KSZ8041TL/FTL/MLL December 2009 34 M9999-120909-1.2 LinkMD® Cable Diagnostics The LinkMD® feature utilizes time domain reflectometry (TDR) to analyze the cabling plant for common cabling problems, such as open circuits, short circuits and impedance mismatches. LinkMD® works by sending a pulse of known amplitude and duration down the MDI and MDI-X pairs, and then analyzing the shape of the reflected signal. Timing the pulse duration gives an indication of the distance to the cabling fault with maximum distance of 200m and accuracy of +/-2m. Internal circuitry computes the TDR information and presents it in a user-readable digital format. Note: Cable diagnostics are only valid for copper connections and do not support fiber optic operation. Access LinkMD® is initiated by accessing register 1Dh, the LinkMD ® Control/Status Register, in conjunction with register 1Fh, the PHY Control 2 Register. Usage The following test procedure demonstrates how to use LinkMD® for cable diagnostic: 1. Disable auto MDI/MDI-X by writing a ‘1’ to register 1Fh bit 13 to enable manual control over the differential pair used to transmit the LinkMD® pulse. 2. Select the differential pair to transmit the LinkMD ® pulse with register 1Fh bit 14. 3. Start cable diagnostic test by writing a ‘1’ to register 1Dh bit 15. This enable bit is self-clearing. 4. Wait (poll) for register 1Dh bit 15 to return a ‘0’, indicating cable diagnostic test is completed. 5. Read cable diagnostic test results in register 1Dh bits [14:13]. The results are as follows: 00 = normal condition (valid test) 01 = open condition detected in cable (valid test) 10 = short condition detected in cable (valid test) 11 = cable diagnostic test failed (invalid test) The ‘11’ case, invalid test, occurs if the KSZ8041TL/FTL/MLL is unable to shut down the link partner. In this instance, the test is not run, since it would be impossible for the KSZ8041TL/FTL/MLL to determine if the detected signal is a reflection of the signal generated by the KSZ8041TL/FTL/MLL, or a signal from its link partner. 6. Get distance to fault by multiplying the decimal value in register 1Dh bits [8:0] by a constant of 0.4. The distance, D (expressed in meters), to the cable fault is determined by the following formula: D (distance to cable fault) = 0.4 x {decimal value of register 1Dh bits [8:0]} The 0.4 constant can be calibrated for different cable types and cabling conditions, such as cables with velocity of propagation that varies significantly from the norm. Power Management The KSZ8041TL/FTL/MLL offers the following power management modes: Power Saving Mode This mode is used to reduce power consumption when the cable is unplugged. It is in effect when auto-negotiation mode is enabled, cable is disconnected, and register 1Fh bit 10 is set to 1. Under power saving mode, the KSZ8041TL/FTL/MLL shuts down all transceiver blocks, except for transmitter, energy detect and PLL circuits. Additionally, in MII mode, the RXC clock output is disabled. RXC clock is enabled after the cable is connected and link is established. Power saving mode is disabled by writing a zero to register 1Fh bit 10. Power Down Mode This mode is used to power down the entire KSZ8041TL/FTL/MLL device when it is not in use. Power down mode is enabled by writing a one to register 0h bit 11. In the power down state, the KSZ8041TL/FTL/MLL disables all internal functions, except for the MII management interface.
connections are shown in the following figure and table. Figure 9. KSZ8041TL/FTL/MLL Power and Ground Connections Decouple with 22uF and 0.1uF capacitors to ground. VDD_1.8 31 Input Connect to V1.8_OUT (pin 6) thru ferrite bead. Decouple with 0.1uF capacitor to ground. VDDA_1.8 4, 5 Input Connect to V1.8_OUT (pin 6) thru ferrite bead. Decouple with 0.1uF capacitor on each pin to ground. VDDIO_3.3 25, 26 Input Connect to board’s 3.3V supply. Decouple with 22uF and 0.1uF capacitors to ground. VDDA_3.3 7, 8 Input Connect to board’s 3.3V supply thru ferrite bead. Decouple with 22uF and 0.1uF capacitors to ground. Table 10. KSZ8041TL/FTL/MLL Power Pin Description
Table 11. Copper and Fiber Mode Selection output voltage swing to match the FXSD pin’s input voltage threshold. zero. This pattern is used to inform the fiber link partner that there is a faulty link on its transmit side. By default, FEF is enabled. FEF is disabled by strapping “no FEF” (pin 43) low. See “Strapping Options” section for detail.
at 10Base-T is not allowed, and is blocked during auto-negotiation. Figure 10. KSZ8041TL/MLL and KSZ8041FTL Back-to-Back Media Converter /g120 MII signals connected as shown in the following table. Table 12. MII Signal Connection for MII Back-to-Back Mode
/g120 RMII signals connected as shown in the following table. Table 13. RMII Signal Connection for RMII Back-to-Back Mode energy detected (cable connected).
Micrel, Inc. KSZ8041TL/FTL/MLL December 2009 40 M9999-120909-1.2 Register Map Register Number (Hex) Description 0h Basic Control 1h Basic Status 2h PHY Identifier 1 3h PHY Identifier 2 4h Auto-Negotiation Advertisement 5h Auto-Negotiation Link Partner Ability 6h Auto-Negotiation Expansion 7h Auto-Negotiation Next Page 8h Link Partner Next Page Ability 9h – 13h Reserved 14h MII Control 15h RXER Counter 16h – 1Ah Reserved 1Bh Interrupt Control/Status 1Ch Reserved 1Dh LinkMD ® Control/Status 1Eh PHY Control 1 1Fh PHY Control 2 Register Description Address Name Description Mode(1) Default Register 0h – Basic Control
0.15 Reset 1 = Software reset
0 = Normal operation This bit is self-cleared after a ‘1’ is written to it. RW/SC 0
0.14 Loop-back 1 = Loop-back mode
0 = Normal operation RW 0
0.13 Speed Select
(LSB) 1 = 100Mbps 0 = 10Mbps This bit is ignored if auto-negotiation is enabled (register 0.12 = 1). RW Set by SPEED strapping pin. See “Strapping Options” section for details.
0.12 Auto-
1 = Enable auto-negotiation process 0 = Disable auto-negotiation process If enabled, auto-negotiation result overrides settings in register 0.13 and 0.8. RW Set by NWAYEN strapping pin. See “Strapping Options” section for details.
0.11 Power Down 1 = Power down mode
0 = Normal operation RW 0
0.10 Isolate 1 = Electrical isolation of PHY from MII and
0 = Normal operation RW Set by ISO strapping pin. See “Strapping Options” section for details.
0.9 Restart Auto-
1 = Restart auto-negotiation process 0 = Normal operation. This bit is self-cleared after a ‘1’ is written to it. RW/SC 0
Micrel, Inc. KSZ8041TL/FTL/MLL December 2009 41 M9999-120909-1.2 Address Name Description Mode(1) Default
0.8 Duplex Mode 1 = Full-duplex
0 = Half-duplex RW Inverse of DUPLEX strapping pin value. See “Strapping Options” section for details.
0.7 Collision Test 1 = Enable COL test
0 = Disable COL test RW 0 0.6:1 Reserved RO 000_000
0.0 Disable
0 = Enable transmitter 1 = Disable transmitter RW 0 Register 1h – Basic Status 1.15 100Base-T4 1 = T4 capable 0 = Not T4 capable RO 0 1.14 100Base-TX Full Duplex 1 = Capable of 100Mbps full-duplex 0 = Not capable of 100Mbps full-duplex RO 1 1.13 100Base-TX Half Duplex 1 = Capable of 100Mbps half-duplex 0 = Not capable of 100Mbps half-duplex RO 1 1.12 10Base-T Full Duplex 1 = Capable of 10Mbps full-duplex 0 = Not capable of 10Mbps full-duplex RO 1 1.11 10Base-T Half Duplex 1 = Capable of 10Mbps half-duplex 0 = Not capable of 10Mbps half-duplex RO 1 1.10:7 Reserved RO 0000
1.6 No Preamble 1 = Preamble suppression
0 = Normal preamble RO 1
1.5 Auto-
1 = Auto-negotiation process completed 0 = Auto-negotiation process not completed RO 0
1.4 Remote Fault 1 = Remote fault
0 = No remote fault RO/LH 0
1.3 Auto-
1 = Capable to perform auto-negotiation 0 = Not capable to perform auto-negotiation RO 1
1.2 Link Status 1 = Link is up
0 = Link is down RO/LL 0
1.1 Jabber Detect 1 = Jabber detected
0 = Jabber not detected (default is low) RO/LH 0
1.0 Extended
1 = Supports extended capabilities registers RO 1 Register 2h – PHY Identifier 1 2.15:0 PHY ID Number Assigned to the 3rd through 18th bits of the Organizationally Unique Identifier (OUI). Kendin Communication’s OUI is 0010A1 (hex) RO 0022h
Micrel, Inc. KSZ8041TL/FTL/MLL December 2009 42 M9999-120909-1.2 Address Name Description Mode(1) Default Register 3h – PHY Identifier 2 3.15:10 PHY ID Number Assigned to the 19th through 24th bits of the Organizationally Unique Identifier (OUI). Kendin Communication’s OUI is 0010A1 (hex) RO 0001_01 3.9:4 Model Number Six bit manufacturer’s model number RO 01_0001 3.3:0 Revision Number Four bit manufacturer’s revision number RO Indicate silicon revision Register 4h – Auto-Negotiation Advertisement
4.15 Next Page 1 = Next page capable
0 = No next page capability. RW 0
4.14 Reserved RO 0
4.13 Remote Fault 1 = Remote fault supported
0 = No remote fault RW 0
4.12 Reserved RO 0
4.11:10 Pause [00] = No PAUSE [10] = Asymmetric PAUSE [01] = Symmetric PAUSE [11] = Asymmetric & Symmetric PAUSE RW 00 4.9 100Base-T4 1 = T4 capable 0 = No T4 capability RO 0 4.8 100Base-TX Full-Duplex 1 = 100Mbps full-duplex capable 0 = No 100Mbps full-duplex capability RW Set by SPEED strapping pin. See “Strapping Options” section for details. 4.7 100Base-TX Half-Duplex 1 = 100Mbps half-duplex capable 0 = No 100Mbps half-duplex capability RW Set by SPEED strapping pin. See “Strapping Options” section for details. 4.6 10Base-T Full-Duplex 1 = 10Mbps full-duplex capable 0 = No 10Mbps full-duplex capability RW 1 4.5 10Base-T Half-Duplex 1 = 10Mbps half-duplex capable 0 = No 10Mbps half-duplex capability RW 1 4.4:0 Selector Field [00001] = IEEE 802.3 RW 0_0001 Register 5h – Auto-Negotiation Link Partner Ability
5.15 Next Page 1 = Next page capable
0 = No next page capability RO 0
5.14 Acknowledge 1 = Link code word received from partner
0 = Link code word not yet received RO 0
5.13 Remote Fault 1 = Remote fault detected
0 = No remote fault RO 0
5.12 Reserved RO 0
5.11:10 Pause [00] = No PAUSE [10] = Asymmetric PAUSE [01] = Symmetric PAUSE [11] = Asymmetric & Symmetric PAUSE RO 00
Micrel, Inc. KSZ8041TL/FTL/MLL December 2009 43 M9999-120909-1.2 Address Name Description Mode(1) Default 5.9 100Base-T4 1 = T4 capable 0 = No T4 capability RO 0 5.8 100Base-TX Full-Duplex 1 = 100Mbps full-duplex capable 0 = No 100Mbps full-duplex capability RO 0 5.7 100Base-TX Half-Duplex 1 = 100Mbps half-duplex capable 0 = No 100Mbps half-duplex capability RO 0 5.6 10Base-T Full-Duplex 1 = 10Mbps full-duplex capable 0 = No 10Mbps full-duplex capability RO 0 5.5 10Base-T Half-Duplex 1 = 10Mbps half-duplex capable 0 = No 10Mbps half-duplex capability RO 0 5.4:0 Selector Field [00001] = IEEE 802.3 RO 0_0001 Register 6h – Auto-Negotiation Expansion 6.15:5 Reserved RO 0000_0000_000
6.4 Parallel
1 = Fault detected by parallel detection 0 = No fault detected by parallel detection. RO/LH 0
6.3 Link Partner
1 = Link partner has next page capability 0 = Link partner does not have next page capability RO 0
6.2 Next Page
1 = Local device has next page capability 0 = Local device does not have next page capability RO 1
6.1 Page Received 1 = New page received
0 = New page not received yet RO/LH 0
6.0 Link Partner
1 = Link partner has auto-negotiation capability 0 = Link partner does not have auto-negotiation capability RO 0 Register 7h – Auto-Negotiation Next Page
7.15 Next Page 1 = Additional next page(s) will follow
0 = Last page RW 0
7.14 Reserved RO 0
7.13 Message Page 1 = Message page
0 = Unformatted page RW 1
7.12 Acknowledge2 1 = Will comply with message
0 = Cannot comply with message RW 0
7.11 Toggle 1 = Previous value of the transmitted link code
0 = Logic zero RO 0 7.10:0 Message Field 11-bit wide field to encode 2048 messages RW 000_0000_0001 Register 8h – Link Partner Next Page Ability
8.15 Next Page 1 = Additional Next Page(s) will follow
0 = Last page RO 0
Micrel, Inc. KSZ8041TL/FTL/MLL December 2009 44 M9999-120909-1.2 Address Name Description Mode(1) Default
8.14 Acknowledge 1 = Successful receipt of link word
0 = No successful receipt of link word RO 0
8.13 Message Page 1 = Message page
0 = Unformatted page RO 0
8.12 Acknowledge2 1 = Able to act on the information
0 = Not able to act on the information RO 0
8.11 Toggle 1 = Previous value of transmitted link code
0 = Previous value of transmitted link code word equal to logic one RO 0 8.10:0 Message Field RO 000_0000_0000 Register 14h – MII Control 14.15:8 Reserved RO 0000_0000 14.7 100Base-TX Preamble Restore 1 = Restore received preamble to MII output (random latency) 0 = Consume 1-byte preamble before sending frame to MII output for fixed latency RW 0 or 1 (if CONFIG[2:0] = 100) See “Strapping Options” section for details. 14.6 10Base-T Preamble Restore 1 = Restore received preamble to MII output 0 = Remove all 7-bytes of preamble before sending frame (starting with SFD) to MII output RW 0 14.5:0 Reserved RO 00_0001 Register 15h – RXER Counter 15.15:0 RXER Counter Receive error counter for Symbol Error frames RO/SC 0000h Register 1Bh – Interrupt Control/Status 1b.15 Jabber Interrupt Enable 1 = Enable Jabber Interrupt 0 = Disable Jabber Interrupt RW 0 1b.14 Receive Error Interrupt Enable 1 = Enable Receive Error Interrupt 0 = Disable Receive Error Interrupt RW 0 1b.13 Page Received Interrupt Enable 1 = Enable Page Received Interrupt 0 = Disable Page Received Interrupt RW 0 1b.12 Parallel Detect Fault Interrupt Enable 1 = Enable Parallel Detect Fault Interrupt 0 = Disable Parallel Detect Fault Interrupt RW 0 1b.11 Link Partner Acknowledge Interrupt Enable 1 = Enable Link Partner Acknowledge Interrupt 0 = Disable Link Partner Acknowledge Interrupt RW 0 1b.10 Link Down Interrupt Enable 1 = Enable Link Down Interrupt 0 = Disable Link Down Interrupt RW 0 1b.9 Remote Fault Interrupt Enable 1 = Enable Remote Fault Interrupt 0 = Disable Remote Fault Interrupt RW 0
Micrel, Inc. KSZ8041TL/FTL/MLL December 2009 45 M9999-120909-1.2 Address Name Description Mode(1) Default 1b.8 Link Up Interrupt Enable 1 = Enable Link Up Interrupt 0 = Disable Link Up Interrupt RW 0 1b.7 Jabber Interrupt 1 = Jabber occurred 0 = Jabber did not occurred RO/SC 0 1b.6 Receive Error Interrupt 1 = Receive Error occurred 0 = Receive Error did not occurred RO/SC 0 1b.5 Page Receive Interrupt 1 = Page Receive occurred 0 = Page Receive did not occurred RO/SC 0 1b.4 Parallel Detect Fault Interrupt 1 = Parallel Detect Fault occurred 0 = Parallel Detect Fault did not occurred RO/SC 0 1b.3 Link Partner Acknowledge Interrupt 1 = Link Partner Acknowledge occurred 0 = Link Partner Acknowledge did not occurred RO/SC 0 1b.2 Link Down Interrupt 1 = Link Down occurred 0 = Link Down did not occurred RO/SC 0 1b.1 Remote Fault Interrupt 1 = Remote Fault occurred 0 = Remote Fault did not occurred RO/SC 0 1b.0 Link Up Interrupt 1 = Link Up occurred 0 = Link Up did not occurred RO/SC 0 Register 1Dh – LinkMD® Control/Status 1d.15 Cable Diagnostic Test Enable 1 = Enable cable diagnostic test. After test has completed, this bit is self-cleared. 0 = Indicates cable diagnostic test (if enabled) has completed and the status information is valid for read. RW/SC 0 1d.14:13 Cable Diagnostic Test Result [00] = normal condition [01] = open condition has been detected in cable [10] = short condition has been detected in cable [11] = cable diagnostic test has failed RO 00 1d.12:9 Reserved 0000 1d.8:0 Cable Fault Counter Distance to fault; it’s approximately 0.4m*(Cable Fault Counter value in decimal) RO 0_0000_0000 Register 1Eh – PHY Control 1 1e.15:14 LED mode [00] = LED1 : Speed LED0 : Link/Activity [01] = LED1 : Activity LED0 : Link [10], [11] = Reserved RW 00 1e.13 Polarity 0 = Polarity is not reversed 1 = Polarity is reversed RO
Micrel, Inc. KSZ8041TL/FTL/MLL December 2009 46 M9999-120909-1.2 Address Name Description Mode(1) Default 1e.12 Far-End Fault Detect 0 = Far-End Fault not detected 1 = Far-End Fault detected This bit applies to KSZ8041FTL fiber only. RO 0 1e.11 MDI/MDI-X State 0 = MDI 1 = MDI-X RO 1e.10:8 Reserved 1e.7 Remote loopback 0 = Normal mode 1 = Remote (analog) loop back is enable RW 0 1e.6:0 Reserved Register 1Fh – PHY Control 2 1f.15 HP_MDIX 0 = Micrel Auto MDI/MDI-X mode 1 = HP Auto MDI/MDI-X mode RW 1 1f.14 MDI/MDI-X Select When Auto MDI/MDI-X is disabled, 0 = MDI Mode Transmit on TX+/- (pins 12,11) and Receive on RX+/- (pins 10,9) 1 = MDI-X Mode Transmit on RX+/- (pins 10,9) and Receive on TX+/- (pins 12,11) RW 0 1f.13 Pairswap Disable 1 = Disable auto MDI/MDI-X 0 = Enable auto MDI/MDI-X RW 0 1f.12 Energy Detect 1 = Presence of signal on RX+/- analog wire pair 0 = No signal detected on RX+/- RO 0 1f.11 Force Link 1 = Force link pass 0 = Normal link operation This bit bypasses the control logic and allow transmitter to send pattern even if there is no link. RW 0 1f.10 Power Saving 1 = Enable power saving 0 = Disable power saving If power saving mode is enabled and the cable is disconnected, the RXC clock output (in MII mode) is disabled. RXC clock is enabled after the cable is connected and link is established. RW 0 1f.9 Interrupt Level 1 = Interrupt pin active high 0 = Interrupt pin active low RW 0 1f.8 Enable Jabber 1 = Enable jabber counter 0 = Disable jabber counter RW 1 1f.7 Auto- Negotiation Complete 1 = Auto-negotiation process completed 0 = Auto-negotiation process not completed RO 0 1f.6 Enable Pause (Flow Control) 1 = Flow control capable 0 = No flow control capability RO 0
Micrel, Inc. KSZ8041TL/FTL/MLL December 2009 47 M9999-120909-1.2 Address Name Description Mode(1) Default 1f.5 PHY Isolate 1 = PHY in isolate mode 0 = PHY in normal operation RO 0 1f.4:2 Operation Mode Indication [000] = still in auto-negotiation [001] = 10Base-T half-duplex [010] = 100Base-TX half-duplex [011] = reserved [101] = 10Base-T full-duplex [110] = 100Base-TX full-duplex [111] = reserved RO 000 1f.1 Enable SQE test 1 = Enable SQE test 0 = Disable SQE test RW 0 1f.0 Disable Data Scrambling 1 = Disable scrambler 0 = Enable scrambler RW 0 Note: 1. RW = Read/Write. RO = Read only. SC = Self-cleared. LH = Latch high. LL = Latch low.
Micrel, Inc. KSZ8041TL/FTL/MLL December 2009 48 M9999-120909-1.2 Absolute Maximum Ratings(1) Supply Voltage Operating Ratings(2) Supply Voltage Electrical Characteristics(3) Symbol Parameter Condition Min Typ Max Units Supply Current(4) IDD1 100Base-TX Chip only (no transformer); Full-duplex traffic @ 100% utilization 53.0 58.3 mA IDD2 10Base-T Chip only (no transformer); Full-duplex traffic @ 100% utilization 38.0 41.8 mA IDD3 Power Saving Mode Ethernet cable disconnected (reg. 1F.10 = 1) 32.0 35.2 mA IDD4 Power Down Mode Software power down (reg. 0.11 = 1) 4.0 4.4 mA TTL Inputs VIH Input High Voltage 2.0 V VIL Input Low Voltage 0.8 V IIN Input Current V IN = GND ~ VDDIO -10 10 μA TTL Outputs VOH Output High Voltage I OH = -4mA 2.4 V VOL Output Low Voltage I OL = 4mA 0.4 V |Ioz| Output Tri-State Leakage 10 μA LED Outputs ILED Output Drive Current Each LED pin (LED0, LED1) 8 mA 100Base-TX Transmit (measured differentially after 1:1 transformer) VO Peak Differential Output Voltage 100/g159 termination across differential output 0.95 1.05 V VIMB Output Voltage Imbalance 100/g159termination across differential output 2 % tr, tf Rise/Fall Time 3 5 Ns Rise/Fall Time Imbalance 0 0.5 Ns Duty Cycle Distortion ± 0.25 Ns Overshoot 5 % VSET Reference Voltage of I SET 0.65 V Output Jitter Peak-to-peak 0.7 1.4 Ns 10Base-T Transmit (measured differentially after 1:1 transformer) VP Peak Differential Output Voltage 100/g159 termination across differential output 2.2 2.8 V Jitter Added Peak-to-peak 3.5 Ns tr, tf Rise/Fall Time 25 ns 10Base-T Receive VSQ Squelch Threshold 5MHz square wave 400 mV
Micrel, Inc. KSZ8041TL/FTL/MLL December 2009 49 M9999-120909-1.2 Notes: 1. Exceeding the absolute maximum rating may damage the device. Stresses greater than the absolute maximum rating may cause pe rmanent damage to the device. Operation of the device at these or any other conditions above those specified in the operating section s of this specification is not implied. Maximum conditions for extended periods may affect reliability. 2. The device is not guaranteed to function outside its operating rating. 3. TA = 25°C. Specification for packaged product only. that is provided by the KSZ8041TL/FTL/MLL. The PHY port’s transformer consumes an additional 45mA @ 3.3V for 100Base-TX and 70 mA @ 3.3V for 10Base-T.
Figure 11. MII SQE Timing (10Base-T) Table 14. MII SQE Timing (10Base-T) Parameters
Figure 12. MII Transmit Timing (10Base-T) Table 15. MII Transmit Timing (10Base-T) Parameters
Figure 13. MII Receive Timing (10Base-T) Table 16. MII Receive Timing (10Base-T) Parameters
Figure 14. MII Transmit Timing (100Base-TX) Table 17. MII Transmit Timing (100Base-TX) Parameters
Figure 15. MII Receive Timing (100Base-TX) Table 18. MII Receive Timing (100Base-TX) Parameters
Figure 20. Auto-Negotiation Fast Link Pulse (FLP) Timing Table 21. Auto-Negotiation Fast Link Pulse (FLP) Timing Parameters
Figure 21. MDC/MDIO Timing Table 22. MDC/MDIO Timing Parameters
The KSZ8041TL/FTL/MLL reset timing requirement is summarized in the following figure and table. Figure 22. Reset Timing Table 23. Reset Timing Parameters
The following figure shows the reference circuits for pull-up, float and pull-down on the LED1 and LED0 strapping pins. Figure 25. Reference Circuits for LED Strapping Pins
is recommended for exceeding FCC requirements. The following table gives recommended transformer characteristics. Table 24. Transformer Selection Criteria Table 25. Qualified Single Port Magnetics Table 26. Typical Reference Crystal Characteristics
Micrel, Inc. KSZ8041TL/FTL/MLL December 2009 63 M9999-120909-1.2
Package Information
48-Pin (7mm x 7mm) LQFP Package
Micrel, Inc. KSZ8041TL/FTL/MLL December 2009 64 M9999-120909-1.2 48-Pin TQFP ,SNOISURTORPROHSALFDLOMEDULCNITONSEODNOISNEMID .MM452.0DEECXETONLLAHSHCIHWFOREHTIE .NOISURTORPRABMADEDULCNITONSEODNOISNEMIDDAEL MOTTOBNAHTRELLAMSERASNOISNEMIDDLOMPOTEGAKCAP GNAHREVOTONLLIWEGAKCAPFOPOTDNASNOISNEMIDDLOM .EGAKCAPFOMOTTOB :SETON 48-Pin (7mm x 7mm) TQFP Package Note: ALL DIMENSIONS ARE IN MILLIMETERS.
Micrel, Inc. KSZ8041TL/FTL/MLL December 2009 65 M9999-120909-1.2 MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http://www.micrel.com The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser’s own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. © 2008 Micrel, Incorporated.