KSZ8041RNLI-TR

KSZ8041NL MICROCHIP | Alldatasheet

Document overview

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Technical content

DS00002245B-page 1  2017 Microchip Technology Inc. Highlights

• Single-Chip Ethernet Physical Layer Transceiver (PHY)
• HP Auto-MDIX Support Target Applications
• Printer
• L O M
• Game Console
• I P T V
• IP Phone
• IP Set-Top Box Key Benefits
• Single-Chip 10BASE-T/100BASE-TX Physical Layer Solution
• Fully Compliant To IEEE 802.3u Standard
• Low Power CMOS Design, Power Consumption of <180 mW
• HP Auto MDI/MDI-X For Reliable Detection and Correction for Straight-Through and Crossover Cables with Disable and Enable Option
• Robust Operation Over Standard Cables
• Power Down and Power Saving Modes
• MII Interface Support (KSZ8041NL Only)
• RMII Interface Support with External 50-MHz System Clock (KSZ8041NL Only)
• RMII Interface Support with 25-MHz Crystal/Clock Input and 50-MHz Reference Clock Output to MAC (KSZ8041RNL Only)
• MIIM (MDC/MDIO) Management Bus to 6.25 MHz for Rapid PHY Register Configuration
• Interrupt Pin Option
• Programmable LED Outputs for Link, Activity and Speed
• ESD Rating (6 kV)
• Single Power Supply (3.3V)
• Built-in 1.8V Regulator for Core
• Available In 32-pin 5 mm × 5 mm QFN Package KSZ8041NL/RNL 10BASE-T/100BASE-TX Physical Layer Transceiver

DS00002245B-page 2  2017 Microchip Technology Inc. TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for cur- rent devices. As device/doc umentation issues become known to us, we will publish an errata s heet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following:

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 2017 Microchip Technology Inc. DS00002245B-page 3 KSZ8041NL/RNL Table of Contents

DS0002245B-page 4  2017 Microchip Technology Inc.

1.0 GENERAL DESCRIPTION

The KSZ8041NL is a single supply 10BASE-T/100BASE-TX physical laye r transceiver, which provides MII/RMII interfaces to transmit and receive data. A unique mixed-signal design extends signaling distance while reducing power consumption. HP Auto MDI/MDI-X provides the most robust soluti on for eliminating the need to differentiate between crossover and straight-through cables. The KSZ8041NL represents a new level of features and performance and is an ideal choice of physical layer transceiver for 10BASE-T/100BASE-TX applications. The KSZ8041RNL is an enhanced Reduced Media I ndependent Interface (RMII) version of the KSZ8041NL that does not require a 50-MHz system clock. It uses a 25-MHz crystal for its input reference clock and outputs a 50-MHz RMII reference clock to the media access control (MAC). The KSZ8041NL and KSZ8041RNL are available in 32-pin, lead-free QFN packages (see Product Identifi- cation System). FIGURE 1-1: KSZ8041NL FUNCTIONAL DIAGRAM Pulse Shaper NRZ/NRZI MLT3 Encoder Parallel /Serial Manchester Encoder 4B/5B Encoder Scrambler Parallel /SerialTransmitter TX+ TX- Adaptive EQ Base Line Wander Correction MLT3 Decoder NRZI/NRZ Clock Recovery 4B/5B Decoder Descrambler Serial/Parallel Auto Negotiation 10Base-T Receiver Manchester Decoder Serial/Parallel PLL LED Driver MII/RMII Registers and Controller Interface RX- RX+ XI XO LED1 LED0 Power Down Power Saving TXD3 TXD0 TXD1 TXD2 RXD3 TXEN TXC MDC MDIO RXER RXD0 RXD1 RXD2 REXT RXC RXDV CRS COL RST# INTRP

 2017 Microchip Technology Inc. DS0002245B-page 5 KSZ8041NL/RNL FIGURE 1-2: KSZ8041RNL FUNCTIONAL DIAGRAM Pulse Shaper NRZ/NRZI MLT3 Encoder Parallel/Serial Manchester Encoder 4B/5B Encoder Scrambler Parallel/Serial Transmitter TX+ TX- Adaptive EQ Base Line Wander Correction MLT3 Decoder NRZI/NRZ Clock Recovery 4B/5B Decoder Descrambler Serial/Parallel Auto Negotiation 10Base-T Receiver Manchester Decoder Serial/Parallel PLL LED Driver RMII RX- RX+ XI XO LED1 LED0 Power Down Power Saving TXD1 TXD0 RXD1 TX_EN MDC MDIO RX_ER RXD0 REXT REF_CLK CRS_DV RST# INTRP

DS00002245B-page 6  2017 Microchip Technology Inc.

2.0 PIN DESCRIPTION AND CONFIGURATION

2.1 KSZ8041NL Pin Description and Configuration

FIGURE 2-1: KSZ8041NL 32-QFN PIN ASSIGNMENT (TOP VIEW) TABLE 2-1: KSZ8041NL PIN DESCRIPTION Pin Number Symbol Buffer Type (Note 2-1) Description

1 GND Gnd Ground

2 VDDPLL_1.8 P 1.8V Analog VDD Decouple with 1.0-µF and 0.1-µF capacitors to ground. 3 VDDA_3.3 P 3.3V Analog V DD

4 RX- I/O Physical receive or transmit signal (- differential)

5 RX+ I/O Physical receive or transmit signal (+ differential)

6 TX- I/O Physical transmit or receive signal (- differential)

VDDPLL_1.8 VDDA_3.3 RX- RX+ TX- TX+ XO RXD3/PHYAD0 MDC MDIO REXT XI/REFCLK RXD2/PHYAD1 RXD1/RXD[1]/PHYAD2 RXD0/RXD[0]/DUPLEX 91 01 1 1 2 1 3 1 4 15 16 32 31 30 29 28 27 26 25 TXD0/TXD[0] TXEN/TX_EN TXC INTRP RXER/RX_ER/ISO RXC RXDV/CRSDV/CONFIG2 VDDIO_3.3 COL/CONFIG0 CRS/CONFIG1 LED0/NWAYEN LED1/SPEED RST# TXD3 TXD2 TXD1/TXD[1] Paddle Ground on bottom of chip

 2017 Microchip Technology Inc. DS00002245B-page 7 KSZ8041NL/RNL

7 TX+ I/O Physical transmit or receive signal (+ differential)

Crystal Feedback. This pin is used only in MII mode when a 25-MHz crystal is used. This pin is a no connect if an oscillator or an external clock source is used, or if RMII mode is selected.

9 XI /

Crystal/Oscillator/External Clock Input: MII mode: 25 MHz ±50 ppm (crystal, oscillator, or external clock) RMII mode: 50 MHz ±50 ppm (oscillator or external clock only)

10 REXT I/O

Set physical transmit output current. Connect a 6.49-K resistor in parallel with a 100-pF capacitor to ground on this pin.

11 MDIO I/O Management Interface (MII) Data I/O

This pin requires an external 4.7-K pull-up resistor.

12 MDC I Management Interface (MII) Clock Input

This pin is synchronous to the MDIO data interface.

13 RXD3 /

MII mode: Receive Data Output[3] (Note 2-2) Config mode: The pull-up/pull-down value is latched as PHY- ADDR[0] during power-up or reset. See “Strap-In option – KSZ8041NL” for details.

14 RXD2 /

MII mode: Receive Data Output[2] (Note 2-2) Config mode: The pull-up/pull-down value is latched as PHY- ADDR[1] during power-up or reset. See “Strap-In option – KSZ8041NL” for details. RXD1 / RXD[1] / PHYAD2 Ipd/O MII mode: Receive Data Output[1] (Note 2-2) RMII mode: Receive Data Output[1] (Note 2-3) Config mode: The pull-up/pull-down value is latched as PHY- ADDR[2] during power-up or reset. See “Strap-In option – KSZ8041NL” for details. RXD0 / RXD[0] / DUPLEX Ipu/O MII mode: Receive Data Output[0] (Note 2-2). RMII mode: Receive Data Output[0] (Note 2-3). Config mode: Latched as DUPLEX (register 0h, bit 8) during power- up or reset. See “Strap-In option – KSZ8041NL” for details. 17 VDDIO_3.3 P 3.3V Digital VDD RXDV / CRSDV / CONFIG2 Ipd/O MII mode: Receive Data Valid Output RMII mode: Carrier Sense/Receive Data Valid Output Config mode: The pull-up/pull-down value is latched as CONFIG2 during power-up or reset. See “Strap-In option – KSZ8041NL” for details.

19 RXC O MII mode: Receive Clock Output

RX_ER / ISO Ipd/O MII mode: Receive Error Output RMII mode: Receive Error Output Config mode: The pull-up/pull-down value is latched as ISOLATE during power-up or reset. See “Strap-In option – KSZ8041NL” for details. TABLE 2-1: KSZ8041NL PIN DESCRIPTION (CONTINUED) Pin Number Symbol Buffer Type (Note 2-1) Description

DS00002245B-page 8  2017 Microchip Technology Inc.

21 INTRP Opu

Interrupt Output: Programmable Interrupt Output Register 1Bh is the Interrupt Control/Status Register for program- ming the interrupt conditions and reading the interrupt status. Regis- ter 1Fh bit 9 sets the interrupt output to active low (default) or active high.

22 TXC O MII mode: Transmit Clock Output

23 TXEN /

TX_EN I MII mode: Transmit Enable Input RMII mode: Transmit Enable Input

24 TXD0 /

TXD[0] I MII mode: Transmit Data Input[0] (Note 2-4) RMII mode: Transmit Data Input[0] (Note 2-5)

25 TXD1 /

TXD[1] I MII mode: Transmit Data Input[1] (Note 2-4) RMII mode: Transmit Data Input[1] (Note 2-5)

26 TXD2 I MII mode: Transmit Data Input[2] (Note 2-4)

27 TXD3 I MII mode: Transmit Data Input[3] (Note 2-4)

28 COL/CONFIG0 Ipd/O

MII mode: Collision Detect Output Config mode: The pull-up/pull-down value is latched as CONFIG0 during power-up or reset. See “Strap-In option – KSZ8041NL” for details.

29 CRS/CONFIG1 Ipd/O

MII mode: Collision Sense Output Config mode: The pull-up/pull-down value is latched as CONFIG1 during power-up or reset. See “Strap-In option – KSZ8041NL” for details. TABLE 2-1: KSZ8041NL PIN DESCRIPTION (CONTINUED) Pin Number Symbol Buffer Type (Note 2-1) Description

 2017 Microchip Technology Inc. DS00002245B-page 9 KSZ8041NL/RNL

30 LED0 / NWAYEN Ipu/O

LED Output: Programmable LED0 Output Config ode: Latched as Auto-Negotiation Enable (register 0h, bit 12) during power-up or reset. See Strap-In option – KSZ8041NL for details. The LED0 pin is programmable via register 1Eh bits [15:14] and is defined as follows: LED Mode = [00] LED Mode = [01] LED Mode = [10] Reserved LED Mode = [11] Reserved TABLE 2-1: KSZ8041NL PIN DESCRIPTION (CONTINUED) Pin Number Symbol Buffer Type (Note 2-1) Description Link/Activity Pin State LED Definition No Link H OFF Link L ON Activity Toggle Blinking Link/Activity Pin State LED Definition No Link H OFF Link L ON

DS00002245B-page 10  2017 Microchip Technology Inc. Note 2-1 P = Power supply Gnd = Ground I = Input O = Output I/O = Bi-directional Ipd = Input with internal pull-down (40K ±30%) Ipu = Input with internal pull-up (40K ±30%) Opu = Output with internal pull-up (40K ±30%) Ipu/O = Input with internal pull-up (40K ±30% ) during power-up/reset; output pin otherwise. Ipd/O = Input with internal pull-down (40K ±30%) during power-up/reset; output pin otherwise. Note 2-2 MII Rx mode: The RXD[3:0] bits are synchronous with RXCLK. Wh en RXDV is asserted, RXD[3:0] presents a valid data to the MAC through the M II. RXD[3:0] is invalid when RXDV is deasserted. Note 2-3 RMII Rx mode: The RXD[1:0] bits are synchronous with REF_CLK. For each clock period in which CRS_DV is asserted, two bits of re covered data are sent from the PHY. Note 2-4 MII Tx mode: The TXD[3:0] bits are synchronous with TXCLK. When TXEN is asserted, TXD[3:0] presents a valid data from the MAC through the MII. TXD[3..0] has no effect when TXEN is deasserted. Note 2-5 RMII Tx mode: The TXD[ 1:0] bits are synchronous with REF_CL K. For each clock period in which TX_EN is asserted, two bits of data are received by the PHY from the MAC.

31 LED1 / SPEED Ipu/O

LED Output: Programmable LED1 Output Config mode: Latched as SPEED (register 0h, bit 13) during power- up or reset. See Strap-In option – KSZ8041NL for details. The LED1 pin is programmable via register 1Eh bits [15:14] and is defined as follows: LED Mode = [00] LED Mode = [01] LED Mode = [10] Reserved LED Mode = [11] Reserved

32 RST# I Chip Reset (active low)

TABLE 2-1: KSZ8041NL PIN DESCRIPTION (CONTINUED) Pin Number Symbol Buffer Type (Note 2-1) Description Speed Pin State LED Definition 10BT H OFF 100BT L ON Activity Pin State LED Definition No Activity H OFF Activity Toggle Blinking

 2017 Microchip Technology Inc. DS00002245B-page 11 KSZ8041NL/RNL

2.2 STRAP-IN OPTION – KSZ8041NL

Pin strap-ins are latched during power-up or reset. In some systems, the MAC receive input pins may drive high during power-up or reset, and consequently cause the PHY strap-in pins on the MII/RMII signals to be latched high. In this case, it is recommended to add 1K pull-downs on these PHY strap-in pins to ensure the PHY does not strap in to ISO- LATE mode, or is not configured with an incorrect PHY Address. Note 2-1 Ipu/O = Input with internal pull-up (40K ± 30%) during power-up/reset; output pin otherwise. Ipd/O = Input with internal pull-down (40K ±30%) during power-up/reset; output pin otherwise. TABLE 2-2: STRAP-IN OPTION – KSZ8041NL Pin Number Pin Name Type (Note 2-1) Pin Function

15 PHYAD2 Ipd/O The PHY Address is latched at power-up or reset and is configurable to any

value from 1 to 7. The default PHY Address is 00001. PHY Address bits [4:3] are always set to ‘00’.

14 PHYAD1 Ipd/O

13 PHYAD0 Ipu/O

18 CONFIG2 Ipd/O The CONFIG[2:0] strap-in pins are latched at power-up or reset and are

defined as follows:29 CONFIG1 Ipd/O

28 CONFIG0 Ipd/O

20 ISO Ipd/O

ISOLATE mode: Pull-up = Enable Pull-down (default) = Disable During power-up or reset, this pin value is latched into register 0h bit 10.

31 SPEED Ipu/O

SPEED mode: Pull-up (default) = 100 Mbps Pull-down = 10 Mbps During power-up or reset, this pin value is latched into register 0h bit 13 as the Speed Select, and also is latched into register 4h (Auto-Negotiation Advertisement) as the Speed capability support.

16 DUPLEX Ipu/O

DUPLEX mode: Pull-up (default) = Half Duplex Pull-down = Full Duplex During power-up or reset, this pin value is latched into register 0h bit 8 as the Duplex mode.

30 NWAYEN Ipu/O

Nway Auto-Negotiation Enable: Pull-up (default) = Enable Auto-Negotiation Pull-down = Disable Auto-Negotiation During power-up or reset, this pin value is latched into register 0h bit 12. CONFIG[2:0] Mode

000 MII (default)

001 RMII

010 Reserved - not used

011 Reserved - not used

100 MII 100 Mbps Preamble Restore

101 Reserved - not used

110 Reserved - not used

111 Reserved - not used

DS00002245B-page 12  2017 Microchip Technology Inc.

2.3 KSZ8041RNL Pin Description and Configuration

FIGURE 2-2: KSZ8041RNL 32-QFN PIN ASSIGNMENT (TOP VIEW) TABLE 2-3: KSZ8041RNL PIN DESCRIPTION Pin Number Pin Name Type ( Note 2-1) Pin Function 2 VDDPLL_1.8 P 1.8V Analog VDD Decouple with 1.0-µF and 0.1-µF capacitors to ground. 3 VDDA_3.3 P 3.3V Analog V DD Crystal Feedback for 25-MHz Crystal This pin is a no connect if an oscillator or an external clock source is used. 9X I I Crystal/Oscillator/External Clock Input

25 MHz ±50 ppm

Set physical transmit output current. Connect a 6.49-k resistor in parallel with a 100-pF capaci- tor to ground on this pin. See KSZ8041RNL reference schematics. LED0 / NWAYEN CONFIG1 INTRP LED1 / SPEED RX_ER / ISO MDIO MDC PHYAD0 PHYAD1 RXD1 / PHYAD2 RXD0 / DUPLEX VDDIO_3.3 CRS_DV / CONFIG2 REF_CLK GND VDDPLL_1.8 VDDA_3.3 RX- TX- TX+ XI REXT RX+ XO RST# TXD0 TX_EN NC NC NC TXD1 CONFIG0 9 10 11 12 13 14 15 16 2526272829303132 Paddle Ground (on bottom of chip)

 2017 Microchip Technology Inc. DS00002245B-page 13 KSZ8041NL/RNL This pin requires an external 4.7-k pull-up resistor. This pin is synchronous to the MDIO data interface. The pull-up/pull-down value is latched as PHYADDR[0] during power-up or reset. See Strap-In option – KSZ8041RNL for details. The pull-up/pull-down value is latched as PHYADDR[1] during power-up or reset. See Strap-In option – KSZ8041RNL for details.

15 RXD1 /

RMII mode: RMII Receive Data Output[1] (Note 2-2) Config mode: The pull-up/pull-down value is latched as PHYADDR[2] during power-up or reset. See Strap-In option – KSZ8041RNL for details.

16 RXD0 /

RMII mode: RMII Receive Data Output[0]] (Note 2-2) Config mode: Latched as DUPLEX (register 0h, bit 8) during power-up or reset. See Strap-In option – KSZ8041RNL for details. 17 VDDIO_3.3 P 3.3V Digital V DD

18 CRSDV /

RMII mode: Carrier Sense/Receive Data Valid Output Config mode: The pull-up/pull-down value is latched as CONFIG2 during power-up or reset. See Strap-In option – KSZ8041RNL for details.

19 REF_CLK O

50 MHz Clock Output

This pin provides the 50-MHz RMII reference clock output to the MAC. RXER / RX_ER / ISO Ipd/O RMII mode: Receive Error Output. Config mode: The pull-up/pull-down value is latched as ISO- LATE during power-up or reset. See Strap-In option – KSZ8041RNL for details. Interrupt Output: Programmable Interrupt Output Register 1Bh is the Interrupt Control/Status Register for pro- gramming the interrupt conditions and reading the interrupt status. Register 1Fh bit 9 sets the interrupt output to active low (default) or active high.

22 NC O No Connect

23 TX_EN I RMII Transmit Enable Input

24 TXD0 I RMII Transmit Data Input[0] (Note 2-3)

25 TXD1 I RMII Transmit Data Input[1] (Note 2-3)

26 NC I No Connect

27 NC I No Connect

The pull-up/pull-down value is latched as CONFIG0 during power-up or reset. See Strap-In option – KSZ8041RNL for details.

29 CONFIG1 Ipd/O

The pull-up/pull-down value is latched as CONFIG1 during power-up or reset. See Strap-In option – KSZ8041RNL for details. TABLE 2-3: KSZ8041RNL PIN DESCRIPTION (CONTINUED) Pin Number Pin Name Type ( Note 2-1) Pin Function

DS00002245B-page 14  2017 Microchip Technology Inc.

30 LED0 /

LED Output: Programmable LED0 Output Config mode: Latched as Auto-Negotiation Enable (register 0h, bit 12) during power-up or reset. See Strap-In option – KSZ8041RNL for details. The LED0 pin is programmable via register 1Eh bits [15:14] and is defined as follows: LED Mode = [00] LED Mode = [01] LED Mode = [10], [11] Reserved

31 LED1 /

LED Output: Programmable LED1 Output Config mode: Latched as SPEED (register 0h, bit 13) during power-up or reset. See Strap-In option – KSZ8041RNL for details. The LED1 pin is programmable via register 1Eh bits [15:14] and is defined as follows: LED Mode = [00] LED Mode = [01] LED Mode = [10], [11] Reserved TABLE 2-3: KSZ8041RNL PIN DESCRIPTION (CONTINUED) Pin Number Pin Name Type ( Note 2-1) Pin Function Link/Activity Pin State LED Definition No Link H OFF Link L ON Activity Toggle Blinking Link Pin State LED Definition No Link H OFF Link L ON Speed Pin State LED Definition 10BT H OFF 100BT L ON Activity Pin State LED Definition No Activity H OFF Activity Toggle Blinking

 2017 Microchip Technology Inc. DS00002245B-page 15 KSZ8041NL/RNL Note 2-1 P = Power supply Gnd = Ground I = Input O = Output I/O = Bi-directional Opu = Output with internal pull-up (40K ±30%) Ipu/O = Input with internal pull-up (40K ±30% ) during power-up/reset; output pin otherwise. Ipd/O = Input with internal pull-down (40K ±30%) during power-up/reset; output pin otherwise. Note 2-2 RMII Rx mode: The RXD[1:0] bits are synchronous with REF_CLK. For each clock period in which CRS_DV is asserted, two bits of re covered data are sent from the PHY. Note 2-3 RMII Tx mode: The TXD[ 1:0] bits are synchronous with REF_CL K. For each clock period in which TX_EN is asserted, two bits of data are received by the PHY from the MAC.

DS00002245B-page 16  2017 Microchip Technology Inc.

2.4 STRAP-IN OPTION – KSZ8041RNL

Pin strap-ins are latched during power-up or reset. In some systems, the MAC receive input pins may drive high during power-up or reset, and consequently cause the PHY strap-in pins on the RMII signals to be latched high. In this case, it is recommended to add 1K pull-downs on these PHY strap-in pins to ensure the PHY does not strap in to ISOLATE mode, or is not configured with an incorrect PHY Address. Note 2-1 Ipu/O = Input with internal pull-up (40K ± 30%) during power-up/reset; output pin otherwise. Ipd/O = Input with internal pull-down (40K ±30%) during power-up/reset; output pin otherwise. TABLE 2-4: STRAP-IN OPTION – KSZ8041RNL Pin Number Pin Name Type (Note 2-1) Pin Function value from 1 to 7. The default PHY Address is 00001. PHY Address bits [4:3] are always set to ‘00’. defined as follows:29 CONFIG1 Ipd/O ISOLATE mode: Pull-up = Enable Pull-down (default) = Disable During power-up or reset, this pin value is latched into register 0h bit 10. SPEED mode: Pull-up (default) = 100 Mbps Pull-down = 10 Mbps During power-up or reset, this pin value is latched into register 0h bit 13 as the Speed Select, and also is latched into register 4h (Auto-Negotiation Advertisement) as the Speed capability support. DUPLEX mode: Pull-up (default) = Half Duplex Pull-down = Full Duplex During power-up or reset, this pin value is latched into register 0h bit 8 as the Duplex mode. Nway Auto-Negotiation Enable: Pull-up (default) = Enable Auto-Negotiation Pull-down = Disable Auto-Negotiation During power-up or reset, this pin value is latched into register 0h bit 12. CONFIG[2:0] Mode

000 Reserved - not used

100 Reserved - not used

 2017 Microchip Technology Inc. DS00002245B-page 17 KSZ8041NL/RNL

3.0 FUNCTIONAL DESCRIPTION

The KSZ8041NL is a single 3.3V supply Fast Ethernet transceiver. It is fully compliant with the IEEE 802.3u specification. On the media side, the KSZ8041NL supports 10BASE-T and 100BASE-TX with HP auto MDI/MDI-X for reliable detec- tion of and correction for straight-through and crossover cables. The KSZ8041NL offers a choice of MII or RMII data interface connection with the MAC processor. The MII management bus option gives the MAC processor complete access to the KSZ8041NL control and status registers. Additionally, an interrupt pin eliminates the need for the processor to poll for PHY status change. Physical signal transmission and reception are enhanced through the use of patented analog circuitries that make the design more efficient and allow for lower power consumption and smaller chip die size. The KSZ8041RNL is an enhanced RMII version of the KSZ8041NL that does not require a 50-MHz system clock. It uses a 25-MHz crystal for its input reference clock and outputs a 50-MHz RMII reference clock to the MAC. 3.1 100BASE-TX Transmit The 100BASE-TX transmit function performs parallel-to-serial conversion, 4B/5B coding, scrambling, NRZ-to-NRZI con- version, and MLT3 encoding and transmission. The circuitry starts with a parallel-to-serial conversion, which converts the MII data from the MAC into a 125-MHz serial bit stream. The data and control stream is then converted into 4B/5B coding, followed by a scrambler. The serialized data is further converted from NRZ-to-NRZI format, and then transmitted in MLT3 current output. The output current is set by an external 6.49-kΩ 1% resistor for the 1:1 transformer ratio. It has typical rise or fall times of 4 ns and complies with the ANSI TP-PMD standard regard ing amplitude balance, overs hoot, and timing jitter. The wave-shaped 10BASE-T output drivers are also incorporated into the 100BASE-TX drivers. 3.2 100BASE-TX Receive The 100BASE-TX receiver function performs adaptive equalization, DC restoration, MLT3-to-NRZI conversion, data and clock recovery, NRZI-to-NRZ conversion, descrambling, 4B/5B decoding, and serial-to-parallel conversion. The receiving side starts with the equaliz ation filter to compensate for inter-symbol interference (ISI) over the twisted pair cable. Because the amplitude loss and phase distortion are functions of the cable length, the equalizer must adjust its characteristics to optimize performance. In this design, the variable equalizer makes an initial estimation based on comparisons of incoming signal strength against some known cable characteristics, and then tunes itself for optimiza- tion. This is an ongoing process and self-adjusts against environmental changes such as temperature variations. Next, the equalized signal goes through a DC restoration and data conversion block. The DC restoration circuit is used to compensate for the effect of baseline wander and to im prove the dynamic range. The differential data conversion circuit converts the MLT3 format back to NRZI. The slicing threshold is also adaptive. The clock recovery circuit extracts the 125-MHz clock from the edges of the NRZI signal. This recovered clock is then used to convert the NRZI signal into the NRZ format. This signal is sent through the descrambler followed by the 4B/5B decoder. Finally, the NRZ serial data is converted to the MII format and provided as the input data to the MAC.

3.3 PLL Clock Synthesizer

The KSZ8041NL/RNL generates 125-MHz, 25-MHz, and 20-MHz clocks for system timing. Internal clocks are gener- ated from an external 25-MHz crystal or oscillator. For the KSZ8041NL in RMII mode, these internal clocks are gener- ated from an external 50-MHz oscillator or system clock.

3.4 Scrambler/Descrambler (100BASE-TX only)

The purpose of the scrambler is to spread the power spectrum of the signal to reduce EMI and baseline wander. 3.5 10BASE-T Transmit The 10BASE-T drivers are incorporated wi th the 100BASE-TX drivers to allow for transmission using the same mag- netic. The drivers also perform internal wave-shaping and pre-emphasize, and output 10BASE-T signals with a typical amplitude of 2.5V peak. The 10BASE-T signals have harmonic contents that are at least 27 dB below the fundamental frequency when driven by an all-ones Manchester-encoded signal.

DS00002245B-page 18  2017 Microchip Technology Inc. 3.6 10BASE-T Receive On the receive side, input buffer and level detecting squelch circuits are employed. A differential input receiver circuit and a PLL performs the decoding function. The Manchester-e ncoded data stream is separated into clock signal and NRZ data. A squelch circuit rejects signals with levels less than 400 mV or with short pulse widths to prevent noise at the RX+ and RX- inputs from falsely triggering the decoder . When the input exceeds the squelch limit, the PLL locks onto the incoming signal and the KSZ8041NL/RNL decodes a data frame. The receive clock is kept active during idle periods in between data reception.

3.7 SQE and Jabber Function (10BASE-T only)

In 10BASE-T operation, a short pulse is put out on the COL pin after each frame is transmitted. This SQE Test is required as a test of the 10BASE-T transmit/receive path. If transmit enable (TXEN) is high for more than 20 ms (jabbering), the 10BASE-T transmitter is disabled and COL is asserted high. If TXEN is then driven low for more than 250 ms, the 10BASE-T transmitter is re-enabled and COL is deasserted (returns to low).

3.8 Auto-Negotiation

The KSZ8041NL/RNL conforms to the auto-negotiation protocol, defined in Clause 28 of the IEEE 802.3u specification. Auto-negotiation is enabled by either hardware pin strapping (pin 30) or software (register 0h bit 12). Auto-negotiation allows unshielded twisted pair (UTP) link partners to select the hig hest common mode of operation. Link partners advertise their capabilities to each other, and then compare their own capabilities with those they received from their link partners. The highest speed and duplex setting that is common to the two link partners is selected as the mode of operation. The following list shows the speed and duplex operation mode from highest to lowest:

• Priority 1: 100BASE-TX, full-duplex
• Priority 2: 100BASE-TX, half-duplex
• Priority 3: 10BASE-T, full-duplex
• Priority 4: 10BASE-T, half-duplex If auto-negotiation is not supported or the KSZ8041NL/RNL link partner is forced to bypass auto-negotiation, the KSZ8041NL/RNL sets its operating mode by observing the signal at its receiver. This is known as parallel detection, and this allows the KSZ8041NL/RNL to establish a link by listening for a fixed signal protocol in the absence of auto-nego- tiation advertisement protocol. The auto-negotiation link-up process is shown in the flow chart illustrated as Figure 3-1.

 2017 Microchip Technology Inc. DS00002245B-page 19 KSZ8041NL/RNL FIGURE 3-1: AUTO-NEGOTIATION FLOW CHART

3.9 MII Management (MIIM) Interface

The KSZ8041NL/RNL supports the IEEE 802.3 MII Management Interface, also known as the Management Data Input or Output (MDIO) Interface. This interface allows uppe r-layer devices to monitor and control the state of the KSZ8041NL/RNL. An external device with MIIM capability is used to read the PHY status or to configure the PHY set- The MIIM interface consists of the following:

• A physical connection that incorporates the clock line (MDC) and the data line (MDIO).
• A specific protocol that operates across the aforementioned physical connection that allows an external controller to communicate with one or more PHY devices. Each KSZ8041NL/RNL device is assigned a unique PHY address between 1 and 7 by its PHYAD[2:0] strapping pins. Additionally, every KSZ8041NL/RNL device supports the broadcast PHY address 0, as defined per the IEEE 802.3 specification, which can be used to read or write to a single KSZ8041NL/RNL device, or write to multiple KSZ8041NL/RNL devices simultaneously.
• A set of 16-bit MDIO registers. Registers [0:6] are required, and their functions are defined per the IEEE 802.3 specification. The additional registers are provided for expanded functionality. Start Auto Negotiation Force Link Setting Listen for 10BASE-T Link Pulses Listen for 100BASE-TX Idles Attempt Auto Negotiation Link Mode Set Bypass Auto Negotiation and Set Link Mode Link Mode Set ? Parallel Operation Join Flow N o Yes Yes No

DS00002245B-page 20  2017 Microchip Technology Inc. Table 3-1 shows the MII Management frame format for the KSZ8041NL/RNL.

3.10 Interrupt (INTRP)

INTRP (pin 21) is an optional interrupt signal that is used to inform the external controller that there has been a status update to the KSZ8041NL/RNL PHY register. Bits[15:8] of register 1Bh are the interrupt control bits and are used to enable and disable the conditions for asserting the INTRP signal. Bits[7:0] of register 1Bh are the interrupt status bits, and are used to indicate which interrupt conditions have occurred. The interrupt status bits are cleared after reading register 1Bh. Bit 9 of register 1Fh sets the interrupt level to active high or active low.

3.11 MII Data Interface (KSZ8041NL only)

The Media Independent Interface (MII) is specified in Clause 22 of the IEEE 802.3 specification. It provides a common interface between physical layer and MAC layer devices, and has the following key characteristics:

• Supports 10 Mbps and 100 Mbps data rates
• Uses a 25-MHz reference clock, sourced by the PHY
• Provides independent 4-bit wide (nibble) transmit and receive data paths
• Contains two distinct groups of signals: one for transmission and the other for reception By default, the KSZ8041NL is configured to MII mode after it is powered up or reset with the following:
• A 25-MHz crystal connected to XI, XO (pins 9, 8), or an external 25-MHz clock source (oscillator) connected to XI
• CONFIG[2:0] (pins 18, 29, 28) set to ‘000’ (default setting)

3.12 MII Signal Definition (KSZ8041NL only)

Table 3-2 describes the MII signals. Refer to Clause 22 of the IEEE 802.3 specification for detailed information. TABLE 3-1: MII MANAG EMENT FRAME FORMAT Preamble Start of Frame Read/ Write OP Code PHY Address Bits [4:0] REG Address Bits [4:0] TA Data Bits [15:0] Idle Read 32 1’s 01 10 00AAA RRRRR Z0 DDDDDDDD_DDDDDDDD Z Write 32 1’s 01 01 00AAA RRRRR 10 DDDDDDDD_DDDDDDDD Z TABLE 3-2: MII SIGNAL DEFINITION MII Signal Name Direction (with respect to PHY, KSZ8041NL signal) Direction (with respect to MAC) Description TXC Output Input Transmit Clock (2.5 MHz for 10 Mbps, 25 MHz for 100 Mbps) TXEN Input Output Transmit Enable TXD[3:0] Input Output Transmit Data [3:0] RXC Output Input Receive Clock (2.5 MHz for 10 Mbps, 25 MHz for 100 Mbps) RXDV Output Input Receive Data Valid RXD[3:0] Output Input Receive Data [3:0] RXER Output Input, or (not required) Receive Error CRS Output Input Carrier Sense COL Output Input Collision Detection

 2017 Microchip Technology Inc. DS00002245B-page 21 KSZ8041NL/RNL

3.12.1 TRANSMIT CLOCK (TXC)

TXC is sourced by the PHY. It is a continuous clock that provides the timing reference for Transmit Enable (TXEN) and Transmit Data [3:0] (TXD[3:0]). TXC is 2.5 MHz for 10 Mbps operation and 25 MHz for 100 Mbps operation.

3.12.2 TRANSMIT ENABLE (TXEN)

TXEN indicates the MAC is presenting nibbles on TXD[3:0] for transmission. It is asserted synchronously with the first nibble of the preamble and remains asserted while all nibbles to be transmitted are presented on the MII, and is negated prior to the first TXC following the final nibble of a frame. TXEN transitions synchronously with respect to TXC.

3.12.3 TRANSMIT DATA [3:0] (TXD[3:0])

TXD[3:0] transitions synchronously with respect to TXC. When TXEN is asserted, TXD[3:0] are accepted for transmis- sion by the PHY. TXD[3:0] is “00” to indicate idle when TXEN is deasserted. Values other than “00” on TXD[3:0] while TXEN is deasserted are ignored by the PHY.

3.12.4 RECEIVE CLOCK (RXC)

RXC provides the timing reference for RXDV, RXD[3:0], and RXER.

• In 10 Mbps mode, RXC is recovered from the line while the carrier is active. RXC is derived from the PHY’s refer- ence clock when the line is idle or the link is down.
• In 100 Mbps mode, RXC is continuously recovered from th e line. If the link is down, RXC is derived from the PHY’s reference clock. RXC is 2.5 MHz for 10 Mbps operation and 25 MHz for 100 Mbps operation.

3.12.5 RECEIVE DATA VALID (RXDV)

RXDV is driven by the PHY to indicate that the PHY is presenting recovered and decoded nibbles on RXD[3:0].

• In 10 Mbps mode, RXDV is asserted with the first nibble of the SFD (Start of Frame Delimiter), “5D”, and remains asserted until the end of the frame.
• In 100 Mbps mode, RXDV is asserted from the first nibb le of the preamble to the last nibble of the frame. RXDV transitions synchronously with respect to RXC.

3.12.6 RECEIVE DATA [3:0] (RXD[3:0])

RXD[3:0] transitions synchronously with respect to RXC. For each clock period in which RXDV is asserted, RXD[3:0] transfers a nibble of recovered data from the PHY.

3.12.7 RECEIVE ERROR (RXER)

RXER is asserted for one or more RXC periods to indicate that a Symbol Error (for example, a coding error that a PHY is capable of detecting, and that may otherwise be undetectable by the MAC sub-layer) was detected somewhere in the frame presently being transferred from the PHY. RXER transitions synchronously with respect to RXC. While RXDV is deasserted, RXER has no effect on the MAC.

3.12.8 CARRIER SENSE (CRS)

CRS is asserted and deasserted as follows:

• In 10 Mbps mode, CRS assertion is based on the recepti on of valid preambles. CRS deassertion is based on the reception of an end-of-frame (EOF) marker.
• In 100 Mbps mode, CRS is asserted w hen a start-of-stream delimiter, or /J/K symbol pair is detected. CRS is deasserted when an end-of-stream delimiter, or /T/R symbol pair is detected. Additionally, the PMA layer deasserts CRS if IDLE symbols are received without /T/R.

3.12.9 COLLISION (COL)

COL is asserted in half-duplex mode whenever the transmitt er and the receiver are simultaneously active on the line. This is used to inform the MAC that a collision has occurred during its transmission to the PHY. COL transitions asynchronously with respect to TXC and RXC.

DS00002245B-page 22  2017 Microchip Technology Inc.

3.13 Reduced MII (RMII) Data Interface

The Reduced Media Independent Interface (RMII) specifies a low pin count MII. It provides a common interface between physical layer and MAC layer devices, and has the following key characteristics:

• Supports 10 Mbps and 100 Mbps data rates
• Uses a 50-MHz reference clock
• Provides independent 2-bit wide (di-bit) transmit and receive data paths
• Contains two distinct groups of signals: one for transmission and the other for reception The KSZ8041NL is configured in RMII mode after it is powered up or reset with the following:
• A 500MHz reference clock connected to REFCLK (pin 9)
• CONFIG[2:0] (pins 18, 29, 28) set to ‘001’ The KSZ8041RNL is configured in RMII mode and outputs the 50-MHz RMII reference clock to the MAC on REF_CLK (pin 19) after it is powered up or reset with the following:
• A 25-MHz crystal connected to XI (pin 9) and XO (pin 8), or a 25-MHz reference clock connected to XI (pin 9)
• CONFIG[2:0] (pins 18, 29, 28) set to ‘001’ In RMII mode, unused MII signals, TXD[3:2] (pins 27, 26), are tied to ground.

3.14 RMII Signal Definition

Table 3-3 and Table 3-4 describe the RMII signals for KSZ8041NL and KSZ8041RNL. Refer to RMII specification for detailed information.

3.14.1 REFERENCE CLOCK (REF_CLK)

REF_CLK is a continuous 50-MHz clock that provides the timing reference for TX_EN, TXD[1:0], CRS_DV, RXD[1:0], and RX_ER. TABLE 3-3: RMII SIGNAL DESCRIPTION – KSZ8041NL RMII Signal Name Direction (with respect to PHY, KSZ8041NL signal) Direction (with respect to MAC) Description REF_CLK Input Input or Output Synchronous 50-MHz clock reference for receive, transmit, and control interface TX_EN Input Output Transmit Enable TXD[1:0] Input Output Transmit Data [1:0] CRS_DV Output Input Carrier Sense/Receive Data Valid RXD[1:0] Output Input Receive Data [1:0] RX_ER Output Input, or (not required) Receive Error TABLE 3-4: RMII SIGNAL DESCRIPTION – KSZ8041RNL RMII Signal Name Direction (with respect to PHY, KSZ8041RNL signal) Direction (with respect to MAC) Description REF_CLK Output Input Synchronous 50-MHz clock reference for receive, transmit, and control interface TX_EN Input Output Transmit Enable TXD[1:0] Input Output Transmit Data [1:0] CRS_DV Output Input Carrier Sense/Receive Data Valid RXD[1:0] Output Input Receive Data [1:0] RX_ER Output Input, or (not required) Receive Error

 2017 Microchip Technology Inc. DS00002245B-page 23 KSZ8041NL/RNL The KSZ8041NL inputs the 50-MHz REF_CLK from the MAC or system board. The KSZ8041RNL generates the 50MHz RMII REF_CLK and outputs it to the MAC.

3.14.2 TRANSMIT ENABLE (TX_EN)

TX_EN indicates that the MAC is presenting di-bits on TXD[1:0] for transmission. It is asserted synchronously with the first nibble of the preamble and remains asserted while all di-bits to be transmitted are presented on the RMII, and is negated prior to the first REF_CLK following the final di-bit of a frame. TX_EN transitions synchronously with respect to REF_CLK.

3.14.3 TRANSMIT DATA [1:0] (TXD[1:0])

TXD[1:0] transitions synchronously with respect to REF_CLK. When TX_EN is asserted, TXD[1:0] is accepted for trans- mission by the PHY . TXD[1:0] is “00” to indicate idle when TX_EN is deasserted. Values other than “00” on TXD[1:0] while TX_EN is deasserted are ignored by the PHY.

3.14.4 CARRIER SENSE/RECEIVE DATA VALID (CRS_DV)

CRS_DV is asserted by the PHY when the receive medium is non-idle. It is asserted asynchronously on detection of a carrier. This is when a squelch is passed in 10 Mbps mode, and when two non-contiguous zeros in 10 bits are detected in 100 Mbps mode. Loss of carrier results in the deassertion of CRS_DV. As long as carrier detection criteria are met, CRS_DV remain s asserted continuously from the first recovered di-bit of the frame through the final recovered di-bit, and it is negated prior to the first REF_CLK that follows the final di-bit. The data on RXD[1:0] is considered valid once CRS_DV is asserted. However, since the assertion of CRS_DV is asynchro- nous relative to REF_CLK, the data on RXD[1:0] is “00” until proper receive signal decoding takes place.

3.14.5 RECEIVE DATA [1:0] (RXD[1:0])

RXD[1:0] transitions synchronously to REF_CLK. For each clock period in which CRS_DV is asserted, RXD[1:0] trans- fers two bits of recovered data from the PHY. RXD[1:0] is “00” to indicate idle when CRS_DV is deasserted. Values other than “00” on RXD[1:0] while CRS_DV is deasserted are ignored by the MAC.

3.14.6 RECEIVE ERROR (RX_ER)

RX_ER is asserted for one or more REF_CLK periods to indicate that a Symbol Error (for example,. a coding error that a PHY is capable of detecting, and that may otherwise be undetectable by the MAC sub-layer) was detected somewhere in the frame presently being transferred from the PHY . RX_ER transitions synchronously with respect to REF_CLK. While CRS_DV is deasserted, RX_ER has no effect on the MAC.

3.14.7 COLLISION DETECTION

The MAC regenerates the COL signal of the MII from TX_EN and CRS_DV.

DS00002245B-page 24  2017 Microchip Technology Inc.

3.15 RMII Signal Diagram

The KSZ8041NL RMII pin connections to the MAC are shown in Figure 3-2. FIGURE 3-2: KSZ8041NL RMII INTERFACE FIGURE 3-3: KSZ8041R NL RMII INTERFACE RMII MACKSZ8041NL CRS_DV RXD[1:0] RX_ER REF_CLK CRS_DV RX_ER RXD[1:0] TX_EN TXD[1:0] TX_EN TXD[1:0] REFCLK

50 MHz

REF_CLK KSZ8041RNL CRS_DV RXD[1:0] RX_ER REF_CLK CRS_DV RX_ER RXD[1:0] TX_EN TXD[1:0] TX_EN TXD[1:0] XO XI

25 MHz

 2017 Microchip Technology Inc. DS00002245B-page 25 KSZ8041NL/RNL

3.16 HP Auto MDI/MDI-X

HP Auto MDI/MDI-X configuration eliminates the confusion of whether to use a straight cable or a crossover cable between the KSZ8041NL/RNL and its link partner. This feature allows the KSZ8041NL/RNL to use either type of cable to connect with a link partner that is in either MDI or MDI-X mode. The auto-sense function detects transmit and receive pairs from the link partner, and then assigns transmit and receive pairs of the KSZ8041NL/RNL accordingly. HP Auto MDI/MDI-X is enabled by default. Writing “1” to register 1F bit 13 disables HP Auto MDI/MDL-X. Register 1F bit 14 selects MDI and MDI-X mode if HP Auto MDI/MDI-X is disabled. An isolation transformer with symmetrical transmit and receive data paths is recommended to support auto MDI/MDI-X. The IEEE 802.3 Standard MDI and MDI-X is defined in Table 3-5. TABLE 3-5: MDI/MDI- X PIN DESCRIPTION MDI MDI-X RJ-45 Pin Signal RJ-45 Pin Signal

1 TD+ 1 RD+

2T D –2R D –

3 RD+ 3 TD+

6 RD– 6 TD–

DS00002245B-page 26  2017 Microchip Technology Inc.

3.16.1 STRAIGHT CABLE

A straight cable connects an MDI device to an MDI-X device, or an MDI-X device to an MDI device. Figure 3-4 depicts a typical straight cable connection between a NIC card (MDI) and a switch, or hub (MDI-X). FIGURE 3-4: TYPICAL STRAIGHT CABLE CONNECTION

3.16.2 CROSSOVER CABLE

A crossover cable connects an MDI device to another MDI device, or an MDI-X device to another MDI-X device. Table 3-4 depicts a typical crossover cable connection between two switches or hubs (two MDI-X devices). FIGURE 3-5: TYPICAL CROSSOVER CABLE CONNECTION

 2017 Microchip Technology Inc. DS00002245B-page 27 KSZ8041NL/RNL

3.17 Power Management

The KSZ8041NL/RNL offers the following two power management modes:

• Power Saving Mode This mode is used to reduce power consumption when the cable is unplugged. It is in effect when the auto-negoti- ation mode is enabled, the cable is disconnected, and register 1F bit 10 is set to 1. Under the power saving mode, the KSZ8041NL/RNL shuts down all transceiver blocks, except for transmitter, energy detect, and PLL circuits. Additionally, for the KSZ8041NL in MII mode, the RXC clock output is disabled. RXC clock is enabled after the cable is connected and a link is established. Power-saving mode is disabled by writing “0” to register 1F bit 10.
• Power-Down Mode This mode is used to power down the entire KSZ8041NL/RNL device when it is not in use. Power down mode is enabled by writing “1” to register 0 bit 11. In the power down state, the KSZ8041NL/RNL disables all internal func- tions, except for the MII management interface.

3.18 Reference Clock Connection Options

A crystal or clock source, such as an oscillator, is used to provide the reference clock for the KSZ8041NL/RNL. Figure 3-6 illustrates how to connect the 25-MHz crystal and oscillator reference clock. FIGURE 3-6: 25-MHZ CRYSTAL/OSCILLATOR REFERENCE CLOCK For the KSZ8041NL, Figure 3-7 illustrates how to connect the 50-MHz oscillator reference clock for RMII mode. FIGURE 3-7: 50-MHZ OSCILLATOR REFE RENCE CLOCK FOR KSZ8041NL RMII MODE

3.19 Reference Circuit for Power and Ground Connections

The KSZ8041NL/RNL is a single 3.3V supply device with a built-in 1.8V low-noise regulator. The power and ground con- nections are shown in Figure 3-8 and Table 3-6. 25MHz OSC +/-50ppm NC NC XI XO XI XO pF 22pF 22pF 22pF 25MHz XTAL +/-50ppm 50MHz OSC +/-50ppm NC NC REFCLK XO

DS00002245B-page 28  2017 Microchip Technology Inc. FIGURE 3-8: KSZ8041NL/RNL POWER AND GROUND CONNECTIONS TABLE 3-6: KSZ8041NL/RNL POWER PIN DESCRIPTION Power Pin Pin Number Description VDDPLL_1.8 2 Decouple with 1.0 µF and 0.1 µF capacitors to ground. VDDA_3.3 3 Connect to the board’s 3.3V supply through ferrite bead. VDDIO_3.3 17 Connect to the board’s 3.3V supply. VDDIO_3.3 KSZ8041NL/RNL VDDPLL_1.8 0.1uF 1.0uF VIN GND VOUT 1.8V Low Noise Regulator (integrated) 3.3V VDDA_3.3 Ferrite Bead Paddle 0.1uF 22uF 0.1uF 22uF

 2017 Microchip Technology Inc. DS00002245B-page 29 KSZ8041NL/RNL

4.0 REGISTERS

4.1 Register Map

Table 4-1 summarizes the register map. TABLE 4-1: REGISTER MAP Register Number (Hex) Description 0h Basic Control 1h Basic Status 2h PHY Identifier 1 3h PHY Identifier 2 4h Auto-Negotiation Advertisement 5h Auto-Negotiation Link Partner Ability 6h Auto-Negotiation Expansion 7h Auto-Negotiation Next Page 8h Link Partner Next Page Ability 9h – 13h Reserved 14h MII Control 15h RXER Counter 16h – 1Ah Reserved 1Bh Interrupt Control/Status 1Ch – 1Dh Reserved 1Eh PHY Control 1 1Fh PHY Control 2

DS00002245B-page 30  2017 Microchip Technology Inc.

4.2 Register Descriptions

Table 4-2 provides a list of supported registers and their descriptions. TABLE 4-2: REGISTER DESCRIPTIONS Address Name Description Mode (Note 4-1) Default Register 0h – Basic Control

0.15 Reset

1 = Software reset 0 = Normal operation This bit is self-cleared after a ‘1’ is written to it. RW/SC 0

0.14 Loop-Back 1 = Loop-back mode

0 = Normal operation RW 0

0.13 Speed Select (LSB)

1 = 100 Mbps 0 = 10 Mbps This bit is ignored if auto-negotia- tion is enabled (register 0.12 = 1). RW Set by SPEED strapping pin. See Table 2-2 and Table 2-4 for details.

0.12 Auto-Negotiation Enable

1 = Enable auto-negotiation process 0 = Disable auto-negotiation process If enabled, auto-negotiation result overrides the settings in register 0.13 and 0.8. RW Set by NWAYEN strap- ping pin. See Table 2-2 and Table 2-4 for details.

0.11 Power Down 1 = Power-down mode

0 = Normal operation RW 0

0.10 Isolate

1 = Electrical isolation of PHY from MII and TX+/TX- 0 = Normal operation RW Set by ISO strapping pin. See Table 2-2 and Table 2-4 for details.

0.9 Restart Auto-Negotiation

1 = Restart auto-negotiation process 0 = Normal operation This bit is self-cleared after a ‘1’ is written to it. RW/SC 0

0.8 Duplex Mode 1 = Full-duplex

0 = Half-duplex RW Inverse of DUPLEX strapping pin value. See Table 2-2 and Table 2-4 for details.

0.7 Collision Test 1 = Enable COL test

0 = Disable COL test RW 0 0.6:1 Reserved RO 000_000

0.0 Disable

0 = Enable transmitter 1 = Disable transmitter RW 0 Register 1h – Basic Status 1.15 100BASE-T4 1 = T4 capable 0 = Not T4 capable RO 0 1.14 100BASE-TX Full Duplex 1 = Capable of 100 Mbps full- duplex 0 = Not capable of 100 Mbps full- duplex RO 1

 2017 Microchip Technology Inc. DS00002245B-page 31 KSZ8041NL/RNL 1.13 100BASE-TX Half Duplex 1 = Capable of 100 Mbps half- duplex 0 = Not capable of 100 Mbps half-duplex RO 1 1.12 10BASE-T Full Duplex 1 = Capable of 10 Mbps full- duplex 0 = Not capable of 10 Mbps full- duplex RO 1 1.11 10BASE-T Half Duplex 1 = Capable of 10 Mbps half- duplex 0 = Not capable of 10 Mbps half- duplex RO 1 1.10:7 Reserved — RO 0000

1.6 No Preamble 1 = Preamble suppression

0 = Normal preamble RO 1

1.5 Auto-Negotiation Complete

1 = Auto-negotiation process completed 0 = Auto-negotiation process not completed RO 0

1.4 Remote Fault 1 = Remote fault

0 = No remote fault RO/LH 0

1.3 Auto-Negotiation Ability

1 = Capable to perform auto- negotiation 0 = Not capable to perform auto- negotiation RO 1

1.2 Link Status 1 = Link is up

0 = Link is down RO/LL 0

1.1 Jabber Detect

1 = Jabber detected 0 = Jabber not detected (default is low) RO/LH 0

1.0 Extended Capability 1 = Supports extended capabili-

Register 2h – PHY Identifier 1

2.15.0 PHY ID Number

Assigned to the 3rd through 18th bits of the Organizationally Unique Identifier (OUI). Kendin Communication’s OUI is 0010A1 (hex) RO 0022h Register 3h – PHY Identifier 2 3.15:10 PHY ID Number Assigned to the 19th through 24th bits of the Organizationally Unique Identifier (OUI). Kendin Communication’s OUI is 0010A1 (hex) RO 0001_01 3.9:4 Model Number Six bit manufacturer’s model number RO 01_0001 3.3:0 Revision Number Four bit manufacturer’s revision number RO Indicates silicon revision TABLE 4-2: REGISTER DESCRIPTIONS (CONTINUED) Address Name Description Mode (Note 4-1) Default

DS00002245B-page 32  2017 Microchip Technology Inc. Register 4h – Auto-Negotiation Advertisement

4.15 Next Page 1 = Next page capable

0 = No next page capability RW 0

4.14 Reserved — RO 0

4.13 Remote Fault 1 = Remote fault supported

0 = No remote fault RW 0

4.12 Reserved — RO 0

4.11:10 Pause [00] = No PAUSE [10] = Asymmetric PAUSE [01] = Symmetric PAUSE [11] = Asymmetric & Symmetric PAUSE RW 0 0 4.9 100BASE-T4 1 = T4 capable 0 = No T4 capability RO 0 4.8 100BASE-TX Full-Duplex 1 = 100 Mbps full-duplex capable 0 = No 100 Mbps full-duplex capability RW Set by SPEED strapping pin. See Table 2-2 and Table 2-4 for details. 4.7 100BASE-TX Half-Duplex 1 = 100 Mbps half-duplex capa- ble 0 = No 100 Mbps half-duplex capability RW Set by SPEED strapping pin. See Table 2-2 and Table 2-4 for details. 4.6 10BASE-T Full-Duplex 1 = 10 Mbps full-duplex capable 0 = No 10 Mbps full-duplex capa- bility RW 1 4.5 10BASE-T Half-Duplex 1 = 10 Mbps half-duplex capable 0 = No 10 Mbps half-duplex capability RW 1 4.4:0 Selector Field [0000 1] = IEEE 802.3 RW 0_0001 Register 5h – Auto-Negotiation Link Partner Ability

5.15 Next Page 1 = Next page capable

0 = No next page capability RO 0

5.14 Acknowledge

1 = Link code word received from partner 0 = Link code word not yet received RO 0

5.13 Remote Fault 1 = Remote fault detected

0 = No remote fault RO 0

5.12 Reserved — RO 0

5.11:10 Pause [00] = No PAUSE [10] = Asymmetric PAUSE [01] = Symmetric PAUSE [11] = Asymmetric & Symmetric PAUSE RO 00 5.9 100BASE-T4 1 = T4 capable 0 = No T4 capability RO 0 5.8 100BASE-TX Full-Duplex 1 = 100 Mbps full-duplex capable 0 = No 100 Mbps full-duplex capability RO 0 TABLE 4-2: REGISTER DESC RIPTIONS (CONTINUED) Address Name Description Mode (Note 4-1) Default

 2017 Microchip Technology Inc. DS00002245B-page 33 KSZ8041NL/RNL 5.7 100BASE-TX Half-Duplex 1 = 100 Mbps half-duplex capable 0 = No 100 Mbps half-duplex capability RO 0 5.6 10BASE-T Full-Duplex 1 = 10 Mbps full-duplex capable 0 = No 10 Mbps full-duplex capability RO 0 5.5 10BASE-T Half-Duplex 1 = 10 Mbps half-duplex capable 0 = No 10 Mbps half-duplex capability RO 0 5.4:0 Selector Field [0000 1] = IEEE 802.3 RO 0_0001 Register 6h – Auto-Negotiation Expansion 6.15:5 Reserved — RO 0000_0000_000

6.4 Parallel Detection Fault

1 = Fault detected by parallel detection 0 = No fault detected by parallel detection. RO/LH 0

6.3 Link Partner Next Page Able

1 = Link partner has next page capability 0 = Link partner does not have next page capability RO 0

6.2 Next Page Able

1 = Local device has next page capability 0 = Local device does not have next page capability RO 1

6.1 Page Received 1 = New page received

0 = New page not received yet RO/LH 0

6.0 Link Partner Auto-Negotia-

1 = Link partner has auto- negotiation capability 0 = Link partner does not have auto-negotiation capability RO 0 Register 7h – Auto-Negotiation Next Page

7.15 Next Page

1 = Additional next page(s) will follow 0 = Last page RW 0

7.14 Reserved — RO 0

7.13 Message Page 1 = Message page

0 = Unformatted page RW 1

7.12 Acknowledge2 1 = Will comply with message

0 = Cannot comply with message RW 0

7.11 Toggle

1 = Previous value of the trans- mitted link code word equaled logic one 0 = Logic zero RO 0 7.10:0 Message Field 11-bit wide field to encode 2048 messages RW 000_0000_0001 TABLE 4-2: REGISTER DESCRIPTIONS (CONTINUED) Address Name Description Mode (Note 4-1) Default

DS00002245B-page 34  2017 Microchip Technology Inc. Register 8h – Link Partner Next Page Ability

8.15 Next Page

1 = Additional Next Page(s) will follow 0 = Last page RO 0

8.14 Acknowledge

1 = Successful receipt of link word 0 = No successful receipt of link word RO 0

8.13 Message Page 1 = Message page

0 = Unformatted page RO 0

8.12 Acknowledge2

1 = Able to act on the information 0 = Not able to act on the information RO 0

8.11 Toggle

1 = Previous value of transmitted link code word equal to logic zero 0 = Previous value of transmitted link code word equal to logic one RO 0 8.10:0 Message Field — RO 000_0000_0000 Register 14h – MII Control 14.15:8 Reserved — RO 0000_0000 14.7 100BASE-TX Preamble Restore 1 = Restore received preamble to MII output (random latency) 0 = Consume 1-byte preamble before sending frame to MII output for fixed latency RW 0 or 1 (if CONFIG[2:0] = 100) See Table 2-2 and Table 2-4 for details. 14.6 10BASE-T Preamble Restore 1 = Restore received preamble to MII output 0 = Remove all 7-bytes of preamble before sending frame (starting with SFD) to MII output RW 0 14.5:0 Reserved — RO 00_0001 Register 15h – RXER Counter 15.15:0 RXER Counter Receive error counter for Symbol Error frames RO/SC 000h Register 1Bh – Interrupt Control/Status 1b.15 Jabber Interrupt Enable 1 = Enable Jabber Interrupt 0 = Disable Jabber Interrupt RW 0 1b.14 Receive Error Interrupt Enable 1 = Enable Receive Error Interrupt 0 = Disable Receive Error Interrupt RW 0 1b.13 Page Received Interrupt Enable 1 = Enable Page Received Interrupt 0 = Disable Page Received Interrupt RW 0 1b.12 Parallel Detect Fault Inter- rupt Enable 1 = Enable Parallel Detect Fault Interrupt 0 = Disable Parallel Detect Fault Interrupt RW 0 TABLE 4-2: REGISTER DESC RIPTIONS (CONTINUED) Address Name Description Mode (Note 4-1) Default

 2017 Microchip Technology Inc. DS00002245B-page 35 KSZ8041NL/RNL 1b.11 Link Partner Acknowledge Interrupt Enable 1 = Enable Link Partner Acknowledge Interrupt 0 = Disable Link Partner Acknowledge Interrupt RW 0 1b.10 Link Down Interrupt Enable 1= Enable Link Down Interrupt 0 = Disable Link Down Interrupt RW 0 1b.9 Remote Fault Interrupt Enable 1 = Enable Remote Fault Interrupt 0 = Disable Remote Fault Interrupt RW 0 1b.8 Link Up Interrupt Enable 1 = Enable Link Up Interrupt 0 = Disable Link Up Interrupt RW 0 1b.7 Jabber Interrupt 1 = Jabber occurred 0 = Jabber did not occur RO/SC 0 1b.6 Receive Error Interrupt 1 = Receive Error occurred 0 = Receive Error did not occur RO/SC 0 1b.5 Page Receive Interrupt 1 = Page Receive occurred 0 = Page Receive did not occur RO/SC 0 1b.4 Parallel Detect Fault Interrupt 1 = Parallel Detect Fault occurred 0 = Parallel Detect Fault did not occur RO/SC 0 1b.3 Link Partner Acknowledge Interrupt 1= Link Partner Acknowledge occurred 0= Link Partner Acknowledge did not occur RO/SC 0 1b.2 Link Down Interrupt 1= Link Down occurred 0= Link Down did not occur RO/SC 0 1b.1 Remote Fault Interrupt 1= Remote Fault occurred 0= Remote Fault did not occur RO/SC 0 1b.0 Link Up Interrupt 1= Link Up occurred 0= Link Up did not occur RO/SC 0 Register 1Eh – PHY Control 1 1e:15:14 LED mode [00] = LED1 : Speed LED0 : Link/Activity [01] = LED1 : Activity LED0 : Link [10], [11] = Reserved RW 00 1e.13 Polarity 0 = Polarity is not reversed 1 = Polarity is reversed RO — 1e.12 Reserved — RO 0 1e.11 MDI/MDI-X State 0 = MDI 1 = MDI-X RO — 1e:10:8 Reserved — — — 1e:7 Remote loopback 0 = Normal mode 1 = Remote (analog) loop back is enabled RW 0 TABLE 4-2: REGISTER DESCRIPTIONS (CONTINUED) Address Name Description Mode (Note 4-1) Default

DS00002245B-page 36  2017 Microchip Technology Inc. 1e:6:0 Reserved — — — Register 1Fh – PHY Control 2 1f:15 HP_MDIX 0 = Auto MDI/MDI-X mode 1 = HP Auto MDI/MDI-X mode RW 1 1f:14 MDI/MDI-X Select When Auto MDI/MDI-X is disabled, 0 = MDI mode Transmit on TX+/- (pins 7, 6) and Receive on RX+/- (pins 5, 4) 1 = MDI-X mode Transmit on RX+/- (pins 5,4) and Receive on TX+/- (pins 7, 6) RW 0 1f:13 Pair Swap Disable 1 = Disable auto MDI/MDI-X 0 = Enable auto MDI/MDI-X RW 0 1f.12 Energy Detect 1 = Presence of signal on RX+/- analog wire pair 0 = No signal detected on RX+/- RO 0 1f.11 Force Link 1 = Force link pass 0 = Normal link operation This bit bypasses the control logic and allows the transmitter to send a pattern even if there is no link. RW 0 Register 1Fh – PHY Control 2 (Continued) 1f.10 Power Saving 1 = Enable power saving 0 = Disable power saving If power saving mode is enabled and the cable is disconnected, the RXC clock output (in MII mode) is disabled. RXC clock is enabled after the cable is con- nected and a link is established. RW 0 1f.9 Interrupt Level 1 = Interrupt pin active high 0 = Interrupt pin active low RW 0 1f.8 Enable Jabber 1 = Enable jabber counter 0 = Disable jabber counter RW 1 1f.7 Auto-Negotiation Complete 1 = Auto-negotiation process completed 0 = Auto-negotiation process not completed RW 0 1f.6 Enable Pause (Flow Con- trol) 1 = Flow control capable 0 = No flow control capability RO 0 1f.5 PHY Isolate 1 = PHY in isolate mode 0 = PHY in normal operation RO 0 1f.4:2 Operation Mode Indication [000] = Still in auto-negotiation [001] = 10 BASE-T half-duplex [010] = 100 BASE-TX half-duplex [011] = Reserved [101] = 10 BASE-T full-duplex [110] = 100 BASE-TX full-duplex [111] = Reserved RO 000 TABLE 4-2: REGISTER DESC RIPTIONS (CONTINUED) Address Name Description Mode (Note 4-1) Default

 2017 Microchip Technology Inc. DS00002245B-page 37 KSZ8041NL/RNL Note 4-1 RW = Read/Write RO = Read only SC = Self-cleared LH = Latch high LL = Latch low 1f.1 Enable SQE test 1 = Enable SQE test 0 = Disable SQE test RW 0 1f.0 Disable Data Scrambling 1 = Disable scrambler 0 = Enable scrambler RW 0 TABLE 4-2: REGISTER DESCRIPTIONS (CONTINUED) Address Name Description Mode (Note 4-1) Default

DS00002245B-page 38  2017 Microchip Technology Inc.

5.0 OPERATIONAL CHARACTERISTICS

5.1 Absolute Maximum Ratings ( Note 5-1)

5.2 Operating Ratings ( Note 5-3)

Note 5-1 Exceeding the absolute maximum rating may damage the device. Stresses greater than the absolute maximum rating may cause permanent damage to th e device. Operation of the device at these or any other conditions above those specified in the operating sectio ns of this specification is not implied. Maximum conditions for ex tended periods may affect reliability. Note 5-2 Devices are ESD sensitive. Handling precauti ons are recommended. Human body model, 1.5 k Ω in series with 100 pF. Note 5-3 The device is not guaranteed to f unction outside its operating rating.

 2017 Microchip Technology Inc. DS00002245B-page 39 KSZ8041NL/RNL

6.0 ELECTRICAL CHARACTERISTICS

Note 6-1 Current consumption is for the single 3.3V supply KSZ8041NL/RNL device only, and includes the 1.8V supply voltage (VDDPLL_1.8) that is provided by the KSZ8041NL/RNL. The PHY port’s transformer consumes an additional 45 mA @ 3.3V for 100BASE-TX an d 70 mA @ 3.3V for 10BASE-T. Note 6-2 TA = 25°C. Specification for packaged product only. TABLE 6-1: ELECTRICAL CHARACTERISTICS ( Note 6-1, Note 6-2) Symbol Parameter Condition Min. Typ. Max. Units Supply Current IDD1 100BASE-TX Chip only (no transformer); Full-duplex traffic @ 100% utilization — 53.0 — mA IDD2 10BASE-T Chip only (no transformer); Full-duplex traffic @ 100% utilization — 38.0 — mA IDD3 Power-Saving Mode Ethernet cable discon- nected (reg. 1F.10 = 1) — 32.0 — mA IDD4 Power-Down Mode Software power-down (reg. TTL Inputs VIH Input High Voltage — 2.0 — — V VIL Input Low Voltage — — — 0.8 V IIN Input Current V IN = GND ~ VDDIO — –10 10 µA TTL Outputs V OH Output High Voltage I OH = 4m A 2 . 4 — — V VOL Output Low Voltage I OL = 4 mA — — 0.4 V |Ioz| Output Tri-State Leakage — — — 10 µA LED Outputs ILED Output Drive Current Each LED pin (LED0, LED1) —8— m A 100BASE-TX Transmit (measured differentially after 1:1 transformer) VO Peak Differential Output Voltage 100 termination across differential output 0.95 — 1.05 V VIMB Output Voltage Imbalance 100 termination across differential output —— 2 % tr, tf Rise/Fall Time — 3 — 5 ns Rise/Fall Time Imbalance — 0 — 0.5 ns Duty Cycle Distortion — — — + 0.25 ns Overshoot — — — 5 % VSET Reference Voltage of ISET — — 0.65 — V — Output Jitter Peak-to-peak — 0.7 1.4 ns 10BASE-T Transmit (measured differentially after 1:1 transformer) VP Peak Differential Output Voltage 100 termination across differential output 2.2 — 2.8 V — Jitter Added Peak-to-peak — — 3.5 ns tr, tf Rise/Fall Time — — 25 — ns 10BASE-T Receive VSQ Squelch Threshold 5 MHz square wave — 400 — mV

DS00002245B-page 40  2017 Microchip Technology Inc.

7.0 TIMING DIAGRAMS

7.1 MII SQE Timing

FIGURE 7-1: MII SQE TIMING (10BASE-T)

7.2 MII Transmit Timing (10BASE-T)

FIGURE 7-2: MII TRANSMI T TIMING (10BASE-T) TABLE 7-1: MII SQE TIMING (10BASE-T) PARAMETERS Timing Parameter Description Min. Typ. Max. Unit tP TXC Period — 400 — ns tWL TXC Pulse Width Low — 200 — ns tWH TXC Pulse Width High — 200 — ns tSQE COL (SQE) Delay After TXEN De-Asserted — 2.5 — us tSQEP COL (SQE) Pulse Duration — 1.0 — us TXC tSQE COL tSQEP TXEN tWL tWH tP TXC tHD2tSU2TXEN TXD[3:0] tSU1 tHD1 CRS tCRS2 tCRS1 tWH tWL tP

 2017 Microchip Technology Inc. DS00002245B-page 41 KSZ8041NL/RNL

7.3 MII Receive Timing (10BASE-T)

FIGURE 7-3: MII RECEIVE TIMING (10BASE-T) TABLE 7-2: MII TRANSMIT TIMI NG (10BASE-T) PARAMETERS Timing Parameter Description Min. Typ. Max. Units tP TXC Period — 400 — ns tWL TXC Pulse Width Low — 200 — ns tWH TXC Pulse Width High — 200 — ns tSU1 TXD[3:0] Setup to Rising Edge of TXC 10 —— ns tSU2 TXEN Setup to Rising Edge of TXC 10 —— ns tHD1 TXD[3:0] Hold from Rising Edge of TXC 0 —— ns tHD2 TXEN Hold from Rising Edge of TXC 0 —— ns tCRS1 TXEN High to CRS Asserted Latency — 160 — ns tCRS2 TXEN Low to CRS De-Asserted Latency — 510 — ns TABLE 7-3: MII RECEIVE TIMING (10BASE-T) PARAMETERS Timing Parameter Description Min. Typ. Max. Unit tP RXC Period — 400 — ns tWL RXC Pulse Width Low — 200 — ns tWH RXC Pulse Width High — 200 — ns tOD (RXD[3:0], RXER, RXDV) Output Delay from Rising Edge of RXC 182 — 225 ns tRLAT CRS to (RXD[3:0], RXER, RXDV) Latency — 6.5 — µs RXD[3:0] RXER CRS RXDV tRLAT tOD RXC tWH tWL tP

DS00002245B-page 42  2017 Microchip Technology Inc.

7.4 MII Transmit Timing (100BASE-TX)

FIGURE 7-4: MII TRANSMI T TIMING (100BASE-TX) TABLE 7-4: MII TRANSMIT TIMING (100BASE-TX) PARAMETERS Timing Parameter Description Min. Typ. Max. Unit tP TXC Period — 40 — ns tWL TXC Pulse Width Low — 20 — ns tWH TXC Pulse Width High — 20 — ns tSU1 TXD[3:0] Setup to Rising Edge of TXC 10 —— ns tSU2 TXEN Setup to Rising Edge of TXC 10 —— ns tHD1 TXD[3:0] Hold from Rising Edge of TXC 0 —— ns tHD2 TXEN Hold from Rising Edge of TXC 0 —— ns tCRS1 TXEN High to CRS Asserted Latency — 34 — ns tCRS2 TXEN Low to CRS De-Asserted Latency — 33 — ns TXC tSU2 TXEN tHD2 TXD[3:0] tSU1 CRS tCRS2 tCRS1 Data In tHD1 tWL tWH tP

 2017 Microchip Technology Inc. DS00002245B-page 43 KSZ8041NL/RNL

7.5 MII Receive Timing (100BASE-TX)

FIGURE 7-5: MII RECEIVE TIMING (100BASE-TX) TABLE 7-5: MII RECEIVE TIMING (100BASE-TX) PARAMETERS Timing Parameter Description Min. Typ Max. Units tP RXC Period — 40 — ns tWL RXC Pulse Width Low — 20 — ns tWH RXC Pulse Width High 20 — ns tOD (RXD[3:0], RXER, RXDV) Output Delay from Rising Edge of RXC 19 — 25 ns tRLAT CRS to RXDV Latency — 140 — ns CRS to RXD[3:0] Latency — 52 — ns CRS to RXER Latency — 60 — ns RXD[3:0] RXER CRS RXDV tRLAT tOD RXC tWH tWL tP

DS00002245B-page 44  2017 Microchip Technology Inc.

7.6 RMII Timing

FIGURE 7-6: RMII TIMING – DATA RECEIVED FROM RMII FIGURE 7-7: RMII TIMING – DATA INPUT TO RMII TABLE 7-6: RMII TIMING PARAMETERS – KSZ8041NL Timing Parameter Description Min. Typ Max. Units tcyc Clock Cycle — 20 — ns t1 Setup Time 4 — — ns t2 Hold Time 2 — — ns tod Output Delay 3 — 9 ns TABLE 7-7: RMII TIMING PARAMETERS – KSZ8041RNL Timing Parameter Description Min. Typ Max. Units tcyc Clock Cycle — 20 — ns t1 Setup Time 4 — — ns t2 Hold Time 1 — — ns tod Output Delay 9 11 13 ns REFCLK tcyc tod CRSDV RXD[1:0] Receive Timing

 2017 Microchip Technology Inc. DS00002245B-page 45 KSZ8041NL/RNL

7.7 Auto-Negotiation Timing

FIGURE 7-8: AUTO-NEGOTIATION FAST LINK PULSE (FLP) TIMING TABLE 7-8: AUTO-NEGOTIATION FAST LINK PULSE (FLP) TIMING PARAMETERS Timing Parameter Description Min. Typ Max. Units tBTB FLP Burst to FLP Burst 8 16 24 ms tFLPW FLP Burst Width — 2 — ms tPW Clock/Data Pulse Width — 100 — ns tCTD Clock Pulse to Data Pulse 55.5 64 69.5 µs tCTC Clock Pulse to Clock Pulse 111 128 139 µs — Number of Clock/Data Pulse per FLP Burst 17 — 33 — Auto-Negotiation Fast Link Pulse (FLP) Timing tPW TX+/TX- Clock Pulse Data Pulse Clock Pulse tPW tCTD tCTC tFLPW tBTB TX+/TX- Data Pulse FLP Burst FLP Burst

DS00002245B-page 46  2017 Microchip Technology Inc.

7.8 MDC/MDIO Timing

FIGURE 7-9: MDC/MDIO TIMING TABLE 7-9: MDC/MDIO TIMING PARAMETERS Timing Parameter Description Min. Typ. Max. Unit tP MDC Period — 400 — ns t1MD1 MDIO (PHY Input) Setup to Rising Edge of MDC 10 —— ns tMD2 MDIO (PHY Input) Hold from Rising Edge of MDC 4 —— ns tMD3 MDIO (PHY Output) Delay from Rising Edge of MDC — 222 — ns tMD1 Valid Data MDIO (PHY input) Valid Data MDC tMD2 MDIO (PHY output) Valid Data tMD3 tP

 2017 Microchip Technology Inc. DS00002245B-page 47 KSZ8041NL/RNL

7.9 Power-Up/Reset Timing

The KSZ8041NL/RNL reset timing requirement is summarized in Figure 7-10 and Figure 7-10. FIGURE 7-10: POWER-UP/RESET TIMING The supply voltage (VDDIO_3.3 and VDDA_3.3) power-up waveform should be monotonic. The 250 µs minimum rise time is from 10% to 90%. After the deassertion of reset, it is recommended to wait a minimum of 100 µs before starting programming on the MIIM (MDC/MDIO) Interface. TABLE 7-10: POWER-UP/R ESET TIMING PARAMETERS Parameters Description Min Max Units tVR Supply Voltage (VDDIO_3.3, VDDA_3.3) Rise Time 250 — µs tsr Stable Supply Voltage to Reset High 10 — ms tcs Configuration Setup Time 5 — ns tch Configuration Hold Time 5 — ns trc Reset to Strap-In Pin Output 6 — ns

DS00002245B-page 48  2017 Microchip Technology Inc.

7.10 Reset Circuit

The reset circuit in Figure 7-11 is recommended for powering up the KSZ8041NL/RNL if reset is triggered by the power supply. FIGURE 7-11: RECOMMENDED RESET CIRCUIT Figure 7-12 shows a reset circuit recommended for applications where reset is driven by another device (for example, the CPU or an FPGA). The reset out RST_OUT_n from CPU/FPGA provides the warm reset after power up reset. D2 is required if using different VDDIO voltage between the switch and CPU/FPGA. Diode D2 should be selected to provide maximum 0.3V VF (Forward Voltage), for example, VISHAY BAT54, MSS1P2L. Alternatively, a level shifter device can also be used. D2 is not required if PHY and CPU/FPGA use same VDDIO voltage. FIGURE 7-12: RECOMMENDED R ESET CIRCUIT FOR INTERFACING WITH CPU/FPGA RESET OUTPUT R 10k C 10µF 3.3V D1: 1N4148 RST# KSZ8041NL R 10k C 10µF 3.3V D1, D2: 1N4148 RST# KSZ8041NL RST_OUT_n CPU/FPGA

 2017 Microchip Technology Inc. DS00002245B-page 49 KSZ8041NL/RNL

7.11 Reference Circuits for LED Strapping Pins

The Figure 7-13 shows the reference circuits for pull-up, float, and pull-down on the LED1 and LED0 strapping pins. FIGURE 7-13: REFERENCE CIRC UITS FOR LED STRAPPING PINS LED pin 220Ω4.7kΩ 3.3V 1kΩ Pull-up KSZ8041NL/RNL 220Ω 3.3V Float KSZ8041NL/RNL LED pin 220Ω 3.3V Pull-down KSZ8041NL/RNL LED pin

DS00002245B-page 50  2017 Microchip Technology Inc.

8.0 SELECTION OF ISOLATION TRANSFORMER

A 1:1 isolation transformer is required at the line inte rface. An isolation transformer with integrated common-mode chokes is recommended for exceeding FCC requirements. Table 8-1 gives the recommended transformer characteristics. TABLE 8-1: TRANSFORMER SELECTION CRITERIA Parameter Value Test Condition Turns Ratio 1 CT : 1 CT — Open-Circuit Inductance (minimum) 350 H 100 mV, 100 kHz, 8 mA Leakage Inductance (maximum) 0.4 H 1 MHz (minimum) Inter-Winding Capacitance (typical) 12 pF — DC Resistance (typical) 0.9  — Insertion Loss (maximum) 1.0 dB 0 MHz – 65 MHz HIPOT (minimum) 1500 V RMS — TABLE 8-2: QUALIFIED SINGLE PORT MAGNETICS Magnetic Manufacturer Part Number Auto MDI-X Number of Ports Bel Fuse S558-5999-U7 Yes 1 Bel Fuse (Mag Jack) SI-46001 Yes 1 Bel Fuse (Mag Jack) SI-50170 Yes 1 Delta LF8505 Yes 1 LanKom LF-H41S Yes 1 Pulse H1102 Yes 1 Pulse (low cost) H1260 Yes 1 Transpower HB726 Yes 1 TDK (Mag Jack) TLA-6T718 Yes 1

 2017 Microchip Technology Inc. DS00002245B-page 51 KSZ8041NL/RNL

9.0 SELECTION OF REFERENCE CRYSTAL

TABLE 9-1: TYPICAL REFERENCE CRYSTAL CHARACTERISTICS Characteristics Value Units Frequency 25 MHz Frequency Tolerance (maximum) ±50 ppm Load Capacitance 20 pF Series Resistance 40 Ω

DS00002245B-page 52  2017 Microchip Technology Inc.

10.0 PACKAGE OUTLINE & RE COMMENDED LAND PATTERN

Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging. FIGURE 10-1: 32-LEAD QFN 5X5 PACKAGE TITLE

32 LEAD QFN 5x5mm PACKAGE OUTLINE & RECOMMENDED LAND PATTERN

DRAWING # QFN55-32LD-PL-1 UNIT MM

 2017 Microchip Technology Inc. DS00002245B-page 53 KSZ8041NL/RNL APPENDIX A: DATA SHEET REVISION HISTORY TABLE A-1: REVISION HISTORY Revision Section/Figure/Entry Correction DS00002245B (11-17-17) Figure 10-1 Updated the 32-LEAD QFN 5X5 Package illustration. — Minor text changes throughout. DS00002245A (05-02-17) ALL KSZ8041NL/RNL Datasheet initial conversion to Microchip DS00002245A.

DS00002245B-page 54 Advance Information  2017 Microchip Technology Inc. THE MICROCHIP WEB SITE Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site con- tains the following information:

• Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s guides and hardware support documents, latest software releases and archived software
• General Technical Support – Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing
• Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of semi- nars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revi sions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com. Under “Support”, click on “Customer Change Notifi- cation” and follow the registration instructions. CUSTOMER SUPPORT Users of Microchip products can receive assistance through several channels:
• Distributor or Representative
• Local Sales Office
• Field Application Engineer (FAE)
• Technical Support Customers should contact their distributor , representative or field application engi neer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this docu- ment. Technical support is available through the web site at: http://microchip.com/support

 2017 Microchip Technology Inc. DS00002245B-page 55 KSZ8041NL/RNL PRODUCT IDENTIFICATION SYSTEM To order or obtain information, for example, on pricing or delivery, refer to the factory or the listed sales office. Device: KSZ8041 – 10BASE-T/100BASE-TX Physical Layer Transceiver Interface: Blank = MII/RMII R= R M I I Package: N= 3 2 - p i n Q F N Power Option: L = Integrated LDO/LDO Controller/Regulator Temperature: Blank = Commercial (0°C to +70°C) I = Industrial (–40°C to +85°C) U = Automotive Grade 3 (–40°C to +85°C) (RMII Versions Only) AM = Automotive Grade 3 (–40°C to +85°C) (MII/RMII Version Only) Examples: a) KSZ8041NL – 10BASE-T/100BASE-TX Physi- cal Layer Transceiver, MII/RMII, 32-pin QFN Commercial temperature b) KSZ8041NLI – 10BASE-T/100BASE-TX Phys- ical Layer Transceiver, MII/RMII, 32-pin QFN, Industrial Temperature c) KSZ8041NL-AM – 10BASE-T/100BASE-TX Physical Layer Transceiver, MII/RMII, 32-pin QFN Industrial temperature, Automotive Grade 3 d) KSZ8041RNLU – 10BASE-T/100BASE-TX Physical Layer Transceiver, RMII, 32-pin QFN Automotive Grade 3 e) KSZ8041RNL – 10BASE-T/100BASE-TX Physical Layer Transceiver, RMII, 32-pin QFN, Commercial temperature f) KSZ8041RNLI – 10BASE-T/100BASE-TX Physical Layer Transceiver, RMII, 32-pin QFN, Industrial temperature PART NO. X X PackageInterfaceDevice X Power Option X Temperature

DS00002245B-page 56  2017 Microchip Technology Inc. NOTES:

 2017 Microchip Technology Inc. Advance Information DS00002245B-page 57 Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implic- itly or otherwise, under any Microchip intellectual property rights unless otherwise stated. Trademarks The Microchip name and logo, the Microchip logo, AnyRate, AVR, AVR logo, AVR Freaks, BeaconThings, BitCloud, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KEELOQ, KEELOQ logo, Kleer, LANCheck, LINK MD, maXStylus, maXTouch, MediaLB, megaAVR, MOST, MOST logo, MPLAB, OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, Prochip Designer, QTouch, RightTouch, SAM-BA, SpyNIC, SST, SST Logo, SuperFlash, tinyAVR, UNI/O, and XMEGA are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. ClockWorks, The Embedded Control Solutions Company, EtherSynch, Hyper Speed Control, HyperLight Load, IntelliMOS, mTouch, Precision Edge, and Quiet-Wire are registered trademarks of Microchip Technology Incorporated in the U.S.A. Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BodyCom, chipKIT, chipKIT logo, CodeGuard, CryptoAuthentication, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, Mindi, MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PureSilicon, QMatrix, RightTouch logo, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2017, Microchip Technology Incorporated, All Rights Reserved. ISBN: 978-1-5224-2384-3 Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification cont ained in their particular Microchip Data Sheet.
• Microchip believes that its family of pr oducts is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.
• There are dishonest and possibly illegal meth ods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC ® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV == ISO/TS 16949 ==

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