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Technical content
Features
- Single chip 100BASE-TX/100BASE-FX/ 10BASE-T physical layer solution
- 1.8V CMOS design, power consumption 250 mW
- Robust (130m+) operation over standard cables
- Supports Media Independent Interface (MII), Reduced MII (RMII), and Serial MII (SMII)
- LinkMD ® feature to determine cable length and diagnose faulty cables with +/- 2 m accuracy
- Supports HP MDI/MDI-X auto crossover
- Supports power down mode and power saving mode
- MDC/MDIO to 12.5 MHz for rapid configuration
- Fully compliant to IEEE 802.3u standard
- Supports auto-negotiation and manual selection for 10/100Mbps speed and full / half-duplex mode
- Configurable through MII serial management port or via external control pins
- Programmable LED outputs for link, activity, full/ half duplex, collision and speed
- On-chip built-in analog front end filtering for both 100BASE-TX and 10BASE-T
- Supports back-to-back, 100BASE-FX to 100BASE-TX for media converter applications
- Single 3.3V power supply with built-in 1.8V regu- lator (‘L’ parts)
- Packages: 48-Pin LQFP , 48-Pin SSOP Functional Diagram LED DRIVER LINK COL FDX SPD MII/RMII/SMII REGISTERS AND CONTROLLER INTERFACE TXD3 TXD2 TXC CRS COL RXD3 RXER RXDV RXC TXD1 TXD0 TXER TXEN MDIO MDC RXD2 RXD1 RXD0 4B/5B ENCODER SCRAMBLER PARALLEL/SERIAL PARALLEL/SERIAL MANCHESTER ENCODER 4B/5B DECODER DESCRAMBLER SERIAL/PARALLEL MANCHESTER DECODER SERIAL/PARALLEL NRZ/NRZI MLT3 ENCODER CLOCK RECOVERY AUTO NEGOTIATION POWER DOWN/ POWER SAVING PWRDWN PULSE SHAPER ADAPTIVE EQ BASELINE WANDER CORRECTION MLT3 DECODER NRZI/NRZ 10BASE-T RECEIVER TRANSMITTER TX+ TX- RX+ RX- PLL XI XO KSZ8001L/S 1.8V , 3.3V 10/100BASE-T/TX/FX Physical Layer Transceiver
DS00003062A-page 2 2009-2019 Microchip Technology Inc. TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for cur- rent devices. As device/doc umentation issues become known to us, we will publish an errata s heet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following:
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2009-2019 Microchip Technology Inc. DS00003062A-page 3 KSZ8001L/S Table of Contents
DS00003062A-page 4 2009-2019 Microchip Technology Inc.
1.0 GENERAL DESCRIPTION
The KSZ8001 is a 10BASE-T/100BASE-TX/100BASE-FX Physical Layer Transceiver, operating the core at 1.8 volts to meet low voltage and low power requirements. The solution provides MII/RMII/SMII interfaces to transmit and receive data. A unique mixed-signal design extends signaling distance while reducing power consumption. HP Auto MDI/MDI-X provides the most robust solution for eliminating the need to differentiate between crossover and straight-through cables. Featuring LinkMD® cable diagnostics, which allows detection of common cabling plant problems such as open and short circuits, the KSZ8001 represents a level of features and performance and is an ideal choice of physical layer transceiver for 100BASE-TX/10BASE-T/100BASE-FX applications.
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2.0 PIN DESCRIPTION AND CONFIGURATION
2.1 Pin Diagram
FIGURE 2-1: KSZ8001S - 48-PIN SSOP KSZ8001S XO GND NC RST# NC TX- GND VDDPLL XI TX+ VDDRCV REXT MDIO MDC RXD3/PHYAD1 RXD2/PHYAD2 RXD0/PHYAD4 VDDIO RXC RXER/ISO RXD1/PHYAD3 GND RXDV/PCS_LPBK GND VDDC TXER TXC/REF_CLK TXEN TXD0 TXD1 TXD2 TXD3 COL/RMII CRS/RMII_BTB GND VDDIO GND GND FXSD/FXEN RX+ RX- VDDRX PD# LED3/NWAYEN LED2/DUPLEX LED1/SPD100 LED0/TEST INT#/PHYAD0 Top View SSOP 48
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2.2 Pin Description
FIGURE 2-2: KSZ8001L - 48-PIN LQFP Pin Number Pin Name Type (Note 1) Pin Function
1 MDIO I/O MII Management (MIIM ) Interface: Data I/O
This pin requires an external 4.7K pull-up resistor.
2 MDC I MII Management (MIIM) Interface: Clock Input
This pin is synchronous to the MDIO data line. 3R X D 3 / PHYAD1 Ipd/O MII Mode: Receive Data Output[3] 2 / Configuration Mode: The pull-up/pull-down value is latched as PHY- ADDR[1] during reset. See Section 2.3, "Strapping Options" for details. 4R X D 2 / PHYAD2 Ipd/O MII Mode: MII Receive Data Output[2] 2 / Configuration Mode: The pull-up/pull-down value is latched as PHY- ADDR[2] during reset. See Strapping Options for details. 5R X D 1 / RXD[1]/ PHYAD3 Ipd/O MII Mode: Receive Data Output[1] 2 / RMII Mode: Receive Data Output[1]3 / Configuration Mode: The pull-up/pull-down value is latched as PHY- ADDR[3] during reset. See Strapping Options for details. KSZ8001L RX+ RX- VDDRX GND PD# LED2/DUPLEX LED1/SPD100 GND FXSD/FXEN LED3/NWAYEN LED0/TEST INT#/PHYAD0 VDDC TXER TXC/REF_CLK TXEN TXD0 TXD1 TXD2 TXD3 COL/RMII CRS/RMII_BTB GND VDDIO MDIO MDC RXD3/PHYAD1 RXD2/PHYAD2 RXD0/PHYAD4 VDDIO RXC RXER/ISO RXD1/PHYAD3 GND RXDV/PCS_LPBK GND RST# VDDPLL XI XO NC TX- GND VDDRCV REXT GND NC TX+ Top View LQFP 48
2009-2019 Microchip Technology Inc. DS00003062A-page 7 KSZ8001L/S 6R X D 0 / RXD[0]/ RX PHYAD4 Ipd/O MII Mode: Receive Data Output[0] 2 / RMII Mode: Receive Data Output[0]3 / SMII Mode: Receive Data and Control4 / Configuration Mode: The pull-up/pull-down value is latched as PHY- ADDR[4] during reset. See Strapping Options for details. 7 VDDIO Pwr 3.3V digital VDD
8 GND Gnd Ground
9 RXDV/
PCS_LPBK Ipd/O MII Mode: Receive Data Valid Output / RMII Mode: Carrier Sense/Receive Data Valid / Configuration Mode: The pull-up/pull-down value is latched as pcs_lpbk during reset. See Strapping Options for details.
10 RXC/
SMII_SE- LECT Ipd/O MII Receive Clock Output Operating at:
25 MHz = 100 Mbps
2.5 MHz = 10 Mbps
Configuration Mode: The pull-up/pull-down value is latched as SMII during reset. See Strapping Options for details.
11 RXER/
RX_ER/ ISO Ipd/O MII Mode: Rece ive Error Output / RMII Mode: Receive Error / Configuration Mode: The pull-up/pull-down value is latched as ISOLATE during reset. See Strapping Options for details.
12 GND Gnd Ground
13 VDDC Pwr 1.8V digital core VDD VDD output : KSZ8001L / KSZ8001SL VDD input : KSZ8001S (See Section 3.11, "Circuit Design Reference for Power Supply" for details)
14 TXER Ipd MII Transmit Error Input
15 TXC/ REF-
I/O MII Mode: MII Transmit Clock Output / RMII Mode: 50 MHz Reference Clock Input / SMII Mode: 125 MHz Synchronization Clock Input
16 TXEN Ipd MII Transmit Enable Input
17 TXD0/
TXD[0]/ TX Ipd MII Mode: Transmit Data Input[0] / RMII Mode: Transmit Data Input[0] / SMII Mode: Transmit Data and Control
18 TXD1/
TXD[1]/ SYNC Ipd MII Mode: Transmit Data Input[1] / RMII Mode: Transmit Data Input[1] / SMII Mode: SYNC
19 TXD2 Ipd MII Transmit Data Input[2]
20 TXD3 Ipd MII Transmit Data Input[3]
21 COL /
RMII_SE- LECT Ipd/O MII Collision Detect Output Configuration Mode: The pull-up/pull-down value is latched as RMII select during reset. See Strapping Options for details.
22 CRS/
RMII_BTB Ipd/O MII Carrier Sense Output Configuration Mode: The pull-up/pull-down value is latched as RMII Loop-back during reset when RMII mode is selected. See Strapping Options” for details.
23 GND Gnd Ground
24 VDDIO Pwr 3.3V digital VDD Pin Number Pin Name Type (Note 1) Pin Function
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25 INT#/ PHY-
Ipu/O Management Interface (MII) Interrupt Out. Configuration Mode: Latched as PHYAD[0] during power up / reset. See Strapping Options for details.
26 LED0/
Ipu/O Programmable LED Output 0 Configuration Mode: The external pull down enable test mode and only used for the factory test. Active Low. The LED0 pin is also programma- ble via register 1eh. LED mode = 00 Link/Act Pin State LED Definition No Link H Off Link L On Activity - Toggle LED mode = 01 Link Pin State LED Definition No Link H Off Link L On LED mode = 10 10Mbps Link Pin State LED Definition No Link H Off Link L On
27 LED1 /
Ipu/O Programmable LED Output 1 Configuration Mode: Latched as SPEED (Register 0, bit 13) during power up / reset. See Strapping Options for details. Active Low. The LED1 pin is also programmable via register 1eh. LED mode = 00 Speed Pin State LED Definition 10BT H Off 100BT L On LED mode = 01 Speed Pin State LED Definition 10BT H Off 100BT L On LED mode = 10 100Mbps Link Pin State LED Definition No Link H Off Link L On Pin Number Pin Name Type (Note 1) Pin Function
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28 LED2/
Ipu/O Programmable LED Output 2 Configuration Mode: Latched as DUPLEX (register 0h, bit 8) during power up / reset. See Strapping Options for details. Active Low. The LED2 pin is also programmable via register 1eh. LED mode = 00 Duplex Pin State LED Definition Half H Off Full L On LED mode = 01 Full Duplex/Col Pin State LED Definition Half H Off Full L On Collision - Toggle LED mode = 10 Duplex Pin State LED Definition Half H Off Full L On
29 LED3/
Ipu/O Programmable LED Output 3 Configuration Mode: Latched as ANEG_EN (register 0h, bit 12) during power up / reset. See Strapping Options for details. Active Low. The LED3 pin is also programmable via register 1eh. LED mode = 00 Collision Pin State LED Definition No Collision H Off Collision L On LED mode = 01 Activity Pin Stat e LED Definition Activity - Toggle LED mode = 10 Activity Pin Stat e LED Definition Activity - Toggle
30 PD# Ipu Chip power down input (active low)
1 (high) = Normal operation 0 (low) = Power down 31 VDDRX Pwr 1.8V analog VDD (See Circuit Design Reference for Power Supply for details)
32 RX- I/O Physical receive or transmit ‘-’ differential signal
33 RX+ I/O Physical receive or transmit ‘+’ differential signal
34 FXSD/
Ipd/O Fiber Mode Enable / Signal Detect in Fiber Mode If FXEN=0, FX mode is disable. The default is “0”. (See Section 3.7, "100BASE-FX Mode" for details)
35 GND Gnd Ground
36 GND Gnd Ground
37 REXT I Connect a 6.65K external resistor from this pin to ground 38 VDDRCV Pwr 3.3V analog VDD (See Circuit Design Reference for Power Supply for details) Pin Number Pin Name Type (Note 1) Pin Function
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39 GND Gnd Ground
40 TX- I/O Physical transmit or receive ‘-’ differential signal
41 TX+ I/O Physical transmit or receive ‘+’ differential signal
42 NC No Connect
43 NC No Connect
44 GND Gnd Ground
45 XO O 25MHz crystal/oscillator clock connections
Pins (XI, XO) connect to a crystal. If an oscillator is used, XI connects to a 3.3V tolerant oscillator and XO is a no connect. Clock is +/- 50ppm for both crystal and oscillator.
46 XI I
47 VDDPLL Pwr 1.8V analog PLL VDD (See Circuit Design Reference for Power Supply for details)
48 RST# Ipu Chip Reset
Active low, minimum of 50 us pulse is required Note 1: Pwr = power supply; Gnd = ground; I = input; O = output; I/O = bi-directional Ipu = input w/ internal pull up; Ipd = input w/ internal pull down; Ipu/O = input w/ internal pull up during reset, output pin otherwise; Ipd/O = input w/ internal pull down during reset, output pin otherwise; PD = strap pull down; PU = strap pull up; 2: MII Rx Mode: The RXD[3..0] bits are synch ronous with RXCLK. When RXDV is asserted, de-asserted. 3: RMII Rx Mode: The RXD[1..0] bits are synchronous with REF_CLK. For each clock period in which CRS_DV is asserted, two bits of recovered data are sent from the PHY. 4: SMII Rx Mode: Receive data and control information are sent in 10 bit segments. In 100MBit mode, each segment represents a new byte of data. In 10MBit mode, each segment is repeated ten times; therefore, every ten segments represents a new byte of data. The MAC can sample any one of every 10 segments in 10MBit mode. 5: MII Tx Mode: The TXD[3..0] bits are synchronous with TXCLK. When TXEN is asserted, TXD is de-asserted. 6: RMII Tx Mode: The TXD[1..0] bits are synchronous with REF_CLK. For each clock period in which TX_EN is asserted, two bits of recovered data are recovered by the PHY. 7: SMII Tx Mode: Transmit data and control in formation are received in 10 bit segments. In 100MBit mode, each segment represents a new byte of data. In 10MBit mode, each segment is repeated ten times; therefore, every ten segments represents a new byte of data. The PHY can sample any one of every 10 segments in 10MBit mode. Pin Number Pin Name Type (Note 1) Pin Function
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2.3 Strapping Options
Pin Number Pin Name Type Description 6, 5, 4, PHYAD[4:1] / RXD[0:3] Ipd/O PHY Address latched at power-up / reset. The default PHY address is 00001.
25 PHYAD0 /
INT# Ipu/O
9 PCS_LPBK /
Ipd/O Enables PCS_LPBK mo de at power-up / reset. PD (default) = Disable, PU = Enable
10 SMII_SELECT
/ RXC Ipd/O Enables SMII mode at power-up / reset. PD (default) = Disable, PU = Enable 11 ISO / RXER Ipd/O Enables ISOLATE mode at power-up /reset. PD (default) = Disable, PU = Enable
21 RMII_SELECT
/ COL Ipd/O Enables RMII mode at power-up / reset. PD (default) = Disable, PU = Enable
22 RMII_BTB/
Ipd/O Enable RMII_BTB mode at power-up / reset. PD (default) = Disable, PU = Enable
27 SPD100 /
Ipu/O Latched into Register 0h bit 13 during power-up / reset. PD = 10Mb/s, PU (default) = 100Mb/s. If SPD100 is asserted during power-up / reset, this pin also latched as the Speed Support in register 4h. (If FXEN is pulled up, the latched value 0 means no Far _End _Fault.)
28 DUPLEX/
Ipu/O Latched into Register 0h bit 8 during power-up / reset. PD = Half Duplex, PU (default) = Full duplex. If Duplex is pulled up during reset, this pin also latched as the Duplex support in register 4h.
29 NWAYEN/
Ipu/O Nway (auto-=Negotiation) Enable Latched into Register 0h bit 12 during power-up / reset. PD = Disable Auto-Negotiation, PU (default) = Enable Auto- Negotiation
30 PD# Ipu Power Down Enable
PU (default) = Normal operation, PD = Power down mode Note: Strap-in is latched during power up or reset. In some systems, the MAC RXD pins may drive high at all times causing the PHY strap-in to be latched high during power up or system reset. In this case, it is rec- ommended to use a strong pull down to GND via 1kohm resistor on RXDV, RXC, and RXER pins. Other- wise, the PHY may stay in Isolate or loop back modes.
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3.0 FUNCTIONAL OVERVIEW
3.1 Functional Description
3.1.1 100BASE-TX TRANSMIT The 100BASE-TX transmit function perfo rms parallel-to-serial conversion, NRZ to NRZI conversi on, MLT-3 encoding and transmission. The circuitry starts with a parallel-to-serial conversion, which converts the 25 MHz, 4-bit nibbles into a 125 MHz serial bit stream. The incoming data is clocked in at the positive edge of the TXC signal. The serialized data is further converted from NRZ to NRZI format, and then transmitted in MLT3 current output. The output current is set by an external 1% 6.65 K resistor for the 1:1 transformer ratio. It has typical rise/fall times of 4 ns and complies with the ANSI TP-PMD standard regarding amplitude balance, overshoot and timing jitter. The wave-shaped 10BASE-T output driver is also incorporated into the 100BASE-TX driver. 3.1.2 100BASE-TX RECEIVE The 100BASE-TX receive function performs adaptive equalization, DC restoration, MLT-3 to NRZI conversion, data and clock recovery, NRZI to NRZ conversion, and serial-to-parallel conversion. The receiving side starts with the equaliza- tion filter to compensate for inter-symbol interference (ISI) over the twisted pa ir cable. Since the amplitude loss and phase distortion are a function of the length of the cable, the equalizer has to adjust its characteristic to optimize perfor- mance. In this design, the variable equalizer will make an initial estimation based upon comparisons of incoming signal strength against some known cable characteristics, then tune s itself for optimization. This is an ongoing process and can self adjust against environmental changes such as temperature variations. The equalized signal then goes through a DC restoration and data conversion block. The DC restoration circuit is used to compensate for the effects of base line wander and to improve the dynamic range. The differential data conversion circuit converts the MLT3 format back to NRZI. The slicing threshold is also adaptive. The clock recovery circuit extracts the 125 MHz clock from the edges of the NRZI signal. This recovered clock is then used to convert the NRZI signal into the NRZ format. Finally, the NRZ serial data is converted to 4-bit parallel 4B nibbles. A synchronized 25 MHz RXC is generated so that the 4B nibbles is clocked out at the negative edge of RCK25 and is valid for the receiver at the positive edge. When no valid da ta is present, the clock recovery circuit is locked to the 25 Mz reference clock and both TXC and RXC clocks continue to run.
3.1.3 PLL CLOCK SYNTHESIZER
The KSZ8001 generates 125 M z, 25 Mz and 20 Mz clocks for system timing. An inte rnal crystal oscillator circuit provides the reference clock for the synthesizer.
3.1.4 SCRAMBLER/DE-SCRAMBLER (100BASE-TX ONLY)
The purpose of the scrambler is to spread the power spectrum of the signal in order to reduce EMI and baseline wander. 3.1.5 10BASE-T TRANSMIT When TXEN (transmit enable) goes high, data encodin g and transmission will begin. The KSZ8001 will continue to encode and transmit data as long as TXEN remains high. The data transmission will end when TXEN goes low. The last transition occurs at the boundary of the bit cell if the last bit is zero, or at the center of the bit cell if the last bit is one. The output driver is incorporated into the 100BASE- driver to allow transmission with the same magnetic. They are inter- nally wave-shaped and pre-emphasized into outputs with a typical 2.5 V amplitude. The harmonic contents are at least 27 dB below the fundamental when driven by an all-ones Manchester-encoded signal. 3.1.6 10BASE-T RECEIVE On the receive side, input buffer and level detecting squelch circuits are employed. A differential input receiver circuit and a PLL performs the decoding function. The Manchester-e ncoded data stream is separated into clock signal and NRZ data. A squelch circuit rejects signals with levels less than 300 mV or with short pulse widths in order to prevent noises at the RX+ or RX- input from falsely trigger the decoder. When the input exceeds the squelch limit, the PLL locks onto the incoming signal and the KSZ8001 decodes a data frame. This activates the carrier sense (CRS) ad RXDV sig- nals and makes the receive data (RXD) available. The receive clock is maintained active during idle periods in between data reception.
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3.1.7 SQE AND JABBER F UNCTION (10BASE-T ONLY)
In 10BASE-T operation, a short pulse will be put out on the COL pin after each packet is transmitted. This is required as a test of the 10BASE-T transmit/receive path and is called SQE test. The 10BASE-T transmitter will be disabled and COL will go high if TXEN is High for more than 20 ms (J abbering). If TXEN then goes low for more than 250 ms, the 10BASE-T transmitter will be re-enabled and COL will go Low.
3.1.8 AUTO-NEGOTIATION
The KSZ8001 performs auto-negotiation by hardware strapping option (pin 29) or software (Register 0.12). It will auto- matically choose its mode of operation by advertising its abilities and comparing them with those received from its link partner whenever auto-negotiation is enabled. It can also be configured to advertise 100BASE-TX or 10BASE-T in either full- or half-duplex mode. Auto-negotiation is disabled in FX mode. During auto-negotiation, the contents of Register 4, coded in Fast Link Pulse (FLP), will be sent to its link partner under the conditions of power-on, link-loss or re-start. At the same time, the KSZ8001 will monitor incoming data to determine its mode of operation. Parallel detection circuit will be enabled as soon as either 10BASE-T NLP (Normal Link Pulse) or 100BASE-TX idle is detected. The operation mode is configured based on the following priority:
- Priority 1: 100BASE-TX, full-duplex
- Priority 2: 100BASE-TX, half-duplex
- Priority 3: 10BASE-T, full-duplex
- Priority 4: 10BASE-T, half-duplex When the KSZ8001 receives a burst of FLP from its link partner with 3 identical link code words (ignoring acknowledge bit), it will store these code words in Register 5 and wait for the next 3 identical code words. Once the KSZ8001 detects the second code words, it then configures itself according to the above-mentioned priority. In addition, the KSZ8001 also checks for 100BASE-TX idle or 10BASE-T NLP symbols. If either is detected, the KSZ8001 automatically configures to match the detected operating speed.
3.2 MII Management Interface
The KSZ8001 supports the IEEE 802.3 MII Management Interface, also known as the Management Data Input / Output (MDIO) Interface. This interface allows upper-layer devices to monitor and control the state of the KSZ8001. The MDIO interface consists of the following:
- A physical connection including a data line (MDIO), a clock line (MDC) and an optional interrupt line (INTRPT)
- A specific protocol that runs across the above-mentioned physical connection and it also allows one controller to communicate with multiple KSZ8001 devices. Each KSZ8001 is assigned an MII address between 0 and 31 by the PHYAD inputs.
- An internal addressable set of fourteen 16-bit MDIO regi sters. Register [0:6] are required and their functions are specified by the IEEE 802.3 specifications. Additional registers are provided for expanded functionality. The INTPRT pin functions as a management data interrupt in the MII. An active Low or High in this pin indicates a status change on the KSZ8001 based upon 1fh.9 level control. Register bits at 1bh[15:8] are the interrupt enable bits. Register bits at 1bh[7:0] are the interrupt condition bits. This interrupt is cleared by reading Register 1bh.
3.2.1 MII DATA INTERFACE
The data interface consists of separate channels for tr ansmitting data from a 10/100 802.3 compliant Media Access Controller (MAC) to the KSZ8001, and for receiving data from the line. Normal data transmission is implemented in 4B Nibble Mode (4-bit wide nibbles).
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3.2.1.1 Transmit Clock (TXC): The transmit clock is normally generated by the KSZ8001 from an
external 25MHz reference source at the X1 input. The transmit data and control signals must always be synchronized to the TXC by the MAC. The KSZ8001 normally samples these signals on the rising edge of the TXC.
3.2.1.2 Receive Clock (RXC): For 100BASE-TX links, the receive clock is continuously recovered
from the line. If the link goes down, and auto-negotiation is disabled, the receive clock then operates off the master input clock (X1 or TXC). For 10BASE-T links, the receive clock is recovered from the line while carrier is active, and operates from the master input clock when the line is idle. The KSZ8001 synchronizes the receive data and control signals on the falling edge of RXC in order to stabilize the signals at the rising edge of the clock with 10ns setup and hold times.
3.2.1.3 Transmit Enable: The MAC must assert TXEN at the same time as the first nibble of the
preamble, and de-assert TXEN after the last bit of the packet. 3.2.1.4 Receive Data Valid: The KSZ8001 asserts RXDV when it receives a valid packet. Line operating speed and MII mode will determine timing changes in the following way: For 100BASE-TX link with the MII in 4B mode, RXDV is asserted from the first nibble of the preamble to the last nibble of the data packet. For 10BASE-T links, the entire preamble is truncated. RXDV is asserted with the first ni bble of the SFD “5D” and re- mains asserted until the end of the packet.
3.2.1.5 Error Signals: Whenever the KSZ8001 receives an error symbol from the network, it asserts
RXER and drives “1110” (4B) on the RXD pins. When the MAC asserts TXER, the KSZ8001 will drive “H” symbols (a Transmit Error define in the IEEE 802.3 4B/5B code group) out on the line to force signaling errors.
3.2.1.6 Carrier Sense (CRS): For 100TX links, a start-of-stream delimiter, or /J/K symbol pair causes
assertion of Carrier Sense (CRS). An end-of-stream delimiter, or /T/R symbol pair causes de- assertion of CRS. The PMA layer will also de-assert CRS if IDLE symbols are received without /T/R, yet in this case RXER will be asserted for one clock cycle when CRS is de-asserted. For 10T links, CRS assertion is based on reception of valid preamble, and de-assertion on reception of an end-of-frame (EOF) marker.
3.2.1.7 Collision: Whenever the line state is half-duplex and the transmitter and receiver are active at
the same time, then the KSZ8001 asserts its collision signal, which is asynchronous to any clock.
3.3 RMII (Reduced MII) Data Interface
RMII interface specifies a low pin count (Reduced) Media Independent Interface (RMII) intended for use between Ether- net PHYs and Switch or Repeater ASICs. It is fully compliant with IEEE 802.3u [2]. This interface has the following characteristics:
- It is capable of supporting 10Mb/s and 100Mb/s data rates
- A single clock reference is sourced from the MAC to PHY (or from an external source)
- It provides independent 2 bit wide (di-bit) transmit and receive data paths
- It uses TTL signal levels, compatible with common digital CMOS ASIC processes
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3.3.1 REFERENCE CLOCK (REF_CLK)
REF_CLK is a continuous 50 MHz clock that provides the timing reference for CRS_DV, RXD[1:0], TX_EN, TXD[1:0], and RX_ER. REF_CLK is sourced by the MAC or an external source. Switch implementations may choose to provide REF_CLK as an input or an output depending on whether they provide a REF_CLK output or rely on an external clock distribution device. Each PHY device shall have an input corresponding to this clock but may use a single clock input for multiple PHYs implemented on a single IC.
3.3.2 CARRIER SENSE/RECEIVE DATA VALID (CRS_DV)
CRS_DV is asserted asynchronously on detection of carrier due to the criteria relevant to the operating mode. That is, in 10BASE-T mode, when squelch is passed or in 100BASE-X mode when 2 non-contiguous zeroes in 10 bits are detected carrier is said to be detected. Loss of carrier shall result in the de-assertion of CRS_DV synchronous to REF_CLK. So long as carrier criteria are being met, CRS_DV shall remain asserted continuously from the first recovered di-bit of the frame through the final recovered di-bit and shall be negated prior to the first REF_CLK that follows the final di-bit. The data on RXD[1:0] is considered valid once CRS_DV is asserted. However, since the assertion of CRS_DV is asyn- chronous relative to REF_CLK, the data on RXD[1:0] shall be "00" until proper receive signal decoding takes place (see definition of RXD[1:0] behavior).
3.3.3 RECEIVE DATA [1:0] (RXD[1:0])
RXD[1:0] shall transition synchronously to REF_CLK. For each clock period in which CRS_DV is asserted, RXD[1:0] transfers two bits of recovered data from the PHY. In some cases (e.g. before data recovery or during error conditions) a pre-determined value for RXD[1:0] is transferred instead of recovered data. RXD[1:0] shall be "00" to indicate idle when CRS_DV is de-asserted. Values of RXD[1:0] other than "00" when CRS_DV is de-asserted are reserved for out- of-band signaling (to be defined). Values other than "00" on RXD[1:0] while CRS_DV is de-asserted shall be ignored by the MAC/repeater. Upon assertion of CRS_DV, the PHY shall ensure that RXD[1:0]=00 until proper receive decoding takes place.
3.3.4 TRANSMIT ENABLE (TX_EN)
Transmit Enable TX_EN indicates that the MAC is presenting di-bits on TXD[1:0] on the RMII for trans-mission. TX_EN shall be asserted synchronously with the fi rst nibble of the preamble and shall remain asserted while all di-bits to be transmitted are presented to the RMII. TX_EN shall be negated prior to the first REF_CLK following the final di-bit of a frame. TX_EN shall transition synchronously with respect to REF_CLK. TABLE 3-1: RMII SIGNAL DEFINITION Signal Name Direction (with respect to the PHY) Direction (with respect to the MAC) Use REF_CLK Input Input or Output Synchronous clock reference for receive, transmit and con- trol interface CRS_DV Output Input Carrier Sense/Receive Data Valid RXD[1:0] Output Input Receive Data TX_EN Input Output Transit Enable TXD[1:0] Input Output Transit Data RX_ER Output Input (Not Required) Receive Error Note: Unused MII signals, TXD[3:2], TXER need to be tied to GND when RMII is used.
DS00003062A-page 16 2009-2019 Microchip Technology Inc.
3.3.5 TRANSMIT DATA [1:0] (TXD[1:0])
Transmit Data TXD[1:0] shall transition synchronously wit h respect to REF_CLK. When TX_EN is asserted, TXD[1:0] are accepted for transmission by the PHY. TXD[1:0] shall be "00" to indicate idle when TX_EN is de-asserted. Values of TXD[1:0] other than "00" when TX_EN is de-asserted are reserved for out-of-band signaling (to be defined). Values other than "00" on TXD[1:0] while TX_EN is disserted shall be ignored by the PHY.
3.3.6 COLLISION DETECTION
Since the definition of CRS_DV and TX_EN both contain an accurate indication of the start of frame, the MAC can reli- ably regenerate the COL signal of the MII by Ending TX_EN and CRS_DV. During the IPG time following the successful transmission of a frame, the COL signal is asserted by some transceivers as a self-test. The Signal Quality Error (SQE) function will not be supported by the reduced MII due to the lack of the COL signal. Historically, SQE was present to indicate that a transceiver located physically remote from the MAC was functioning. Since the reduced MII only supports chip-to-chip connections on a PCB, SQE functionality is not required.
3.3.7 RX_ER
The PHY shall provide RX_ER as an output according to the rules specified in IEEE 802.3u [2] (see Clause 24, Figure 24-11 - Receive State Diagram). RX_ER shall be asserted for one or more REF_CLK periods to indicate that an error (e.g. a coding error or any error that a PHY is capable of detecting, and that may otherwise be undetectable by the MAC sublayer) was detected somewhere in the frame presently being transferred from the PHY. RX_ER shall transition syn- chronously with respect to REF_CLK. While CRS_DV is de-asserted, RX_ER shall have no effect on the MAC.
3.3.8 RMII AC CHARACTERISTICS
3.3.8.1 RMII Transmit Timing
Parameter Min Typ Max Unit REF_CLK Frequency 50 MHz TXD[1:0], TX_EN, Data Setup to REF_CLK rising edge 4 ns TXD[1:0], TX_EN, Data hold from REF_CLK rising edge 2 ns REF_CLK 20ns TXD[1:0] TXEN
2009-2019 Microchip Technology Inc. DS00003062A-page 17 KSZ8001L/S
3.3.8.2 RMII Receive Timing
3.4 SMII Signal Definition
SMII is composed of two signals per port, a global synchroniza tion signal, and a global 125MHz reference clock. All signals are synchronous to the clock. All SMII I/F uses a common 125MHz reference clock and SYNC signals that are synchronous to the reference clock. There are two signals in SMII from MAC-to-PHY for each port (TXD and TxSYNC), and one signal per port from PHY-to-MAC (RXD). The Serial Media Independent Interface (SMII) is designed to satisfy the following requirements:
- Convey complete MII information between a 10/100 PHY and MAC with two pins per port.
- Allow a multi-port MAC/PHY comm unication with one system clock.
- Operate in both half and full duplex.
- Per packet switching between 10Mbit and 100Mbit data rates.
- Allow direct MAC-to-MAC communication.
3.4.1 SMII SIGNALS
Parameter Min Typ Max Unit REF_CLK Frequency 50 MHz RXD[1:0], CRS_DV, RX_ER Output delay from REF_CLK rising edge 2.8 10 ns Signal Name From To Use RX PHY MAC Receive Data and Control TX MAC PHY Transmit Data and Control SYNC MAC PHY Synchronization Clock System MAC&PHY Synchronization REF_CLK 20ns tod RXD[1:0] RXDV RXER
DS00003062A-page 18 2009-2019 Microchip Technology Inc.
3.4.2 RECEIVE PATH
Receive data and control information are signaled in ten bi t segments. In 100Mbit mode, each segment represents a new byte of data. In 10Mbit mode, each segment is repeated ten times; therefore, every ten segments represent a new byte of data. The MAC can simply any one of every 10 segment ion 10Mbit mode. Segment boundaries are delimited by SYNC. The MAC continuously generates a pulse on SYNC every 10 clocks. RX contains all of the information found on the receive path of the standard MII.
3.4.2.1 RX – Bit Description
RXD7-0 are used to convey packet data, RX_ER, and PHY status. The MAC can infer the meaning of RXD on a seg- ment-by-basis by encoding the two control bits.
3.4.2.2 TXD7 – 0 Encoding
Inter-frame status bit RXD5 conveys the validity of the upper nibble of the byte of the previous frame. Inter-frame status bit RXD0 indicates whether or not the PHY detected an erro r somewhere on the previous frame. Both of these bits should be valid in the segment immediately following a fram e, and should stay valid until the first data segment of the next frame begins. When asserted, inter-frame status bit RXD6 indicates that the PHY has detected a false carrier event. In order to send receive data to the MAC synchronous to the reference clock, the PHY must pass the data through an elasticity FIFO to handle any difference between the reference clock rate and the clock at the packet source. The Ether- net specification calls for packet data to be referenced to a clock with a frequency tolerance of 100ppm (0.01%); how- ever, it is not uncommon to encounter Ethernet stations with clocks that have frequency errors up to 0.1%. Therefore, the elasticity FIFO should be at least 27 bits * long, filling to the halfway point before beginning valid data transfer via RX. RX_ER should be asserted if, during the reception of a frame, this FIFO overflows or underflows. FIGURE 3-1: Receive Sequence Diagram Bits Purpose CRS Carrier Sense – identical to MII, exce pt that it is not an asynchronous signal RX_DV Receive Data Valid – identical to MII RXD7-0 Encoded Data, see the RXD0-7 Encoding table CRS RX_DV RXD0 RXD1 RXD2 RXD3 RXD4 RXD5 RXD6 RXD7 X0 R X _ E R from pre- vious frame Speed 0=10Mbit 1=100Mbit Duplex 0=Half 1=Full Link 0=Down 1=Up Jabber 0=OK 1=Error Upper Nibble 0=invalid 1=valid False Carrier Detected X 1 One Data Byte (Two MII Data Nibble) CRS RX_DV RXD0 RXD1 RXD2 RXD3 RXD4 RXD5 RXD6 RXD7 RX_CLK RX_SYNC RX
2009-2019 Microchip Technology Inc. DS00003062A-page 19 KSZ8001L/S Only RXD and RX_DV should be passed through the elasticity FIFO. CRS should not be passed through the elasticity FIFO. Instead, CRS should be asserted for the time the ‘wire’ is busy receiving a frame.
3.4.3 TRANSMIT PATH
Transmit data and control information are signaled in ten bit segments, just like the receive path. In 100Mbit mode, each segment represents anew byte of data. In 10Mbit mode each segment is repeated ten times; therefore, every ten seg- ments represents a new byte of data. The PHY can sample any one of every 10 segments in 10Mbit mode. Segment boundaries are delimited by SYNC. The MAC continuously generates a pulse on SYNC every 10 clocks.
3.4.3.1 TX- Bit Description
As far as the PHY is concerned, TXD7-0 are used to convey only packet data. To allow for a direct MAC-to-MAC con- nection, the MAC uses TXD7-0 to signal ‘status’ in between frames. TXD7 – 0 Encoding
3.4.4 COLLISION DETECTION
Collisions occur when CRS and TX_EN are simultaneously asserted. For this to work, the PHY must ensure that CRS is not affected by its transmit path. FIGURE 3-2: Transmit Sequence Diagram Bits Purpose TX_EN Transmit Enable – identical to MII TX_ER Transmit Error – identical to MII TXD7-0 Encoded Data – see TXD7-0 Encoding Table TX_ER TX_EN TXD0 TXD1 TXD2 TXD3 TXD4 TXD7-5 x 0 Use to force an error in a direct MAC to MAC connec- tion 100MBit Full Duplex Link Up No Jabber x 1 One Data Byte (Two MII Data Nibbles) TX_ER TX_EN TXD0 TXD1 TXD2 TXD3 TXD4 TXD5 TXD6 TXD7 TX_CLK TX_SYNC TX
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3.4.5 DC SPECIFICATION
3.4.6 TIMING SPECIFICATION
3.5 HP Auto Crossover (Auto MDI/MDI-X)
Automatic MDI/MDI-X configuration is intended to eliminate the need for crossover cables between similar devices. The assignment of pin-outs for a 10/100 BASE-T crossover function cable is shown below. This feature can eliminate the confusion in real applications by allowing both straight cable and crossover cables. This feature is controlled by register 1f:13, see “Register 1fh” section for details. Parameter Symbol Min Max Units Input High Voltage Vih 2.0 Volts Input Low Voltage Vil 0.8 Volts Input High Current Iih -10 10 uA Input Low Current Iil -10 10 uA Parameter Min Max Units Input Setup 1.5 ns Input Hold 1 ns Output Delay 1.5 5 ns
2009-2019 Microchip Technology Inc. DS00003062A-page 21 KSZ8001L/S Receive PairTransmit Pair Receive Pair Transmit Pair Straight Through Cable 10/100 Base‐T Media Dependent Interface 10/100 Base‐T Media Dependent Interface Modular Connector (RJ45) NIC Modular Connector (RJ45) HUB (Repeater or Switch)
DS00003062A-page 22 2009-2019 Microchip Technology Inc.
3.5.1 AUTO MDI/MDI-X CROSS-O VER TRANSFORMER CONNECTION
KSZ8001 features HP Auto MDI/MDI-X crossover and requires symmetric transformers that support Auto MDI/MDI-X. See “Section 6.9, "Selection of Isolation Transformer"” for a list of transformers that support Auto MDI/MDI-X.
3.6 Power Management
The KSZ8001 offers the following modes for power management:
- Power Down Mode: This mode can be achieved by writing to Register 0.11 or pulling pin 30 PD# Low. In the power down state, the KS8061 disables all internal functions and drives output pins to logic zero, except for the MII serial management interface.
- Power Saving Mode: writing to register 1fh.10 can disable this mode. The KSZ8001 will then turn off everything except for the Energy Detect and PLL circuits when the cable is not installed. In other words, the KSZ8001 will shutdown most of the internal circuits to save power if there is no link. Power Saving mode will be in this most effective state when Auto-Negotiation Mode is enabled. 3.7 100BASE-FX Mode 100BASE-FX mode is activated when FXSD/FXEN is higher than 0.6V (This pin has a default pull down). Under this mode, the auto-negotiation and auto-MDIX features are disabled. In fiber operation FXSD pin should connect to the SD (signal detect) output of the fiber module. The internal threshold of FXSD is around ⅔ Vdd +/- 50 mV (2.2V +/- 0.05V at 3.3V). Above this level, it is considered Fiber signal detected, and the operation is summarized in the following table: Receive PairTransmit Pair Receive Pair Transmit Pair Straight Through Cable 10/100 Base‐T Media Dependent Interface 10/100 Base‐T Media Dependent Interface Modular Connector (RJ45) NIC Modular Connector (RJ45) HUB (Repeater or Switch)
2009-2019 Microchip Technology Inc. DS00003062A-page 23 KSZ8001L/S To ensure proper operation, the swing of fiber module SD should cover the threshold variation. A resistive voltage divider is recommended to adjust the SD voltage range. FEF (Far End Fault), repetition of a special pattern, which consists of 84-ones and 1-zero, is generated under “FX mode with no signal detected”. The purpose of FEF is to notify the sender of a faulty link. When receiving a FEF, the LINK will go down to indicate a fault, even with fiber signal detected. The transmitter is not affected by receiving a FEF and still sends out its normal transmit pattern from MAC. FEF can be disabled by strapping pin27 low, please refer to “Strapping Options” section.
3.8 Media Converter Operation
The KSZ8001 is capable of performing media conversion with 2 parts in a back-to-back RMII mode as indicated in the diagram. Both parts are in RMII mode and with RMII_BTB asserted (pin21 & 22 strapped high). One part is operating at TX mode and the other in FX mode. Both parts can share a common 50MHz oscillator. Under this operation, auto-Negotiation on the TX side will prohibit 10BASE-T link up. Additional options can be imple- mented under this operation. Disable the transmitter and set it at tri-state by controlling the high TXD2 pin. In order to do this, RXD2 and TXD2 pins need to be connected via an inverter. When TXD2 pin is high in both the copper and fiber operation, it disables transmit. Meanwhile, the RXD2 pin on the copper side serves as the energy detect and can indi- cate if a line signal is detected. TXD3 should be tied low and RXD3 let float. Please contact your local Microchip FAE for a Media Converter reference design. FXSD/FXEN Condition Less than 0.6V 100TX mode Less than 2.15V, but greater than 0.6V FX mode No signal detected FEF generated Greater than 2.25V FX mode Signal detected
DS00003062A-page 24 2009-2019 Microchip Technology Inc.
3.9 LinkMD ® Cable Diagnostics
The KSZ8001 utilizes time domain reflectometry (TDR) to analyze the cabling plant for common cabling problems such as open circuits, short circuits and impedance mismatches. LinkMD® works by sending a pulse of known amplitude and duration down the MDI and MDIX pairs and analyzing the shape of the reflected signal. Timing the duration gives an indication of the distance to the cabling fault with maximum distance of 200 m and accuracy of +/- 2 m. Cable diagnostics are only valid for copper connections and do not support fiber optic operation. LinkMD is used by accessing register 1dh, the LinkMD Contro l/Status register in conjuncti on with register 1fh, the 100BASE-TX PHY Controller register. To use LinkMD, HP Auto-MDIX is disabled by writing a ‘1’ to 1f:13 to enable man- ual control over which pair is used to transmit the LinkMD pulse. The self-clearing Cable diagnostic test enable bit, 1d.15 is set to ‘1’ to start the test on this pair. When 1d.15 returns to ‘0’, the test is complete. The test result is returned in 1d.14:13 and the distance is returned in 1d.8:0. The cable diagnostic test results are as follows:
- 00 = Valid test, normal condition
- 01 = Valid test, open circuit in cable
- 10 = Valid test, short circuit in cable KSZ8001 Rx +/- Tx +/- FTx FRx KSZ8001 Vcc Pin RxD TxD To the SD pin of the Fiber Module (Fiber Mode) Vcc RxD TxD 21 22 Pin Pin 21 22 OSC
50 MHz
Ref_CLK TxC/ Ref_CLK
2009-2019 Microchip Technology Inc. DS00003062A-page 25 KSZ8001L/S
- 11 = Invalid test, LinkMD failed The ‘11’ case, Invalid test, occurs when it is not possible for the KSZ8001 to shut down the link partner. In this case, the test is not run, since it would not be possible for the KSZ8001 to determine if the detected signal is a reflection of the signal generated or a signal from another source. Cable length can be determined by multiplying the contents of 1d.8:0 by 0.39. This constant may be calibrated for dif- ferent cabling conditions, including cables with a velocity of propagation that varies significantly from the norm.
3.10 Reference Clock Connection Options
KSZ8001 is capable of performing three different kinds of cl ock speed options for connecting the external reference clock depends upon the different interface of using MII/RMII/SMII. The figures below illustrate the recommended con- nection for using the different interface options. See Section 6.10, "Selection of Reference Crystal" for specifications. FIGURE 3-3: 25MHz Oscillator Reference Clock Connection Diagram FIGURE 3-4: 25MHz Crystal Reference Clock Connection Diagram XI XO 25MHz Osc +/-50ppm NC NC XI XO 27pF 27pF 27pF 27pF 25MHz Xtal +/-50ppm
DS00003062A-page 26 2009-2019 Microchip Technology Inc.
3.11 Circuit Design Reference for Power Supply
The following diagram shows the power connections for the single 3.3V supply KSZ8001L and KSZ8001SL devices. FIGURE 3-5: 50/125 MHz Oscillator Reference Clock Connection for RMII/SMII Mode Diagram 50/125MHz Osc +/-50ppm NC NC 10K XI XO REF_CLK VCC 47 13 VDDIO KSZ8001L KSZ8001SL VDDPLL 0.1uF1uF VIN GND VOUT 1.8PLL Ferrite Bead Ferrite Bead1.8A 1.8V VDDRX 1.8V LDO Regulator 8 23 3635 39 4412 VDDIO VDDC 3.3V 0.1uF0.1uF VDDRCV 0.1uF1uF 3.3A Ferrite Bead
2009-2019 Microchip Technology Inc. DS00003062A-page 27 KSZ8001L/S
4.0 REGISTER MAP
Register No. Description 0h Basic Control Register 1h Basic Status Register 2h PHY Identifier I 3h PHY Identifier II 4h Auto-Negotiation Advertisement Register 5h Auto-Negotiation Link Partner Ability Register 6h Auto-Negotiation Expansion Register 7h Auto-Negotiation Next Page Register 8h Link Partner Next Page Ability 9h-14h Reserved 15h RXER Counter Register 16h – 1ah Reserved 1bh Interrupt Control/Status Register 1ch Reserved 1dh LinkMD ® Control/Status Register 1eh PHY Control Register 1fh 100BASE-TX PHY Control Register Address Name Description Mode Default Register 0h – Basic Control 0.15 Reset 1 = software rese t. Bit is self-clearing RW/ SC
0.14 Loop-back 1 = loop-back mode
0 = normal operation RW 0
0.13 Speed Select
(LSB) 1 = 100Mb/s 0 = 10Mb/s Ignored if Auto-Negotiation is enabled (0.12 = 1) RW Set by SPD100
0.12 Auto-Negotia-
1 = enable auto-negotiation process (over- ride 0.13 and 0.8) 0 = disable auto-negotiation process RW Set by NWAYEN
0.11 Power Down 1 = power down mode
0 = normal operation RW 0
0.10 Isolate 1 = electrical isolation of PHY from MII and
0 = normal operation RW Set by ISO
0.9 Restart Auto-
1 = restart auto-negotiation process 0 = normal operation. Bit is self-clearing RW/ SC
0.8 Duplex Mode 1 = full duplex
0 = half duplex RW Set by DUPLEX
0.7 Collision Test 1 = enable COL test
0 = disable COL test RW 0 0.6:1 Reserved RO 0
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0.0 Disable
0 = enable transmitter 1 = disable transmitter RW 0 Register 1h – Basic Status 1.15 100BASE-T4 1 = T4 capable 0 = not T4 capable RO 0 1.14 100BASE-TX Full Duplex 1 = capable of 100BASE-X full duplex 0 = not capable of 100BASE-X full duplex RO 1 1.13 100BASE-TX Half Duplex 1 = capable of 100BASE-X half duplex 0 = not capable of 100BASE-X half duplex RO 1 1.12 10BASE-T Full Duplex 1 = 10Mbps with full duplex 0 = no 10Mbps with full duplex capability RO 1 1.11 10BASE-T Half Duplex 1 = 10Mbps with half duplex 0 = no 10Mbps with half duplex capability RO 1 1.10:7 Reserved RO 0
1.6 No Preamble 1 = preamble suppression
0 = normal preamble RO 1
1.5 Auto-Negotia-
1 = auto-negotiation process completed 0 = auto-negotiation process not com- pleted RO 0
1.4 Remote Fault 1 = remote fault
0 = no remote fault RO/ LH
1.3 Auto-Negotia-
1 = capable to perform auto-negotiation 0 = unable to perform auto-negotiation RO 1
1.2 Link Status 1 = link is up
0 = link is down RO/ LL
1.1 Jabber Detect 1 = jabber detected
0 = jabber not detected. Default is Low RO/ LH
1.0 Extended
1 = supports extended capabilities regis- ters RO 1 Register 2h – PHY Identifier 1 2.15:0 PHY ID Num- ber Assigned to the 3rd through 18th bits of the Organizationally Unique Identifier (OUI). Kendin Communication’s OUI is 0010A1 (hex) RO 0022h Register 3h – PHY Identifier 2 3.15:10 PHY ID Num- ber Assigned to the 19th through 24th bits of the Organizationally Unique Identifier (OUI). Kendin Communication’s OUI is 0010A1 (hex) RO 000101 3.9:4 Model Num- ber Six bit manufacturer’s model number RO 100001 3.3:0 Revision Number Four bit manufacturer’s model number RO 1010 Register 4h – Auto-Negotiation Advertisement
4.15 Next Page 1 = next page capable
0 = no next page capability. RW 0
4.14 Reserved RO 0
4.13 Remote Fault 1 = remote fault supported
0 = no remote fault RW 0 Address Name Description Mode Default
2009-2019 Microchip Technology Inc. DS00003062A-page 29 KSZ8001L/S 4.12 : 11 Reserved RO 0
4.10 Pause 1 = pause function supported
0 = no pause function RW 0 4.9 100BASE-T4 1 = T4 capable 0 = no T4 capability RO 0 4.8 100BASE-TX Full Duplex 1 = TX with full duplex 0 = no TX full duplex capability RW Set by SPD100 & DUPLEX 4.7 100BASE-TX 1 = TX capable 0 = no TX capability RW Set by SPD100 4.6 10BASE-T Full Duplex 1 = 10Mbps with full duplex 0 = no 10Mbps full duplex capability RW Set by DUPLEX 4.5 10BASE-T 1 = 10Mbps capable 0 = no 10Mbps capability RW 1 4.4:0 Selector Field [0000 1] = IEEE 802.3 RW 00001 Register 5h – Auto-Negotiation Link Partner Ability
5.15 Next Page 1 = next page capable
0 = no next page capability RO 0
5.14 Acknowledge 1 = link code word received from partner
0 = link code word not yet received RO 0
5.13 Remote Fault 1 = remote fault detected
0 = no remote fault RO 0
5.12 Reserved RO 0
5.11:10 Pause 5.10 5.11 No PAUSE Asymmetric PAUSE (link partner) Symmetric PAUSE Symmetric & Asymmetric PAUSE (local device) RO 0 5.9 100 BASE-T4 1 = T4 capable 0 = no T4 capability RO 0 5.8 100BASE-TX Full Duplex 1 = TX with full duplex 0 = no TX full duplex capability RO 0 5.7 100BASE-TX 1 = TX capable 0 = no TX capability RO 0 5.6 10BASE-T Full Duplex 1 = 10Mbps with full duplex 0 = no 10Mbps full duplex capability RO 0 5.5 10BASE-T 1 = 10Mbps capable 0 = no 10Mbps capability RO 0 5.4:0 Selector Field [0000 1] = IEEE 802.3 RO 00001 Register 6h – Auto-Negotiation Expansion 6.15:5 Reserved RO 0
6.4 Parallel
1 = fault detected by parallel detection 0 = no fault detected by parallel detection. RO/ LH Address Name Description Mode Default
DS00003062A-page 30 2009-2019 Microchip Technology Inc.
6.3 Link Partner
1 = link partner has next page capability 0 = link partner does not have next page capability RO 0
6.2 Next Page
1 = local device has next page capability 0 = local device does not have next page capability RO 1
6.1 Page
1 = new page received 0 = new page not yet received RO/ LH
6.0 Link Partner
1 = link partner has auto-negotiation capa- bility 0 = link partner does not have auto-negoti- ation capability RO 0 Register 7h – Auto-Negotiation Next Page
7.15 Next Page 1 = additional next page(s) will follow
0 = last page RW 0
7.14 Reserved RO 0
7.13 Message
1 = message page 0 = unformatted page RW 1
7.12 Acknowl-
1 = will comply with message 0 = cannot comply with message RW 0
7.11 Toggle 1 = previous value of the transmitted link
code word equaled logic One 0 = logic Zero RO 0 7.10:0 Message Field 11-bit wide field to encode 2048 messages RW 001 Register 8h – Link Partner Next Page Ability
8.15 Next Page 1 = additional Next Page(s) will follow
0 = last page RO 0
8.14 Acknowledge 1 = successful receipt of link word
0 = no successful receipt of link word RO 0
8.13 Message
1 = Message Page 0 = Unformatted Page RO 0
8.12 Acknowl-
1 = able to act on the information 0 = not able to act on the information RO 0
8.11 Toggle 1 = previous value of transmitted Link
Code Word equal to logic zero 0 = previous value of transmitted Link Code Word equal to logic one RO 0 8.10:0 Message Field RO 0 Register 15h – RXER Counter 15.15:0 RXER Counter RX Error counter for the RX_ER in each package RO 0000 Register 1bh – Interrupt Control/Status Register 1b.15 Jabber Inter- rupt Enable 1=Enable Jabber Interrupt 0=Disable Jabber Interrupt RW 0 Address Name Description Mode Default
2009-2019 Microchip Technology Inc. DS00003062A-page 31 KSZ8001L/S 1b.14 Receive Error Interrupt Enable 1=Enable Receive Error Interrupt 0=Disable Receive Error Interrupt RW 0 1b.13 Page Received Interrupt Enable 1=Enable Page Received Interrupt 0=Disable Page Received Interrupt RW 0 1b.12 Parallel Detect Fault Interrupt Enable 1= Enable Parallel Detect Fault Interrupt 0= Disable Parallel Detect Fault Interrupt RW 0 1b.11 Link Partner Acknowledge Interrupt Enable 1= Enable Link Partner Acknowledge Inter- rupt 0= Disable Link Partner Acknowledge Interrupt RW 0 1b.10 Link Down Interrupt Enable 1= Enable Link Down Interrupt 0= Disable Link Down Interrupt RW 0 1b.9 Remote Fault Interrupt Enable 1= Enable Remote Fault Interrupt 0= Disable Remote Fault Interrupt RW 0 1b.8 Link Up Inter- rupt Enable 1= Enable Link Up Interrupt 0= Disable Link Up Interrupt RW 0 1b.7 Jabber Inter- rupt 1= Jabber Interrupt Occurred 0= Jabber Interrupt Does Not Occurred RO/ SC 1b.6 Receive Error Interrupt 1= Receive Error Occurred 0= Receive Error Does Not Occurred RO/ SC 1b.5 Page Receive Interrupt 1= Page Receive Occurred 0= Page Receive Does Not Occurred RO/ SC 1b.4 Parallel Detect Fault Interrupt 1= Parallel Detect Fault Occurred 0= Parallel Detect Fault Does Not Occurred RO/ SC 1b.3 Link Partner Acknowledge Interrupt 1= Link Partner Acknowledge Occurred 0= Link Partner Acknowledge Does Not Occurred RO/ SC 1b.2 Link Down Interrupt 1= Link Down Occurred 0= Link Down Does Not Occurred RO/ SC 1b.1 Remote Fault Interrupt 1= Remote Fault Occurred 0= Remote Fault Does Not Occurred RO/ SC 1b.0 Link Up Inter- rupt 1= Link Up Interrupt Occurred 0= Link Up Interrupt Does Not Occurred RO/ SC Register 1dh – LinkMD® Control/Status Register 1d.15 Cable diag- nostic test enable 0 = Indicates cable diagnostic test has completed and the status information is valid for read. 1 = the cable diagnostic test is activated. This bit is self-clearing. RW/ SC Address Name Description Mode Default
DS00003062A-page 32 2009-2019 Microchip Technology Inc. 1d.14:13 Cable diag- nostic test result [00] = normal condition [01] = open condition has been detected in cable [10] = short condition has been detected in cable [11] = cable diagnostic test failed RO 0 1d.12:9 Reserved 1d.8:0 Cable fault counter Distance to fault, approximately 0.39m*cabfaultcnt value RO 0 Register 1eh – PHY Control 1e:15:14 LED mode [00] = LED3 <- collision LED2 <- full duplex LED1 <- speed LED0 <- link/activity [01] = LED3 <- activity LED2 <- full duplex/collision LED1 <- speed LED0 <- link [10] = LED3 <- activity LED2 <- full duplex LED1 <- 100Mbps link LED0 <- 10Mbps link [11] = reserved RW 0 1e.13 Polarity 0 = Polarity is not reversed 1 = Polarity is reversed RO 1e.12 Far end fault detect 0 = Far end fault detected 1 = Far end fault not detected RO 1e.11 MDIX/MDI state 0 = MDIX 1 = MDI RO 1e:10:8 Reserved 1e:7 Remote loop- back 0: normal mode 1: remote (analog) loop back is enable RW 0 1e:6:0 Reserved Register 1fh – 100BASE-TX PHY Controller 1f:15 HP_MDIX 0: Microchip Auto MDI/MDI-X mode 1: HP Auto MDI/MDI-X mode RW 1 1f:14 MDI/MDI-X Select When Auto MDI/MDI-X is disabled, 0 = Transmit on TX+/- (pins 41,40) Receive on RX+/- (pins 33,32) 1 = Transmit on RX+/- (pins 33,32) Receive on TX+/- (pins 41,40) RW 0 Address Name Description Mode Default
2009-2019 Microchip Technology Inc. DS00003062A-page 33 KSZ8001L/S 1f:13 Pairswap dis- able 1 = disable MDI/MDIX 0 = enable MDI/MDIX RW 0 1f.12 Energy detect 1 = presence of signal on RX+/- analog wire pair 0 = no signal detected on RX+/- RO 0 1f.11 Force link 1 = force link pass 0 = normal link operation This bit bypasses the control logic and allow transmitter to send pattern even if there is no link. RW 0 1f.10 Power Saving 1 = enable power saving 0 = disable RW 1 1f.9 Interrupt Level 1 = interrupt pin active high 0 = active low RW 0 1f.8 Enable Jabber 1 = enable jabber counter 0 = disable RW 1 1f.7 Auto-Negotia- tion Complete 1 = auto-negotiation complete 0 = not complete This bit has the same definition as register 1.5. RO 0 1f.6 Enable Pause (Flow-Control Result) 1 = flow control capable 0 = no flow control RO 0 1f.5 PHY Isolate 1 = PHY in isolate mode 0 = not isolated RO 0 1f.4:2 Operation Mode Indica- tion [000] = still in auto-negotiation [001] = 10BASE-T half duplex [010] = 100BASE-TX half duplex [011] = default [101] = 10BASE-T full duplex [110] = 100BASE-TX full duplex [111] = PHY/MII isolate RO 0 1f.1 Enable SQE test 1 = enable SQE test 0 = disable RW 0 1f.0 Disable Data Scrambling 1 = disable scrambler 0 = enable RW 0 Address Name Description Mode Default
DS00003062A-page 34 2009-2019 Microchip Technology Inc.
5.0 OPERATIONAL CHARACTERISTICS
5.1 Absolute Maximum Rating ( Note 1)
**Please read the Notes at the end of the Electrical Characteristics.
5.2 Operating Range ( Note 2)
5.3 Package Thermal Resistance ( JA) (Note 3)
5.4 Electrical Characteristics ( Note 4)
Thermal Resistance JA JA JA JC Airflow Velocity (m/s) 0 1 2 0 KSZ8001L / KSZ8001LI 83.56 77.08 72.36 35.90 KSZ8001SL / KSZ8001SLI 75.19 68.20 66.43 42.65 KSZ8001S 42.43 36.19 34.24 6.75 Symbol Parameter Condition Min Typ Max Unit Total Supply Current (Note 5) KSZ8001L:
- Current consumption is for the single 3.3V supply KSZ8001L device only, and includes the 1.8V supply voltages (VDDRX, VDDPLL) that are provided by the KSZ8001L via power output pin 13 (VDDC).
- Transformer consumes an additional 45mA @ 3.3V for 100BASE-TX and 70mA @ 3.3V for 10BASE-T. IDD1 100BASE-TX Chip only, no transformer 52 mA IDD2 10BASE-T Chip only, no transformer 32 mA IDD3 Power Saving Mode Ethernet cable disconnected 35 mA IDD4 SW Power Down Mode Register (software) power down 5 mA IDD5 Power down pin (PD#) Chip (hardware) power down 3 mA TTL Inputs VIH Input High Voltage 2.0 V VIL Input Low Voltage 0.8 V IIN Input Current VIN = GND – V DD -10 10 A TTL Outputs VOH Output High Voltage I OH = -4mA 2.4 V VOL Output Low Voltage 0.4 V I IOZ I Output Tri-State Leakage 10 A
2009-2019 Microchip Technology Inc. DS00003062A-page 35 KSZ8001L/S Note 1: Exceeding the absolute rating(s) may cause permanent damage to the device. Operating at maximum con- ditions for extended periods may affect device reliability. 2: This device is not guaranteed to operate beyond its specified operating rating. Unused inputs must always be tied to an appropriate logic voltage level (Ground to VDD). 3: No HS (heat spreader) in package. 4: Specification for packaged product only. 5: 100% data transmission in full-duplex mode and minimum IPG with 130-meter cable. 100BASE-TX Transmit (measured differentially after 1:1 transformer) VO Peak Differential Output Voltage 50 from each output to VDD 0.95 1.05 V VIMB Output Voltage Imbal- ance 50 from each output to VDD 2% tr, tt Rise/Fall Time 3 5 ns Rise/Fall Time Imbalance 0 0.5 ns Duty Cycle Distortion 0.25 ns Overshoot 5% V SET Reference Voltage of ISET 0.75 V Propagation Delay 45 60 Ns Jitter 0.7 1.4 ns (pk-pk) 10BASE-T Transmit (measured differentially after 1:1 transformer) VP Peak Differential Output Voltage 50 from each output to VDD 2.2 2.8 V VIMB Output Voltage Imbal- ance 50 from each output to VDD 3.5 ns tr, tt Rise/Fall Time 25 ns Clock Outputs X1, X2 Crystal Oscillator 25 MHz RXC100 Receive Clock, 100TX 25 MHz RXC10 Receive Clock, 10T 2.5 MHz Receive Clock Jitter 3.0 ns (pk-pk) TXC100 Transmit Clock, 100TX 25 MHz TXC10 Transmit Clock, 10T 2.5 MHz Transmit Clock Jitter 1.8 ns (pk-pk) Symbol Parameter Condition Min Typ Max Unit
DS00003062A-page 36 2009-2019 Microchip Technology Inc.
6.0 TIMING DIAGRAMS
6.1 10BaseT MII Transmit Timing TXC min. typ. max. tSU1 TXD[3:0] Setup to TXC High 10ns tSU2 TXEN Setup to TXC High 10ns tHD1 TXD[3:0] Hold after TXC High 0ns tHD2 TXEN Hold after TXC High 0ns tCRS1 TXEN High to CRS asserted latency 4BT tCRS2 TXEN Low to CRS de-asserted latency 8BT tLAT TXEN High to TXP/TXM output (TX latency) 4BT tSQE COL (SQE) Delay after TXEN de-asserted 2.5us tSQEP COL (SQE) Pulse Duration 1.0us tHD2 tSU2TXEN TXD[3:0] tSU1 tHD1 CRS tCRS2 tCRS1 TXP/TXM tLAT Valid Data TXC tSQECOL tSQEP SQE Timing TXEN
2009-2019 Microchip Technology Inc. DS00003062A-page 37 KSZ8001L/S 6.2 100BaseTX MII Transmit Timing TXC tSU2 min. typ. max. tSU1 TXD[3:0] Setup to TXC High 10ns tSU2 TX_ER Setup to TXC High 10ns tHD1 TXD[3:0] Hold after TXC High 0ns tHD2 TXER Hold after TXC High 0ns tHD3 TXEN Hold after TXC High 0ns tCRS1 TXEN High to CRS asserted latency 4BT tCRS2 TXEN Low to CRS de-asserted latency 4BT tLAT TXEN High to TX+/TX- output (TX latency) 7BT TXEN tHD2 TXD[3:0], TXER tSU1 CRS tCRS2 tCRS1 TX+/TX- tLAT Symbol Out Data In tHD1
DS00003062A-page 38 2009-2019 Microchip Technology Inc. 6.3 100BaseTX MII Receive Timing min. typ. max. tP RXC period 40ns tWL RXC pulse width 20ns tWH RXC pulse width 20ns tSU RXD[3:0], RXER, RXDV setup to rising edge of RXC 20ns tHD RXD[3:0], RXER, RXDV hold from rising edge of RXC 20ns tRLAT CRS to RXD latency, 4B or 5B aligned 1BT 2BT 3BT tCRS1 "Start of Stream " to CRS asserted 140ns tCRS2 "End of Stream" to CRS de-asserted 170ns RX+/RX- RXD[3:0] RXER CRS tCRS1 tCRS2 RXDV tRLAT tSU tHD Start of Stream End of Stream RXC tWL tWH tP
2009-2019 Microchip Technology Inc. DS00003062A-page 39 KSZ8001L/S
6.4 Auto Negotiation / Fast Link Pulse Timing
min. typ. max. tBTB FLP burst to FLP burst 8ms 16ms 24ms tFLPW FLP burst width 2ms tPW Clock/Data pulse width 100ns tCTD Clock pulse to data pulse 69us tCTC Clock pulse to clock pulse 136us Number of Clock/Data pulses per burst 17 33 TX+/TX- Clock Pulse Data Pulse Clock Pulse tPW tCTD tCTC tFLPW tBTB TX+/TX- Data Pulse FLP Burst FLP Burst
DS00003062A-page 40 2009-2019 Microchip Technology Inc.
6.5 Serial Management Interface Timing
min. typ. max. tP MDC period 400 ns tMD1 MDIO Setup to MDC (MDIO as input) 10ns tMD2 MDIO Hold after MDC (MDIO as input) 10ns tMD3 MDC to MDIO Valid (MDIO as output) 222ns tMD1 Valid Data MDIO (Into Chip) Valid Data MDC tMD2 MDIO (Out of Chip) Valid Data tMD3 tP
2009-2019 Microchip Technology Inc. DS00003062A-page 41 KSZ8001L/S
6.6 Reset Timing
FIGURE 6-1: RESET TIMING DIAGRAM TABLE 6-1: RESET TIMING PARAMETERS Parameter Description Min Max Units tsr Stable supply voltages to reset high 50 us tsr Supply Voltage RST_N Strap‐In Value
DS00003062A-page 42 2009-2019 Microchip Technology Inc.
6.7 Reset Circuit Diagram
Microchip recommends the following discrete reset circuit when powering up the KSZ8001 device. For the application where the reset circuit signal comes from another device (e.g., CPU, FPGA, etc), the following reset circuit is recommended. FIGURE 6-2: RECOMMENDED RESET CIRCUIT FIGURE 6-3: RECOMMENDED CIRCUIT FOR INTERFACING WITH CPU/FPGA RESET KSZ8001 VCC D1: 1N4148 R 10K C 10uF RST# KSZ8001 CPU/FPGA VCC C 10uF R 10K RST_OUT_n D1, D2: 1N4148 RST#
2009-2019 Microchip Technology Inc. DS00003062A-page 43 KSZ8001L/S At power-on-reset, R, C, and D1 provide the necessary ramp rise time to reset the Microchip device. The reset out from CPU/FPGA provides warm reset after power up. It is also recommend to power up VDD core voltage earlier than VDDIO voltage. At worst case, the both VDD core and VDDIO voltages should come up at the same time.
6.8 Reference Circuit for Strapping Option Configuration
The following figure shows the reference circuits for external pull-up and pull-down on the LED strapping pins. KSZ8001 LED pin 3.3 V Reference circuits for unmanaged programming through LED ports KSZ8001 LED pin 3.3 V Pull Down Pull Up
DS00003062A-page 44 2009-2019 Microchip Technology Inc.
6.9 Selection of Isolation Transformer
A 1:1 isolation transformer is required at the line interface. An isolation transformer with integrated common-mode choke is recommended for exceeding FCC requirements. The following table gives recommended transformer characteristics.
6.10 Selection of Reference Crystal
An oscillator or crystal with the following typical characteristics is recommended. TABLE 6-2: TRANSFORMER SELECTION CRITERIA Parameter Value Test Condition Turns Ratio 1 CT : 1 CT Open-Circuit Inductance (min.) 350 uH 100 mV, 100 kHz, 8 mA Leakage Inductance (max.) 0.4 uH 1 MHz (min.) Inter-Winding Capacitance (max.) 12 pF D.C. Resistance (max.) 0.9 Ohms Insertion Loss (max.) 1.0 dB 0-65 MHz HIPOT (min.) 1500 Vrms TABLE 6-3: MAGNETIC VENDOR SELECTION LISTS Single Port Magnetic Manufacturer Part Number AUTO MDIX Number of Port Pulse H1102 Yes 1 Bel Fuse S558-5999-U7 Yes 1 Bel Fuse SI-46001 Yes 1 Bel Fuse SI-50170 Yes 1 YCL PT163020 Yes 1 Transpower HB726 Yes 1 Delta LF8505 Yes 1 LanKom LF-H41S Yes 1 Characteristics Value Units Frequency 25.00000 MHz Frequency Tolerance (max) 50 ppm Load Capacitance (max) 20 pF Series Resistance 40 W
2009-2019 Microchip Technology Inc. DS00003062A-page 45 KSZ8001L/S
7.0 PACKAGE INFORMATION
FIGURE 7-1: 48-PIN LQFP PACKAGE OUTLINE AND RECOMMENDED LAND PATTERN Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging.
DS00003062A-page 46 2009-2019 Microchip Technology Inc. FIGURE 7-2: 48-PIN SSOP PACKAGE OUTLINE AND RECOMMENDED LAND PATTERN Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging.
2009-2019 Microchip Technology Inc. DS00003062A-page 47 KSZ8001L/S APPENDIX A: DATA SHEET REVISION HISTORY TABLE A-1: REVISION HISTORY Revision Section/Figure/Entry Correction DS00003062A (06-26-19) Replaces previous Micrel version Rev. 1.04, June 2009. Rev. 1.04 (25 June 2009) Updated ordering information. Rev. 1.03 (7 March 2006) • Removed 48 Pin QFN (targeted) package option
- Renamed KS8001 to KSZ8001 throughout data sheet
- Added mechanical info for SSOP package
- Updated package thermal resistance Rev. 1.02 (30 Jan 2006) • Updated part ordering information
- Corrected recommended reset circuits to match corresponding description
- Added Micrel disclaimer to last page
- Corrected crystal/oscillator PPM in Reference Clock Connection Diagrams
- Added current consumption for KSZ8001L
- Correct RXC clock pulse width timing in 100BASE-TX MII Receive Timing Dia- gram
- Added description for Auto MDI/MDI-X mode in register 1f.15
- Updated description for MDI/MDI-X select in register 1f.14
- Corrected Auto-Negotiation Complete bit, register 1f.7, to read only
- Added “Circuit Design Reference for Power Supply” section
- Updated Pin Description for the followin g pins: MDIO, VDDIO, VDDC, RX+, RX- , TX+, TX-, XI, XO Rev. 1.01 (16 May 2005) • Changed REXT value to 6.65 K
- Removed preliminary status
- Added KSZ8001S to ordering information Rev. 1.00 (31 Mar 2005) • Added lead-free part numbers Rev. 0.82 (25 Jan 2005) • LinkMD distance coefficient changed to 0.39
- Interrupt register status bits set to RO/SC
- Recommended reset circuit added
- RMII timing added Rev. 0.81 (17 Sep 2004) • Updated series resistance for crystal specification to 40 Rev. 0.8 (9 Aug 2004) • Updated pin 38 (VDDRCV) definition to 3.3V
- Corrected pin configuration diagrams to reflect NC on pins 42 and 43
- Updated crystal tolerance to +/- 50 ppm PRELIMINARY (25 Mar 2004) Preliminary data
DS00003062A-page 48 2009-2019 Microchip Technology Inc. THE MICROCHIP WEB SITE Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site con- tains the following information:
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- Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of semi- nars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revi sions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com. Under “Support”, click on “Customer Change Notifi- cation” and follow the registration instructions. CUSTOMER SUPPORT Users of Microchip products can receive assistance through several channels:
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2009-2019 Microchip Technology Inc. DS00003062A-page 49 KSZ8001L/S PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. Device: KSZ8001L(2), KSZ8001S Temperature: Blank = 0 C to +70 C (Commercial) I= - 4 0 C to +85 C (Industrial) Package: S = 48-pin SSOP 48-pin LQFP also offered (2) Tape and Reel Option: Blank = Standard packaging (tray) TR = Tape and Reel (1) Examples: a) KSZ8001L Commercial Temperature, Integrated LDO 48-pin LQFP RoHS Compliant Pkg, Tray b) KSZ8001L-TR Commercial Temperature, Integrated LDO 48-pin LQFP RoHS Compliant Pkg, Tape & Reel c) KSZ8001LI Industrial Temperature, Integrated LDO 48-pin LQFP RoHS Compliant Pkg, Tray d) KSZ8001LI-TR Industrial Temperature, Integrated LDO 48-pin LQFP RoHS Compliant Pkg, Tape & Reel e) KSZ8001SL Commercial Temperature, no Integrated LDO 48-pin SSOP RoHS Compliant Pkg, Tape & Reel f) KSZ8001SL-TR Commercial Temperature, no Integrated LDO 48-pin SSOP RoHS Compliant Pkg, Tape & Reel Note 1: Tape and Reel identifier only appears in the catalog part number description. This identifier is used for ordering purposes and is not printed on the device package. Check with your Microchip Sales Office for package availability with the Tape and Reel option. 2: L = built-in 1.8V regulator PART NO. [X] XXX PackageTemperature Range Device X Tape and Reel Option - -
DS00003062A-page 50 2009-2019 Microchip Technology Inc. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Micro- chip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless otherwise stated. Trademarks The Microchip name and logo, the Microchip logo, Adaptec, AnyRate, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, chipKIT, chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck, LinkMD, maXStylus, maXTouch, MediaLB, megaAVR, Microsemi, Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer, PackeTime, PIC, picoPower, PICSTART, PIC32 logo, PolarFire, Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST, SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon, TempTrackr, TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. APT, ClockWorks, The Embedded Control Solutions Company, EtherSynch, FlashTec, Hyper Speed Control, HyperLight Load, IntelliMOS, Libero, motorBench, mTouch, Powermite 3, Precision Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet-Wire, SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub, TimePictra, TimeProvider, Vite, WinPath, and ZL are registered trademarks of Microchip Technology Incorporated in the U.S.A. Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BlueSky, BodyCom, CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, Crypto Controller, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, INICnet, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, memBrain, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. The Adaptec logo, Frequency on Demand, Silicon Storage Technology, and Symmcom are registered trademarks of Microchip Technology Inc. in other countries. GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2009-2019, Microchip Technology Incorporated, All Rights Reserved. ISBN: 9781522444473 Note the following details of the code protection feature on Microchip devices:
- Microchip products meet the specification cont ained in their particular Microchip Data Sheet.
- Microchip believes that its family of pr oducts is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.
- There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
- Microchip is willing to work with the customer who is concerned about the integrity of their code.
- Neither Microchip nor any other semiconductor manufacturer can gu arantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. For information regarding Microchip’s Quality Management Systems, please visit www.microchip.com/quality.
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