KS8995MA

KS8995MA MICREL | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 73

Technical content

Features

• I ntegrated switch with five MACs and five Fast Ethernet transceivers fully compliant to IEEE 802.3u standard
• Shared memory based switch fabric with fully non- blocking configuration
• 1 .4Gbps high-performance memory bandwidth
• 10BASE-T, 100BASE-TX, and 100BASE-FX modes (FX in ports 4 and 5)
• Dual MII configuration: MII-Switch (MAC or PHY mode MII) and MII-P5 (PHY mode MII)
• I EEE 802.1q tag-based VLAN (16 VLANs, full-range VID) for DMZ port, WAN/LAN separation or inter-VLAN switch links
• VLAN ID tag/untag options, per-port basis
• P rogrammable rate limiting 0Mbps to 100Mbps, ingress and egress port, rate options for high and low priority, per-port basis in 32Kbps increments
• F low control or drop packet rate limiting (ingress port)
• I ntegrated MIB counters for fully compliant statistics gathering, 34 MIB counters per port Micrel, Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel + 1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com Functional Diagram 1K Look-Up Engine Queue Mgmnt MAC 1 Buffer Mgmnt Frame Buffers FIFO, Flow Contro l, VLAN Tag ging, Pri ority MAC 2 MAC 3 MAC 4 MAC 5 SNI T/Tx 1 T/Tx 2 T/Tx 3 T/Tx/Fx 4 T/Tx/Fx 5 SPI EEPROM I/F LED I/F Auto MDI/MDI-X Control Reg I/F KS8995MA MIB Counters MII-SW or SNI LED0[5:1] LED1[5:1] LED2[5:1] Control Registers MII-P5 MDC, MDI/O Auto MDI/MDI-X Auto MDI/MDI-X Auto MDI/MDI-X Auto MDI/MDI-X

KS8995MA Micrel, Inc. M9999-051305 2 May 2005 Features (continued)

• Enable/Disable option for huge frame size up to 1916 bytes per frame
• I GMP v1/v2 snooping for multicast packet filtering
• Special tagging mode to send CPU info on ingress packet’s port value
• SPI slave (complete) and MDIO (MII PHY only) serial management interface for control of register configura- tion
• MAC-id based security lock option
• Control registers configurable on-the-fly (port-priority, 802.1p/d/q, AN...)
• CPU read access to MAC forwarding table entries
• 802.1d Spanning Tree Protocol
• Port mirroring/monitoring/sniffing: ingress and/or egress traffic to any port or MII
• B roadcast storm protection with % control – global and per-port basis
• Optimization for fiber-to-copper media conversion
• Full-chip hardware power-down support (register configuration not saved)
• Per-port based software power-save on PHY (idle link detection, register configuration preserved)
• QoS/CoS packets prioritization supports: per port, 802.1p and DiffServ based
• 802.1p/q tag insertion or removal on a per-port basis (egress)
• MDC and MDI/O interface support to access the MII PHY control registers (not all control registers)
• M II local loopback support
• On-chip 64Kbyte memory for frame buffering (not shared with 1K unicast address table)
• W ire-speed reception and transmission
• I ntegrated look-up engine with dedicated 1K MAC addresses
• Full duplex IEEE 802.3x and half-duplex back pressure flow control
• Comprehensive LED support
• 7 -wire SNI support for legacy MAC interface
• Automatic MDI/MDI-X crossover for plug-and-play
• D isable automatic MDI/MDI-X option
• Low power: Core: 1.8V I/O: 2.5V or 3.3V
• 0 . 1 8µm CMOS technology
• Commercial temperature range: 0 °C to +70°C
• I ndustrial temperature range: –40 °C to +85°C
• Available in 128-pin PQFP package

Applications

• B roadband gateway/firewall/VPN
• I ntegrated DSL or cable modem multi-port router
• W ireless LAN access point plus gateway
• Home networking expansion
• S tandalone 10/100 switch
• Hotel/campus/MxU gateway
• Enterprise VoIP gateway/phone
• FTTx customer premise equipment
• Managed Media converter

Ordering Information

Part Number Temp. Range Package Lead Finish KS8995MA 0 °C to +70°C 128-Pin PQFP Standard KSZ8995MA 0 °C to +70°C 128-Pin PQFP Lead-Free KS8995MAI –40 °C to +85°C 128-Pin PQFP Standard

KS8995MA Micrel, Inc.

Revision History

Revision Date Summary of Changes 2.0 10/10/03 Created. 2.1 10/30/03 Editorial changes on electrical characteristics. 2.2 4/1/04 Editorial changes on the TTL input and output electrical characteristics. 2.4 4/13/05 Changed VDDIO to 3.3V. Changed Jitter to 16 ns Max.

KS8995MA Micrel, Inc. M9999-051305 4 May 2005 Table of Contents

KS8995MA Micrel, Inc.

KS8995MA Micrel, Inc. M9999-051305 6 May 2005

Figure 3. Standalone Switch

KS8995MA Micrel, Inc. Pin Description (by Number) Pin Number Pin Name Type (1) Port Pin Function (2) 1 MDI-XDIS Ipd 1-5 Disable auto MDI/MDI-X. PD (default) = normal operation. PU = disable auto MDI/MDI-X on all ports. 2 GNDA Gnd Analog ground. 3 VDDAR P 1.8V analog V DD. 4 RXP1 I 1 Physical receive signal + (differential). 5 RXM1 I 1 Physical receive signal – (differential). 6 GNDA Gnd Analog ground. 7 TXP1 O 1 Physical transmit signal + (differential). 8 TXM1 O 1 Physical transmit signal – (differential). 9 VDDAT P 2.5V or 3.3V analog V DD. 10 RXP2 I 2 Physical receive signal + (differential). 11 RXM2 I 2 Physical receive signal - (differential). 12 GNDA Gnd Analog ground. 13 TXP2 O 2 Physical transmit signal + (differential). 14 TXM2 O 2 Physical transmit signal – (differential). 15 VDDAR P 1.8V analog V DD. 16 GNDA Gnd Analog ground. 17 ISET Set physical transmit output current. Pull-down with a 3.01k Ω 1% resistor. 18 VDDAT P 2.5V or 3.3V analog V DD. 19 RXP3 I 3 Physical receive signal + (differential). 20 RXM3 I 3 Physical receive signal – (differential). 21 GNDA Gnd Analog ground. 22 TXP3 O 3 Physical transmit signal + (differential). 23 TXM3 O 3 Physical transmit signal – (differential). 24 VDDAT P 2.5V or 3.3V analog V DD. 25 RXP4 I 4 Physical receive signal + (differential). 26 RXM4 I 4 Physical receive signal – (differential). 27 GNDA Gnd Analog ground. 28 TXP4 O 4 Physical transmit signal + (differential). 29 TXM4 O 4 Physical transmit signal – (differential). 30 GNDA Gnd Analog ground. Note: 1. P = Power supply. I = Input. O = Output. I/O = Bidirectional. Gnd = Ground. Ipu = Input w/ internal pull-up. Ipd = Input w/ internal pull-down. Ipd/O = Input w/ internal pull-down during reset, output pin otherwise. Ipu/O = Input w/ internal pull-up during reset, output pin otherwise. NC = No connect. 2. PU = Strap pin pull-up. PD = Strap pin pull-down.

KS8995MA Micrel, Inc. M9999-051305 10 May 2005 Pin Number Pin Name Type (1) Port Pin Function 31 VDDAR P 1.8V analog V DD. 32 RXP5 I 5 Physical receive signal + (differential). 33 RXM5 I 5 Physical receive signal – (differential). 34 GNDA Gnd Analog ground. 35 TXP5 O 5 Physical transmit signal + (differential). 36 TXM5 O 5 Physical transmit signal – (differential). 37 VDDAT P 2.5V or 3.3V analog V DD. 38 FXSD5 I 5 Fiber signal detect/factory test pin. 39 FXSD4 I 4 Fiber signal detect/factory test pin. 40 GNDA Gnd Analog ground. 41 VDDAR P 1.8V analog V DD. 42 GNDA Gnd Analog ground. 43 VDDAR P 1.8V analog V DD. 44 GNDA Gnd Analog ground. 45 MUX1 NC Factory test pins. MUX1 and MUX2 should be left unconnected for 46 MUX2 NC normal operation. Mode MUX1 MUX2 Normal Operation NC NC 47 PWRDN_N Ipu Full-chip power down. Active low. 48 RESERVE NC Reserved pin. No connect. 49 GNDD Gnd Digital ground. 50 VDDC P 1.8V digital core V DD. 51 PMTXEN Ipd 5 PHY[5] MII transmit enable. 52 PMTXD3 Ipd 5 PHY[5] MII transmit bit 3. 53 PMTXD2 Ipd 5 PHY[5] MII transmit bit 2. 54 PMTXD1 Ipd 5 PHY[5] MII transmit bit 1. 55 PMTXD0 Ipd 5 PHY[5] MII transmit bit 0. 56 PMTXER Ipd 5 PHY[5] MII transmit error. 57 PMTXC O 5 PHY[5] MII transmit clock. PHY mode MII. 58 GNDD Gnd Digital ground. 59 VDDIO P 3.3V digital V DD for digital I/O circuitry. 60 PMRXC O 5 PHY[5] MII receive clock. PHY mode MII. Note: 1. P = Power supply. I = Input. O = Output. I/O = Bidirectional. Gnd = Ground. Ipu = Input w/ internal pull-up. Ipd = Input w/ internal pull-down. Ipd/O = Input w/ internal pull-down during reset, output pin otherwise. Ipu/O = Input w/ internal pull-up during reset, output pin otherwise. NC = No connect.

KS8995MA Micrel, Inc. Pin Number Pin Name Type (1) Port Pin Function (2) 61 PMRXDV Ipd/O 5 PHY[5] MII receive data valid. 62 PMRXD3 Ipd/O 5 PHY[5] MII receive bit 3. Strap option: PD (default) = enable flow control; PU = disable flow control. 63 PMRXD2 Ipd/O 5 PHY[5] MII receive bit 2. Strap option: PD (default) = disable back pressure; PU = enable back pressure. 64 PMRXD1 Ipd/O 5 PHY[5] MII receive bit 1. Strap option: PD (default) = drop excessive collision packets; PU = does not drop excessive collision packets. 65 PMRXD0 Ipd/O 5 PHY[5] MII receive bit 0. Strap option: PD (default) = disable aggressive back-off algorithm in half-duplex mode; PU = enable for performance enhancement. 66 PMRXER Ipd/O 5 PHY[5] MII receive error. Strap option: PD (default) = 1522/1518 bytes; PU = packet size up to 1536 bytes. 67 PCRS Ipd/O 5 PHY[5] MII carrier sense/force duplex mode. See “Register 76” for port 4 only. PD (default) = force half-duplex if auto-negotiation is disabled or fails. PU = force full-duplex if auto-negotiation is disabled or fails. 68 PCOL Ipd/O 5 PHY[5] MII collision detect/force flow control. See “Register 66” for port 4 only. PD (default) = no force flow control. normal operation. PU = force flow control. 69 SMTXEN Ipd Switch MII transmit enable. 70 SMTXD3 Ipd Switch MII transmit bit 3. 71 SMTXD2 Ipd Switch MII transmit bit 2. 72 SMTXD1 Ipd Switch MII transmit bit 1. 73 SMTXD0 Ipd Switch MII transmit bit 0. 74 SMTXER Ipd Switch MII transmit error. 75 SMTXC I/O Switch MII transmit clock. Input in MAC mode, output in PHY mode MII. 76 GNDD Gnd Digital ground. 77 VDDIO P 3.3V digital V DD for digital I/O circuitry 78 SMRXC I/O Switch MII receive clock. Input in MAC mode, output in PHY mode MII.

79 SMRXDV Ipd/O Switch MII receive data valid

80 SMRXD3 Ipd/O Switch MII receive bit 3. Strap option: PD (default) = Disable Switch MII full-duplex flow control; PU = enable switch MII full-duplex flow control. 81 SMRXD2 Ipd/O Switch MII receive bit 2. Strap option: PD (default) = switch MII in full duplex mode; PU = switch MII in half-duplex mode. Note: 1. P = Power supply. I = Input. O = Output. I/O = Bidirectional. Gnd = Ground. Ipu = Input w/ internal pull-up. Ipd = Input w/ internal pull-down. Ipd/O = Input w/ internal pull-down during reset, output pin otherwise. Ipu/O = Input w/ internal pull-up during reset, output pin otherwise. NC = No connect. 2. PU = Strap pin pull-up. PD = Strap pin pull-down.

KS8995MA Micrel, Inc. M9999-051305 12 May 2005 Pin Number Pin Name Type (1) Port Pin Function (2) 82 SMRXD1 Ipd/O Switch MII receive bit 1. Strap option: PD (default) = switch MII in 100Mbps mode; PU = switch MII in 10Mbps mode. 83 SMRXD0 Ipd/O Switch MII receive bit 0. Strap option: LED mode PD (default) = mode 0; PU = mode 1. See “Register 11.” Mode 0 Mode 1 LEDX_2 Lnk/Act 100Lnk/Act LEDX_1 Fulld/Col 10Lnk/Act LEDX_0 Speed Full duplex 84 SCOL Ipd/O Switch MII collision detect. 85 SCRS Ipd/O Switch MII carrier sense. 86 SCONF1 Ipd Dual MII configuration pin. Pin (91, 86, 87): Switch MII PHY [5] MII

000 Disable, Otri Disable, Otri

001 PHY Mode MII Disable, Otri

010 MAC Mode MII Disable, Otri

011 PHY Mode SNI Disable, Otri

100 Disable Disable

101 PHY Mode MII PHY Mode MII

110 MAC Mode MII PHY Mode MII

111 PHY Mode SNI PHY Mode MII

87 SCONF0 Ipd Dual MII configuration pin. 88 GNDD Gnd Digital ground. 89 VDDC P 1.8V digital core V DD. 90 LED5-2 Ipu/O 5 LED indicator 2. Strap option: aging setup. See “Aging” section. PU (default) = aging enable; PD = aging disable. 91 LED5-1 Ipu/O 5 LED indicator 1. Strap option: PU (default) = enable PHY MII I/F. PD: tristate all PHY MII output. See “Pin 86 SCONF1.”

92 LED5-0 Ipu/O 5 LED indicator 0

93 LED4-2 Ipu/O 4 LED indicator 2

94 LED4-1 Ipu/O 4 LED indicator 1

95 LED4-0 Ipu/O 4 LED indicator 0

96 LED3-2 Ipu/O 3 LED indicator 2

97 LED3-1 Ipu/O 3 LED indicator 1

Note: 1. P = Power supply. I = Input. O = Output. I/O = Bidirectional. Gnd = Ground. Ipu = Input w/ internal pull-up. Ipd = Input w/ internal pull-down. Ipd/O = Input w/ internal pull-down during reset, output pin otherwise. Ipu/O = Input w/ internal pull-up during reset, output pin otherwise. NC = No connect. 2. PU = Strap pin pull-up. Otri = Output tristated. PD = Strap pin pull-down. Fulld = Full duplex.

KS8995MA Micrel, Inc. Pin Number Pin Name Type (1) Port Pin Function 98 LED3-0 Ipu/O 3 LED indicator 0. 99 GNDD Gnd Digital ground. 100 VDDIO P 3.3V digital V DD for digital I/O. 101 LED2-2 Ipu/O 2 LED indicator 2. 102 LED2-1 Ipu/O 2 LED indicator 1. 103 LED2-0 Ipu/O 2 LED indicator 0. 104 LED1-2 Ipu/O 1 LED indicator 2. 105 LED1-1 Ipu/O 1 LED indicator 1. 106 LED1-0 Ipu/O 1 LED indicator 0. 107 MDC Ipu All Switch or PHY[5] MII management data clock. 108 MDIO I/O All Switch or PHY[5] MII management data I/O. Features internal pull down to define pin state when not driven.

109 SPIQ Otri All (1) SPI serial data output in SPI slave mode; (2) not used in I2C master

mode. See “Pin 113.”

110 SPIC/SCL I/O All (1) Input clock up to 5MHz in SPI slave mode; (2) output clock at

81kHz in I2C master mode. See “Pin 113.”

111 SPID/SDA I/O All (1) Serial data input in SPI slave mode; (2) serial data input/output in

I2C master mode. See “Pin 113.” 112 SPIS_N Ipu All Active low. (1) SPI data transfer start in SPI slave mode. When SPIS_N is high, the KS8995MA is deselected and SPIQ is held in high impedance state, a high-to-low transition to initiate the SPI data transfer; (2) not used in I2C master mode. 113 PS1 Ipd Serial bus configuration pin. For this case, if the EEPROM is not present, the KS8995MA will start itself with the PS[1:0] = 00 default register values . Pin Configuration Serial Bus Configuration PS[1:0]=00 I 2C Master Mode for EEPROM PS[1:0]=01 Reserved PS[1:0]=10 SPI Slave Mode for CPU Interface PS[1:0]=11 Factory Test Mode (BIST) 114 PS0 Ipd Serial bus configuration pin. See “Pin 113.” 115 RST_N Ipu Reset the KS8995MA. Active low. 116 GNDD Gnd Digital ground. 117 VDDC P 1.8V digital core V DD. 118 TESTEN Ipd NC for normal operation. Factory test pin. Note: 1. P = Power supply. I = Input. O = Output. I/O = Bidirectional. Gnd = Ground. Ipu = Input w/ internal pull-up. Ipd = Input w/ internal pull-down. Ipd/O = Input w/ internal pull-down during reset, output pin otherwise. Ipu/O = Input w/ internal pull-up during reset, output pin otherwise. NC = No connect.

KS8995MA Micrel, Inc. M9999-051305 14 May 2005 Pin Number Pin Name Type (1) Port Pin Function 119 SCANEN Ipd NC for normal operation. Factory test pin. 120 NC NC No connect. 121 X1 I 25MHz crystal clock connection/or 3.3V tolerant oscillator input. Oscillator should be ±100ppm. 122 X2 O 25MHz crystal clock connection. 123 VDDAP P 1.8V analog V DD for PLL. 124 GNDA Gnd Analog ground. 125 VDDAR P 1.8V analog V DD. 126 GNDA Gnd Analog ground. 127 GNDA Gnd Analog ground. 128 TEST2 NC NC for normal operation. Factory test pin. Note: 1. P = Power supply. I = Input. O = Output. I/O = Bidirectional. Gnd = Ground. Ipu = Input w/ internal pull-up. Ipd = Input w/ internal pull-down. Ipd/O = Input w/ internal pull-down during reset, output pin otherwise. Ipu/O = Input w/ internal pull-up during reset, output pin otherwise. NC = No connect.

KS8995MA Micrel, Inc. Pin Description (by Name) Pin Number Pin Name Type (1) Port Pin Function 39 FXSD4 I 4 Fiber signal detect/factory test pin. 38 FXSD5 I 5 Fiber signal detect/factory test pin. 124 GNDA Gnd Analog ground. 42 GNDA Gnd Analog ground. 44 GNDA Gnd Analog ground. 2 GNDA Gnd Analog ground. 16 GNDA Gnd Analog ground. 30 GNDA Gnd Analog ground. 6 GNDA Gnd Analog ground. 12 GNDA Gnd Analog ground. 21 GNDA Gnd Analog ground. 27 GNDA Gnd Analog ground. 34 GNDA Gnd Analog ground. 40 GNDA Gnd Analog ground. 120 NC NC No connect. 127 GNDA Gnd Analog ground. 126 GNDA Gnd Analog ground. 49 GNDD Gnd Digital ground. 88 GNDD Gnd Digital ground. 116 GNDD Gnd Digital ground. 58 GNDD Gnd Digital ground. 76 GNDD Gnd Digital ground. 99 GNDD Gnd Digital ground. 17 ISET Set physical transmit output current. Pull-down with a 3.01k Ω 1% resistor. 106 LED1-0 Ipu/O 1 LED indicator 0. 105 LED1-1 Ipu/O 1 LED indicator 1. 104 LED1-2 Ipu/O 1 LED indicator 2. 103 LED2-0 Ipu/O 2 LED indicator 0. 102 LED2-1 Ipu/O 2 LED indicator 1. 101 LED2-2 Ipu/O 2 LED indicator 2. 98 LED3-0 Ipu/O 3 LED indicator 0. Note: 1. P = Power supply. I = Input. O = Output. I/O = Bidirectional. Gnd = Ground. Ipu = Input w/ internal pull-up. Ipd = Input w/ internal pull-down. Ipd/O = Input w/ internal pull-down during reset, output pin otherwise. Ipu/O = Input w/ internal pull-up during reset, output pin otherwise. NC = No connect.

KS8995MA Micrel, Inc. M9999-051305 16 May 2005 Pin Number Pin Name Type (1) Port Pin Function(2) 97 LED3-1 Ipu/O 3 LED indicator 1. 96 LED3-2 Ipu/O 3 LED indicator 2. 95 LED4-0 Ipu/O 4 LED indicator 0. 94 LED4-1 Ipu/O 4 LED indicator 1. 93 LED4-2 Ipu/O 4 LED indicator 2. 92 LED5-0 Ipu/O 5 LED indicator 0. 91 LED5-1 Ipu/O 5 LED indicator 1. Strap option: PU (default) = enable PHY MII I/F PD: tristate all PHY MII output. See “Pin 86 SCONF1.” 90 LED5-2 Ipu/O 5 LED indicator 2. Strap option: aging setup. See “Aging” section. (default) = aging enable; PD = aging disable. 107 MDC Ipu All Switch or PHY[5] MII management data clock. 108 MDIO I/O All Switch or PHY[5] MII management data I/O. 1 MDI-XDIS Ipd 1-5 Disable auto MDI/MDI-X. 45 MUX1 NC Factory test pins. MUX1 and MUX2 should be left unconnected for 46 MUX2 NC normal operation. Mode MUX1 MUX2 Normal Operation NC NC 68 PCOL Ipd/O 5 PHY[5] MII collision detect/force flow control. See “Register 18.” For port 4 only. PD (default) = no force flow control. PU = force flow control. 67 PCRS Ipd/O 5 PHY[5] MII carrier sense/force duplex mode. See “Register 28.” For port 4 only. PD (default) = force half-duplex if auto-negotiation is disabled or fails. PU = force full-duplex if auto-negotiation is disabled or fails. 60 PMRXC O 5 PHY[5] MII receive clock. PHY mode MII. 65 PMRXD0 Ipd/O 5 PHY[5] MII receive bit 0. Strap option: PD (default) = disable aggressive back-off algorithm in half-duplex mode; PU = enable for performance enhancement. 64 PMRXD1 Ipd/O 5 PHY[5] MII receive bit 1. Strap option: PD (default) = drop excessive collision packets; PU = does not drop excessive collision packets. 63 PMRXD2 Ipd/O 5 PHY[5] MII receive bit 2. Strap option: PD (default) = disable back pressure; PU = enable back pressure. 62 PMRXD3 Ipd/O 5 PHY[5] MII receive bit 3. Strap option: PD (default) = enable flow control; PU = disable flow control. 61 PMRXDV Ipd/O 5 PHY[5] MII receive data valid. 66 PMRXER Ipd/O 5 PHY[5] MII receive error. Strap option: PD (default) = 1522/1518 bytes; PU = packet size up to 1536 bytes. Note: 1. P = Power supply. I = Input. O = Output. I/O = Bidirectional. Gnd = Ground. Ipu = Input w/ internal pull-up. Ipd = Input w/ internal pull-down. Ipd/O = Input w/ internal pull-down during reset, output pin otherwise. Ipu/O = Input w/ internal pull-up during reset, output pin otherwise. NC = No connect. 2. PU = Strap pin pull-up. PD = Strap pin pull-down.

KS8995MA Micrel, Inc. Pin Number Pin Name Type (1) Port Pin Function 57 PMTXC O 5 PHY[5] MII transmit clock. PHY mode MII. 55 PMTXD0 Ipd 5 PHY[5] MII transmit bit 0. 54 PMTXD1 Ipd 5 PHY[5] MII transmit bit 1. 53 PMTXD2 Ipd 5 PHY[5] MII transmit bit 2. 52 PMTXD3 Ipd 5 PHY[5] MII transmit bit 3. 51 PMTXEN Ipd 5 PHY[5] MII transmit enable. 56 PMTXER Ipd 5 PHY[5] MII transmit error. 114 PS0 Ipd Serial bus configuration pin. See “Pin 113.” 113 PS1 Ipd Serial bus configuration pin. If EEPROM is not present, the KS8995MA will start itself with chip default (00)... Pin Configuration Serial Bus Configuration PS[1:0]=00 I 2C Master Mode for EEPROM PS[1:0]=01 Reserved PS[1:0]=10 SPI Slave Mode for CPU Interface PS[1:0]=11 Factory Test Mode (BIST) 47 PWRDN_N Ipu Full-chip power down. Active low. 48 RESERVE NC Reserved pin. No connect. 115 RST_N Ipu Reset the KS8995MA. Active low. 5 RXM1 I 1 Physical receive signal – (differential). 11 RXM2 I 2 Physical receive signal – (differential). 20 RXM3 I 3 Physical receive signal – (differential). 26 RXM4 I 4 Physical receive signal – (differential). 33 RXM5 I 5 Physical receive signal – (differential). 4 RXP1 I 1 Physical receive signal + (differential). 10 RXP2 I 2 Physical receive signal + (differential). 19 RXP3 I 3 Physical receive signal + (differential). 25 RXP4 I 4 Physical receive signal + (differential). 32 RXP5 I 5 Physical receive signal + (differential). 119 SCANEN Ipd NC for normal operation. Factory test pin. 84 SCOL Ipd/O Switch MII collision detect. 87 SCONF0 Ipd Dual MII configuration pin. Note: 1. P = Power supply. I = Input. O = Output. I/O = Bidirectional. Gnd = Ground. Ipu = Input w/ internal pull-up. Ipd = Input w/ internal pull-down. Ipd/O = Input w/ internal pull-down during reset, output pin otherwise. Ipu/O = Input w/ internal pull-up during reset, output pin otherwise. NC = No connect.

KS8995MA Micrel, Inc. M9999-051305 18 May 2005 Pin Number Pin Name Type (1) Port Pin Function(2) 86 SCONF1 Ipd Dual MII configuration pin. Pin (91, 86, 87): Switch MII PHY [5] MII 85 SCRS Ipd/O Switch MII carrier sense. 78 SMRXC I/O Switch MII receive clock. Input in MAC mode, output in PHY mode MII.

83 SMRXD0 Ipd/O Switch MII receive bit 0; strap option: LED mode

PD (default) = mode 0; PU = mode 1. See “Register 11.” Mode 0 Mode 1 LEDX_2 Lnk/Act 100Lnk/Act LEDX_1 Fulld/Col 10Lnk/Act LEDX_0 Speed Full duplex 82 SMRXD1 Ipd/O Switch MII receive bit 1. Strap option: PD (default) = switch MII in 100Mbps mode; PU = switch MII in 10Mbps mode. 81 SMRXD2 Ipd/O Switch MII receive bit 2. Strap option: PD (default) = switch MII in full-duplex mode; PU = switch MII in half-duplex mode. 80 SMRXD3 Ipd/O Switch MII receive bit 3. Strap option: PD (default) = disable switch MII full-duplex flow control; PU = enable switch MII full-duplex flow control. 79 SMRXDV Ipd/O Switch MII receive data valid. 75 SMTXC I/O Switch MII transmit clock. Input in MAC mode, output in PHY mode MII. 73 SMTXD0 Ipd Switch MII transmit bit 0. 72 SMTXD1 Ipd Switch MII transmit bit 1. 71 SMTXD2 Ipd Switch MII transmit bit 2. 70 SMTXD3 Ipd Switch MII transmit bit 3. 69 SMTXEN Ipd Switch MII transmit enable. 74 SMTXER Ipd Switch MII transmit error. Note: 1. P = Power supply. I = Input. O = Output. I/O = Bidirectional. Gnd = Ground. Ipu = Input w/ internal pull-up. Ipd = Input w/ internal pull-down. Ipd/O = Input w/ internal pull-down during reset, output pin otherwise. Ipu/O = Input w/ internal pull-up during reset, output pin otherwise. Otri = Output tristated. NC = No connect. 2. PU = Strap pin pull-up. PD = Strap pin pull-down. Fulld = Full duplex.

KS8995MA Micrel, Inc. Pin Number Pin Name Type (1) Port Pin Function

110 SPIC/SCL I/O All (1) Input clock up to 5MHz in SPI slave mode; (2) Output clock at 81kHz

in I2C master mode. See “Pin 113.” I2C master mode. See “Pin 113.” mode. See “Pin 113.” 112 SPIS_N Ipu All Active low. (1) SPI data transfer start in SPI slave mode. When SPIS_N is high, the KS8995MA is deselected and SPIQ is held in high impedance state, a high-to-low transition to initiate the SPI data transfer; (2) Not used in I2C master mode. 128 TEST2 NC No connect for normal operation. Factory test pin. 118 TESTEN Ipd No connect for normal operation. Factory test pin. 8 TXM1 O 1 Physical transmit signal – (differential). 14 TXM2 O 2 Physical transmit signal – (differential). 23 TXM3 O 3 Physical transmit signal – (differential). 29 TXM4 O 4 Physical transmit signal – (differential). 36 TXM5 O 5 Physical transmit signal – (differential). 7 TXP1 O 1 Physical transmit signal + (differential). 13 TXP2 O 2 Physical transmit signal + (differential). 22 TXP3 O 3 Physical transmit signal + (differential). 28 TXP4 O 4 Physical transmit signal + (differential). 35 TXP5 O 5 Physical transmit signal + (differential). 123 VDDAP P 1.8V analog V DD for PLL. 41 VDDAR P 1.8V analog V DD. 43 VDDAR P 1.8V analog V DD. 3 VDDAR P 1.8V analog V DD. 15 VDDAR P 1.8V analog V DD. 31 VDDAR P 1.8V analog V DD. 125 VDDAR P 1.8V analog V DD. 18 VDDAT P 2.5V or 3.3V analog V DD. 9 VDDAT P 2.5V or 3.3V analog V DD. 24 VDDAT P 2.5V or 3.3V analog V DD. 37 VDDAT P 2.5V or 3.3V analog V DD. 50 VDDC P 1.8V digital core V DD. Note: 1. P = Power supply. I = Input. O = Output. I/O = Bidirectional. Gnd = Ground. Ipu = Input w/ internal pull-up. Ipd = Input w/ internal pull-down. Ipd/O = Input w/ internal pull-down during reset, output pin otherwise. Ipu/O = Input w/ internal pull-up during reset, output pin otherwise. Otri = Output tristated. NC = No connect.

KS8995MA Micrel, Inc. M9999-051305 20 May 2005 Pin Number Pin Name Type (1) Port Pin Function 89 VDDC P 1.8V digital core V DD. 117 VDDC P 1.8V digital core V DD. 59 VDDIO P 3.3V digital V DD for digital I/O circuitry. 77 VDDIO P 3.3V digital V DD for digital I/O circuitry. 100 VDDIO P 3.3V digital V DD for digital I/O circuitry. 121 X1 I 25MHz crystal clock connection/or 3.3V tolerant oscillator input. Oscillator should be ±100ppm. 122 X2 O 25MHz crystal clock connection. Note: 1. P = Power supply. I = Input. O = Output.

KS8995MA Micrel, Inc. Pin Configuration MDIXDIS GNDA VDDAR RXP1 RXM1 GNDA TXP1 TXM1 VDDAT RXP2 RXM2 GNDA TXP2 TXM2 VDDAR GNDA ISET VDDAT RXP3 RXM3 GNDA TXP3 TXM3 VDDAT RXP4 RXM4 GNDA TXP4 TXM4 GNDA VDDAR RXP5 RXM5 GNDA TXP5 TXM5 VDDAT FXSD5 LED2-1 LED2-2 VDDIO GNDD LED3-0 LED3-1 LED3-2 LED4-0 LED4-1 LED4-2 LED5-0 LED5-1 LED5-2 VDDC GNDD SCONF0 SCONF1 SCRS SCOL SMRXD0 SMRXD1 SMRXD2 SMRXD3 SMRXDV SMRXC VDDIO GNDD SMTXC SMTXER SMTXD0 SMTXD1 SMTXD2 SMTXD3 SMTEXN PCOL PCRS PMRXER PMRXD0 PMRXD1 PMRXD2 PMRXD3 PMRXDV PMRXC VDDIO GNDD PMTXC PMTXER PMTXD0 PMTXD1 PMTXD2 PMTXD3 PMTXEN VDDC GNDD RESERVE PWRDN_N MUX2 MUX1 GNDA VDDAR GNDA VDDAR GNDA FXSD4 LED2-0 LED1-2 LED1-1 LED1-0 MDC MDIO SPIQ SPIC/SCL SPID/SDA SPIS_N PS1 PS0 RST_N GNDD VDDC TESTEN SCANEN NC VDDAP GNDA VDDAR GNDA GNDA TEST2 103 128-Pin PQFP (PQ)

KS8995MA Micrel, Inc. M9999-051305 22 May 2005 Introduction The KS8995MA contains five 10/100 physical layer transceivers and five media access control (MAC) units with an integrated Layer 2 managed switch. The device runs in three modes. The first mode is as a five-port integrated switch. The second is as a five-port switch with the fifth port decoupled from the physical port. In this mode, access to the fifth MAC is provided through a media independent interface (MII) . This is useful for implementing an integrated broadband router. The third mode uses the dual MII feature to recover the use of the fifth PHY. This allows the additional broadband gateway configuration, where the fifth PHY may be accessed through the MII-P5 port. The KS8995MA has the flexibility to reside in a managed or unmanaged design. In a managed design, a host processor has complete control of the KS8995MA via the SPI bus, or partial control via the MDC/MDIO interface. An unmanaged design is achieved through I/O strapping or EEPROM programming at system reset time. On the media side, the KS8995MA supports IEEE 802.3 10BASE-T, 100BASE-TX on all ports, and 100BASE-FX on ports 4 and 5. The KS8995MA can be used as two separate media converters. Physical signal transmission and reception are enhanced through the use of patented analog circuitry that makes the design more efficient and allows for lower power consumption and smaller chip die size. The major enhancements from the KS8995E to the KS8995MA are support for host processor management, a dual MII interface, tag as well as port based VLAN, spanning tree protocol support, IGMP snooping support, port mirroring support and rate limiting functionality. Functional Overview: Physical Layer Transceiver 100BASE-TX Transmit The 100BASE-TX transmit function performs parallel-to-serial conversion, 4B/5B coding, scrambling, NRZ-to-NRZI conver- sion, MLT3 encoding and transmission. The circuit starts with a parallel-to-serial conversion, which converts the MII data from the MAC into a 125MHz serial bit stream. The data and control stream is then converted into 4B/5B coding followed by a scrambler. The serialized data is further converted from NRZ-to-NRZI format, and then transmitted in MLT3 current output. The output current is set by an external 1% 3.01kΩ resistor for the 1:1 transformer ratio. It has a typical rise/fall time of 4ns and complies with the ANSI TP-PMD standard regarding amplitude balance, overshoot, and timing jitter. The wave-shaped 10BASE-T output is also incorporated into the 100BASE-TX transmitter. 100BASE-TX Receive The 100BASE-TX receiver function performs adaptive equalization, DC restoration, MLT3-to-NRZI conversion, data and clock recovery, NRZI-to-NRZ conversion, de-scrambling, 4B/5B decoding, and serial-to-parallel conversion. The receiving side starts with the equalization filter to compensate for inter-symbol interference (ISI) over the twisted pair cable. Since the amplitude loss and phase distortion is a function of the length of the cable, the equalizer has to adjust its characteristics t o optimize the performance. In this design, the variable equalizer will make an initial estimation based on comparisons of incoming signal strength against some known cable characteristics, then tunes itself for optimization. This is an ongoing process and can self-adjust against environmental changes such as temperature variations. The equalized signal then goes through a DC restoration and data conversion block. The DC restoration circuit is used to compensate for the effect of baseline wander and improve the dynamic range. The differential data conversion circuit converts the MLT3 format back to NRZI. The slicing threshold is also adaptive. The clock recovery circuit extracts the 125MHz clock from the edges of the NRZI signal. This recovered clock is then used to convert the NRZI signal into the NRZ format. The signal is then sent through the de-scrambler followed by the 4B/5B decoder. Finally, the NRZ serial data is converted to the MII format and provided as the input data to the MAC. PLL Clock Synthesizer The KS8995MA generates 125MHz, 42MHz, 25MHz, and 10MHz clocks for system timing. Internal clocks are generated from an external 25MHz crystal or oscillator. Scrambler/De-scrambler (100BASE-TX only) The purpose of the scrambler is to spread the power spectrum of the signal in order to reduce EMI and baseline wander. The data is scrambled through the use of an 11-bit wide linear feedback shift register (LFSR). This can generate a 2047-bit non- repetitive sequence. The receiver will then de-scramble the incoming data stream with the same sequence at the transmitter. 100BASE-FX Operation 100BASE-FX operation is very similar to 100BASE-TX operation except that the scrambler/de-scrambler and MLT3 encoder/ decoder are bypassed on transmission and reception. In this mode the auto-negotiation feature is bypassed since there is no standard that supports fiber auto-negotiation. 100BASE-FX Signal Detection The physical port runs in 100BASE-FX mode if FXSDx >0.6V for ports 4 and 5 only. This signal is internally referenced to 1.25V. The fiber module interface should be set by a voltage divider such that FXSDx ‘H’ is above this 1.25V reference, indicating signal

is disabled. Since there is no auto-negotiation for 100BASE-FX mode, ports 4 and 5 must be forced to either full or half-duplex. Note that strap-in options exist to set duplex mode for port 4, but not for port 5. far end fault may be disabled through register settings. 27dB below the fundamental when driven by an all-ones Manchester-encoded signal. the entire chip will be shutdown. The flow for the link setup is shown in Figure 4. Figure 4. Auto-Negotiation

KS8995MA Micrel, Inc. M9999-051305 24 May 2005 Functional Overview: Switch Core Address Look-Up The internal look-up table stores MAC addresses and their associated information. It contains a 1K unicast address table plus switching information. The KS8995MA is guaranteed to learn 1K addresses and distinguishes itself from a hash-based look- up table, which depending on the operating environment and probabilities, may not guarantee the absolute number of addresses it can learn. Learning The internal look-up engine updates its table with a new entry if the following conditions are met:

• The received packet’s source address (SA) does not exist in the look-up table.
• The received packet is good; the packet has no receiving errors and is of legal length. The look-up engine inserts the qualified SA into the table, along with the port number and time stamp. If the table is full, the last entry of the table is deleted first to make room for the new entry. Migration The internal look-up engine also monitors whether a station is moved. If this occurs, it updates the table accordingly. Migration happens when the following conditions are met:
• The received packet’s SA is in the table but the associated source port information is different.
• The received packet is good; the packet has no receiving errors and is of legal length. The look-up engine will update the existing record in the table with the new source port information. Aging The look-up engine will update the time stamp information of a record whenever the corresponding SA appears. The time stamp is used in the aging process. If a record is not updated for a period of time, the look-up engine will remove the record from the table. The look-up engine constantly performs the aging process and will continuously remove aging records. The aging period is 300 + 75 seconds. This feature can be enabled or disabled through Register 3 or by external pull-up or pull-down resistors on LED[5][2]. See “Register 3” section. Forwarding The KS8995MA will forward packets using an algorithm that is depicted in the following flowcharts. Figure 5 shows stage one of the forwarding algorithm where the search engine looks up the VLAN ID, static table, and dynamic table for the destination address, and comes up with “port to forward 1” (PTF1). PTF1 is then further modified by the spanning tree, IGMP snooping, port mirroring, and port VLAN processes to come up with “port to forward 2” (PTF2), as shown in Figure 6. This is where the packet will be sent. KS8995MA will not forward the following packets:
• E rror packets. These include framing errors, FCS errors, alignment errors, and illegal size packet errors.
• 802.3x pause frames. The KS8995MA will intercept these packets and perform the appropriate actions.
• “ Local” packets. Based on destination address (DA) look-up. If the destination port from the look-up table matches the port where the packet was from, the packet is defined as “local”. Switching Engine The KS8995MA features a high-performance switching engine to move data to and from the MAC’s, packet buffers. It operates in store and forward mode, while the efficient switching mechanism reduces overall latency. The KS8995MA has a 64kB internal frame buffer. This resource is shared between all five ports. The buffer sharing mode can be programmed through Register 2. See “Register 2.” In one mode, ports are allowed to use any free buffers in the buffer pool. In the second mode, each port is only allowed to use 1/5 of the total buffer pool. There are a total of 512 buffers available. Each buffer is sized at 128B. Media Access Controller (MAC) Operation The KS8995MA strictly abides by IEEE 802.3 standards to maximize compatibility. Inter Packet Gap (IPG) If a frame is successfully transmitted, the 96-bit time IPG is measured between the two consecutive MTXEN. If the current packet is experiencing collision, the 96-bit time IPG is measured from MCRS and the next MTXEN. Backoff Algorithm The KS8995MA implements the IEEE Std 802.3 binary exponential back-off algorithm, and optional “aggressive mode” back off. After 16 collisions, the packet will be optionally dropped depending on the chip configuration in Register 3. See “Register 3.”

KS8995MA Micrel, Inc. M9999-051305 26 May 2005 Late Collision If a transmit packet experiences collisions after 512-bit times of the transmission, the packet is dropped. Illegal Frames The KS8995MA discards frames of less than 64 bytes and can be programmed to accept frames up to 1536 bytes in Register 4. For special applications, the KS8995MA can also be programmed to accept frames up to 1916 bytes in Register 4. Since the KS8995MA supports VLAN tags, the maximum size is adjusted when these tags are present. Flow Control The KS8995MA supports standard 802.3x flow control frames on both transmit and receive sides. On the receive side, if the KS8995MA receives a pause control frame, the KS8995MA will not transmit the next normal frame until the timer, specified in the pause control frame, expires. If another pause frame is received before the current timer expires, the timer will be updated with the new value given in the second pause frame. During this period of flow control, only flow controlled packets from the KS8995MA are transmitted. On the transmit side, the KS8995MA has intelligent and efficient ways to determine when to invoke flow control. The flow control is based on availability of the system resources, including available buffers, available transmit queues, and available receive queues. The KS8995MA flow controls a port that has just received a packet if the destination port resource is busy. The KS8995MA issues a flow control frame (XOFF), containing the maximum pause time defined in IEEE standard 802.3x. Once the resource is freed up, the KS8995MA sends out the other flow control frame (XON) with zero pause time to turn off the flow control (turn on transmission to the port). A hysteresis feature is also provided to prevent over-activation and deactivation of the flow control mechanism. The KS8995MA flow controls all ports if the receive queue becomes full. Half-Duplex Back Pressure The KS8995MA also provides a half-duplex back pressure option (note: this is not in IEEE 802.3 standards). The activation and deactivation conditions are the same as the ones given for full-duplex mode. If back pressure is required, the KS8995MA sends preambles to defer the other station's transmission (carrier sense deference). To avoid jabber and excessive deference as defined in IEEE 802.3 standard, after a certain period of time, the KS8995MA discontinues carrier sense but raises it quickly after it drops packets to inhibit other transmissions. This short silent time (no carrier sense) is to prevent other stations from sending out packets and keeps other stations in a carrier sense deferred state. If the port has packets to send during a back pressure situation, the carrier-sense-type back pressure is interrupted and those packets are transmitted instead. If there are no more packets to send, carrier-sense-type back pressure becomes active again until switch resources are free. If a collision occurs, the binary exponential backoff algorithm is skipped and carrier sense is generated immediately, reducing the chance of further colliding and maintaining carrier sense to prevent reception of packets. To ensure no packet loss in 10BASE-T or 100BASE-TX half-duplex modes, the user must enable the following:

• Aggressive backoff (Register 3, bit 0)
• No excessive collision drop (Register 4, bit 3)
• Back pressure (Register 4, bit 5) These bits are not set as the default because this is not the IEEE standard. Broadcast Storm Protection The KS8995MA has an intelligent option to protect the switch system from receiving too many broadcast packets. Broadcast packets are normally forwarded to all ports except the source port and thus use too many switch resources (bandwidth and available space in transmit queues). The KS8995MA has the option to include “multicast packets” for storm control. The broadcast storm rate parameters are programmed globally and can be enabled or disabled on a per port basis. The rate is based on a 50ms interval for 100BT and a 500ms interval for 10BT. At the beginning of each interval, the counter is cleared to zero and the rate limit mechanism starts to count the number of bytes during the interval. The rate definition is described in Registers 6 and 7. The default setting for Registers 6 and 7 is 0x4A (74 decimal). This is equal to a rate of 1%, calculated as follows: 148,800 frames/sec ¥ 50ms/interval ¥ 1% = 74 frames/interval (approx.) = 0x4A MII Interface Operation The media independent interface (MII) is specified by the IEEE 802.3 committee and provides a common interface between physical layer and MAC layer devices. The KS8995MA provides two such interfaces. The MII-P5 interface is used to connect to the fifth PHY, whereas the MII-SW interface is used to connect to the fifth MAC. Each of these MII interfaces contains two distinct groups of signals, one for transmission and the other for receiving. Table 1 describes the signals used in the MII-P5 interface.

Table 2. MII – SW Signals Table 1. MII – P5 Signals (PHY Mode)

a collision has occurred during transmission. configuration. For PHY mode operation, if the device interfacing with the KS8995MA has an MRXER pin, it should be tied low. For MAC mode operation, if the device interfacing with the KS8995MA has an MTXER pin, it should be tied low. for reception. The signals involved are described in Table 3. Table 3. SNI Signals For half-duplex operation, there is a signal that indicates if a collision has occurred during transmission. Port 5 is the designated port for spanning tree support. description shows the port setting and software actions taken for each of the five spanning tree states. Disable state: the port should not forward or receive any packets. Learning is disabled. packets. Note: processor is connected to port 5 via MII interface. Address learning is disabled on the port in this state. Blocking state: only packets to the processor are forwarded. Learning is disabled. the switch will forward those specific packets to the processor. Address learning is disabled on the port in this state. Listening state: only packets to and from the processor are forwarded. Learning is disabled.

Learning state: only packets to and from the processor are forwarded. Learning is enabled. Forwarding state: packets are forwarded and received normally. Learning is enabled. The special tagging mode is designed for spanning tree protocol IGMP snooping and is flexible for use in other applications. special tag. This mode is enabled by setting both Register 11 bit 0 and Register 80 bit 2. Table 4. Special Tagging Mode Format “0011” packet broadcast to port 1 and port 2. “1111” packet broadcast to port 1, 2, 3 and 4. processors do not have a tag, the KS8995MA will treat them as normal packets and an internal look-up will be performed. (blocking, disable, listening, learning). Table 5 shows the egress rules when dealing with STPID.

(0x810+ port mask) 0 0 • Modify tag field to 0x8100.

• Recalculate CRC.
• No change to TCI if not null VID.
• Replace VID with ingress (port 5) port VID if null VID. (0x810+ port mask) 0 1 • (STPID + TCI) will be removed.
• Padding to 64 bytes if necessary.
• Recalculate CRC. (0x810+ port mask) 1 0 • Modify tag field to 0x8100.
• Recalculate CRC.
• No change to TCI if not null VID.
• Replace VID with ingress (port 5) port VID if null VID. (0x810+ port mask) 1 1 • Modify tag field to 0x8100.
• Recalculate CRC.
• No change to TCI if not null VID.
• Replace VID with ingress (port 5) port VID if null VID. Not tagged Don’t care Don’t care Determined by the dynamic MAC address table.

Table 5. STPID Egress Rules (Processor to Switch Port 5) Tagged with 0x8100 + TCI • Modify TPID to 0x810 + “port mask,” which indicates source port.

• No change to TCI, if VID is not null.
• Replace null VID with ingress port VID.
• Recalculate CRC. Not tagged • Insert TPID to 0x810 + “port mask,” which indicates source port.
• Insert TCI with ingress port VID.
• Recalculate CRC.

Table 6. STPID Egress Rules (Switch to Processor) mode” by setting both Register 11 bit 0 and Register 80 bit 2.

1. “Receive Only” mirror on a port. All the packets received on the port will be mirrored on the sniffer port. For example,

1, is destined to port 4 after the internal look-up. The KS8995MA will forward the packet to both port 4 and port 5. KS8995MA can optionally forward even “bad” received packets to port 5.

1. “Transmit Only” mirror on a port. All the packets transmitted on the port will be mirrored on the sniffer port. For
2. “Receive and Transmit” mirror on two ports. All the packets received on port A AND transmitted on port B will be

look-up. The KS8995MA will forward the packet to both port 2 and port 5. per port features can be selected through Register 17. dynamic MAC table bit [54:52]. static MAC table bit [52:48]. dynamic MAC table bit [54:52]. static MAC table bit [52:48]. Table 7. FID+DA Look-Up in the VLAN Mode

No The SA+FID will be learned into the dynamic table. Yes Time stamp will be updated. Table 8. FID+SA Look-Up in the VLAN Mode in Register 18 bit 6 and bit 5. These features can be controlled on a port basis. limiting in a priority or non-priority environment. The rate limit starts from 0Kbps and goes up to the line rate in steps of 32Kbps. limit mechanism starts to count the number of bytes during this interval. limit is programmed lower than 128Kbps and the byte counter is 2K bytes below the limit, the flow control will be triggered. the “one second” interval expires. be programmed through Registers 21–27.

KS8995MA Micrel, Inc. Configuration Interface The KS8995MA can function as a managed switch or unmanaged switch. If no EEPROM or micro-controller exists, the KS8995MA will operate from its default setting. Some default settings are configured via strap in options as indicated in the table below. Pin # Pin Name PU/PD (1) Description(1) 1 MDI-XDIS Ipd Disable auto MDI/MDI-X. PD = (default) = normal operation. PU = disable auto MDI/MDI-X on all ports. 45 MUX1 NC Factory test pins. MUX1 and MUX2 should be left unconnected for normal operation.

46 MUX2 NC

62 PMRXD3 Ipd/O PHY[5] MII receive bit 3. Strap option: PD (default) = enable flow control; PU = disable flow control. 63 PMRXD2 Ipd/O PHY[5] MII receive bit 2. Strap option: PD (default) = disable back pressure; PU = enable back pressure. 64 PMRXD1 Ipd/O PHY[5] MII receive bit 1. Strap option: PD (default) = drop excessive collision packets; PU = does not drop excessive collision packets. 65 PMRXD0 Ipd/O PHY[5] MII receive bit 0. Strap option: PD (default) = disable aggressive back-off algorithm in half-duplex mode; PU = enable for performance enhancement. 66 PMRXER Ipd/O PHY[5] MII receive error. Strap option: PD (default) = 1522/1518 bytes; PU = packet size up to 1536 bytes. 67 PCRS Ipd/O PHY[5] MII carrier sense/force duplex mode. See “Register 76” for port 4 only. PD (default) = force half-duplex if auto-negotiation is disabled or fails. PU = force full-duplex if auto-negotiation is disabled or fails. 68 PCOL Ipd/O PHY[5] MII collision detect/force flow control. See “Register 66” for port 4 only. PD (default) = no force flow control. PU = force flow control. 80 SMRXD3 Ipd/O Switch MII receive bit 3. Strap option: PD (default) = disable switch MII full-duplex flow control; PU = enable switch MII full-duplex flow control. 81 SMRXD2 Ipd/O Switch MII receive bit 2. Strap option: PD (default) = switch MII in full-duplex mode; PU = switch MII in half-duplex mode. 82 SMRXD1 Ipd/O Switch MII receive bit 1. Strap option: PD (default) = switch MII in 100Mbps mode; PU = switch MII in 10Mbps mode.

83 SMRXD0 Ipd/O Switch MII receive bit 0; Strap option: LED mode PD (default) = mode 0;

PU = mode 1. See “Register 11.” Mode 0 Mode 1 LEDX_2 Lnk/Act 100Lnk/Act LEDX_1 Fulld/Col 10Lnk/Act LEDX_0 Speed Fulld Note: 1. NC = No connect. Ipd = Input w/ internal pull-down. Ipd/O = Input w/ internal pull-down during reset, output pin otherwise. Fulld = Full duplex.

KS8995MA Micrel, Inc. M9999-051305 34 May 2005 Pin # Pin Name PU/PD (1) Description1) 86 SCONF1 Ipd Dual MII configuration pin. Pins 91, 86, 87 Switch MII PHY [5] MII 87 SCONF0 Ipd Dual MII configuration pin. 90 LED5-2 Ipu/O LED indicator 2. Strap option: Aging setup. See “Aging” section PU (default) = aging enable; PD = aging disable. 91 LED5-1 Ipu/O LED indicator 1. Strap option: PU (default): enable PHY MII I/F. PD: tristate all PHY MII output. See “Pin 86 SCONF1.” 113 PS1 Ipd Serial bus configuration pin. For this case, if the EEPROM is not present, the KS8995MA will start itself with the PS[1:0] = 00 default register values . Pin Configuration Serial Bus Configuration PS[1:0]=00 I 2C Master Mode for EEPROM PS[1:0]=01 Reserved PS[1:0]=10 SPI Slave Mode for CPU Interface PS[1:0]=11 Factory Test Mode (BIST) 114 PS0 Ipd Serial bus configuration pin. See “Pin 113.” 128 TEST2 NC NC for normal operation. Factory test pin. Note: 1. NC = No connect. Ipd = Input w/ internal pull-down. Ipu/O = Input w/ internal pull-up during reset, output pin otherwise. Otri = Output tristated.

Map,” except the status registers. After reset, the KS8995MA will start to read all 110 registers sequentially from the EEPROM. prgm) is less than 15ms as shown in Figure 7. Figure 7. KS8995MA EEPROM

1. At the board level, connect pin 110 on the KS8995MA to the SCL pin on the EEPROM. Connect pin 111 on the

KS8995MA to the SDA pin on the EEPROM.

1. Set the input signals PS[1:0] (pins 113 and 114, respectively) to “00.” This puts the KS8995MA serial bus

configuration into I2C master mode.

1. Be sure the board-level reset signal is connected to the KS8995MA reset signal on pin 115 (RST_N).
2. Program the contents of the EEPROM before placing it on the board with the desired configuration data. Note that
3. Place EEPROM on the board and power up the board. Assert the active-low board level reset to RST_N on the

KS8995MA. After the reset is de-asserted, the KS8995MA will begin reading configuration data from the EEPROM. Note: For proper operation, make sure that pin 47 (PWRDN_N) is not asserted during the reset operation. switch, write a "1" to Register 1 bit 0. before issuing another command and address. The address counter wraps back to zero once it reaches the highest address. Therefore the entire register set can be written to or read from by issuing a single command and address.

1. At the board level, connect KS8995MA pins as follows:

112 SPIS_N SPI Slave Select

110 SPIC SPI Clock

111 SPID Master Out Slave Input

109 SPIQ Master In Slave Output

Table 9. SPI Connections

1. Set the input signals PS[1:0] (pins 113 and 114, respectively) to “10” to set the serial configuration to SPI slave mode.
2. Power up the board and assert a reset signal. After reset wait 100µs, the start switch bit in Register 1 will be set to
3. Write configuration to registers using a typical SPI write data cycle as shown in Figure 8 or SPI multiple write as shown

in Figure 10. Note that data input on SPID is registered on the rising edge of SPIC.

1. Registers can be read and configuration can be verified with a typical SPI read data cycle as shown in Figure 9 or

a multiple read as shown in Figure 11. Note that read data is registered out of SPIQ on the falling edge of SPIC.

1. After configuration is written and verified, write a ‘1’ to Register 1 bit 0 to begin KS8995MA operation.

KS8995MA Micrel, Inc. Register Description Offset Decimal Hex Description 0-1 0x00-0x01 Chip ID Registers 2-11 0x02-0x0B Global Control Registers 12-15 0x0C-0x0F Reserved 16-29 0x10-0x1D Port 1 Control Registers 30-31 0x1E-0x2F Port 1 Status Registers 32-45 0x20-0x2D Port 2 Control Registers 46-47 0x2E-0x2F Port 2 Status Registers 48-61 0x30-0x3D Port 3 Control Registers 62-63 0x3E-0x3F Port 3 Status Registers 64-77 0x40-0x4D Port 4 Control Registers 78-79 0x4E-0x4F Port 4 Status Registers 80-93 0x50-0x5D Port 5 Control Registers 94-95 0x5E-0x5F Port 5 Status Registers 96-103 0x60-0x67 TOS Priority Control Registers 104-109 0x68-0x6D MAC Address Registers 110-111 0x6E-0x6F Indirect Access Control Registers 112-120 0x70-0x78 Indirect Data Registers 121-122 0x79-0x7A Digital Testing Status Registers 123-124 0x7B-0x7C Digital Testing Control Registers 125-126 0x7D-0x7E Analog Testing Control Registers 127 0x7F Analog Testing Status Register Global Registers Address Name Description Mode Default Register 0 (0x00): Chip ID0 7-0 Family ID Chip family. RO 0x95 Register 1 (0x01): Chip ID1 / Start Switch 7-4 Chip ID 0x0 is assigned to M series. (95MA) RO 0x0

0 Start Switch 1, start the chip when external pins (PS1, PS0) = (1,0) RW —

or (0,1). Note: in (PS1,PS0) = (0,0) mode, the chip will start automatically, after trying to read the external EEPROM. If EEPROM does not exist, the chip will use default values for all internal registers. If EEPROM is present, the contents in the EEPROM will be checked. The switch will check: (1) Register 0 = 0x95, (2) Register 1 [7:4] = 0x0. If this check is OK, the contents in the EEPROM will override chip register default values =0, chip will not start when external pins Note: (PS1, PS0) = (1,1) for factory test only.

KS8995MA Micrel, Inc. M9999-051305 40 May 2005 Address Name Description Mode Default Register 2 (0x02): Global Control 0 7 Reserved Reserved. R/W 0x0 6-4 802.1p Base Priority Used to classify priority for incoming 802.1q packets R/W 0x4 “User priority” is compared against this value ⊕ : classified as high priority. < : classified as low priority. 3 Enable PHY MII 1, enable PHY MII interface. R/W Pin LED[5][1] Note: if not enabled, the switch will tri-state all outputs. strap option. Pull-down (0): isolate. Pull-up (1): Enable. Note: LED[5][1] has internal pull-up. 2 Buffer Share Mode 1, buffer pool is shared by all ports. A port can use R/W 0x1 more buffer when other ports are not busy. 0, a port is only allowed to use 1/5 of the buffer pool.

1 UNH Mode 1, the switch will drop packets with 0x8808 in T/L R/W 0

filed, or DA=01-80-C2-00-00-01. 0, the switch will drop packets qualified as “flow control” packets.

0 Link Change Age 1, link change from “link” to “no link” will cause fast R/W 0

aging (<800µs) to age address table faster. After an age cycle is complete, the age logic will return to normal (300 + 75 seconds ). Note: If any port is unplugged, all addresses will be automatically aged out. Register 3 (0x03): Global Control 1 7 Pass All Frames 1, switch all packets including bad ones. Used solely R/W 0 for debugging purpose. Works in conjunction with sniffer mode. 6 Reserved Reserved. R/W 0 5 IEEE 802.3x Transmit 0, will enable transmit flow control based on AN result. R/W Pin PMRXD3 Flow Control Disable 1, will not enable transmit flow control regardless of strap option. AN result. Pull-down(0): Enable Tx flow control. Pull-up(1): Disable Tx/Rx flow control. Note: PMRXD3 has internal pull- down. 4 IEEE 802.3x Receive 0, will enable receive flow control based on AN result. R/W Pin PMRXD3 strap Flow Control Disable 1, will not enable receive flow control regardless of option. Pull-down AN result. (0): Enable Rx flow control. Pull-up (1): Note: Bit 5 and bit 4 default values are controlled by Disable Tx/Rx flow the same pin, but they can be programmed control. independently. Note: PMRXD3 has internal pull- down.

3 Frame Length Field Check 1, will check frame length field in the IEEE packets R/W 0

If the actual length does not match, the packet will be dropped (for L/T <1500) .

KS8995MA Micrel, Inc. Address Name Description Mode Default 2 Aging Enable 1, Enable age function in the chip. R/W Pin LED[5][2] strap 0, Disable aging function. option. Pull-down (0): Aging disable Pull-up (1): Aging enable. Note: LED[5][2] has internal pull up. 1 Fast age Enable 1 = Turn on fast age (800 µs). R/W 0

0 Aggressive Back 1 = Enable more aggressive back-off algorithm in half R/W Pin PMRXD0 strap

Off Enable duplex mode to enhance performance. This is not an option. Pull-down IEEE standard. (0): Disable aggressive back off. Pull-up (1): Aggressive back off. Note: PMRXD0 has internal pull down. Register 4 (0x04): Global Control 2

7 Unicast Port-VLAN This feature is used for port VLAN R/W 1

Mismatch Discard (described in Register 17, Register 33...). 1, all packets can not cross VLAN boundary. 0, unicast packets (excluding unknown/ multicast/broadcast) can cross VLAN boundary.

6 Multicast Storm 1, “Broadcast Storm Protection” does not include R/W 1

Protection Disable multicast packets. Only DA=FFFFFFFFFFFF packets will be regulated. 0, “Broadcast Storm Protection” includes DA = FFFFFFFFFFFF and DA[40] = 1 packets. 5 Back Pressure Mode 1, carrier sense based backpressure is selected. R/W 1 0, collision based backpressure is selected. 4 Flow Control and Back 1, fair mode is selected. In this mode, if a flow control R/W 1 Pressure Fair Mode port and a non-flow control port talk to the same destination port, packets from the non-flow control port may be dropped. This is to prevent the flow control port from being flow controlled for an extended period of time. 0, in this mode, if a flow control port and a non-flow control port talk to the same destination port, the flow control port will be flow controlled. This may not be “fair” to the flow control port.

3 No Excessive Collision Drop 1, the switch will not drop packets when 16 or more R/W Pin PMRXD1 strap

collisions occur. option. Pull-down 0, the switch will drop packets when 16 or more (0): Drop collisions occur. excessive collision packets. Pull-up (1): Don’t drop excessive collision packets. Note: PMRXD1 has internal pull down. 2 Huge Packet Support 1, will accept packet sizes up to 1916 bytes (inclusive). R/W 0 This bit setting will override setting from bit 1 of the same register. 0, the max packet size will be determined by bit 1 of this register.

KS8995MA Micrel, Inc. M9999-051305 42 May 2005 Address Name Description Mode Default 1 Legal Maximum Packet 1, will accept packet sizes up to 1536 bytes (inclusive). R/W Pin PMRXER Size Check Disable 0, 1522 bytes for tagged packets (not including packets strap option. with STPID from CPU to ports 1-4), 1518 bytes for Pull-down (0): untagged packets. Any packets larger than the specified 1518/1522 byte value will be dropped. packets. Pull-up (1): 1536 byte packets. Note: PMRXER has internal pull- down.

0 Priority Buffer Reserve 1, each output queue is pre-allocated 48 buffers, R/W 0

used exclusively for high priority packets. It is recommended to enable this when priority queue feature is turned on. 0, no reserved buffers for high priority packets. Register 5 (0x05): Global Control 3 7 802.1q VLAN Enable 1, 802.1q VLAN mode is turned on. VLAN table needs R/W 0 to set up before the operation. 0, 802.1q VLAN is disabled. 6 IGMP Snoop Enable on 1, IGMP snoop enabled. All the IGMP packets will be R/W 0 Switch MII Interface forwarded to Switch MII port. 0, IGMP snoop disabled. 5 Enable Direct Mode on 1, direct mode on port 5. This is a special mode for the R/W 0 Switch MII Interface Switch MII interface. Using preamble before MRXDV to direct switch to forward packets, bypassing internal look-up. 0, normal operation.

4 Enable Pre-Tag on 1, packets forwarded to Switch MII interface will be R/W 0

Switch MII Interface pre-tagged with the source port number (preamble before MRXDV). 0, normal operation. 3-2 Priority Scheme Select 00 = always deliver high priority packets first. R/W 00 01 = deliver high/low packets at ratio 10/1. 10 = deliver high/low packets at ratio 5/1. 11 = deliver high/low packets at ratio 2/1.

1 Enable “Tag” Mask 1, the last 5 digits in the VID field are used as a mask R/W 0

to determine which port(s) the packet should be forwarded to. 0, no tag masks.

0 Sniff Mode Select 1, will do Rx AND Tx sniff (both source port and R/W 0

destination port need to match). 0, will do Rx OR Tx sniff (Either source port or destination port needs to match). This is the mode used to implement Rx only sniff. Register 6 (0x06): Global Control 4

7 Switch MII Back 1, enable half-duplex back pressure on switch MII R/W 0

Pressure Enable interface. 0, disable back pressure on switch MII interface. 6 Switch MII Half-Duplex 1, enable MII interface half-duplex mode. R/W Pin SMRXD2 strap Mode 0, enable MII interface full-duplex mode. option. Pull-down (0): Full-duplex mode. Pull-up (1): Half-duplex mode. Note: SMRXD2 has internal pull-down.

KS8995MA Micrel, Inc. Address Name Description Mode Default (1) 5 Switch MII Flow 1, enable full-duplex flow control on switch MII interface. R/W Pin SMRXD3 strap Control Enable 0, disable full-duplex flow control on switch MII interface. option. Pull-down (0): disable flow control. Pull-up(1): enable flow control. Note: SMRXD3 has internal pull- down. 4 Switch MII 10BT 1, the switch interface is in 10Mbps mode. R/W Pin SMRXD1 strap 0, the switch interface is in 100Mbps mode. option. Pull-down (0): Enable 100Mbps. Pull-up (1): Enable 10Mpbs. Note: SMRXD1 has internal pull- down. 3 Null VID Replacement 1, will replace null VID with port VID (12 bits). R/W 0 0, no replacement for null VID. 2-0 Broadcast Storm This along with the next register determines how many R/W 000 Protection Rate Bit [10:8] “64 byte blocks” of packet data allowed on an input port in a preset period. The period is 50ms for 100BT or 500ms for 10BT. The default is 1%. Register 7 (0x07): Global Control 5 7-0 Broadcast Storm This along with the previous register determines how R/W 0x4A (1) Protection Rate Bit [7:0] many “64 byte blocks” of packet data are allowed on an input port in a preset period. The period is 50ms for 100BT or 500ms for 10BT. The default is 1%. Note: 1. 148,800 frames/sec × 50ms/interval × 1% = 74 frames/interval (approximately) = 0x4A. Register 8 (0x08): Global Control 6 7-0 Factory Testing Reserved. R/W 0x24 Register 9 (0x09): Global Control 7 7-0 Factory Testing Reserved. R/W 0x28 Register 10 (0x0A): Global Control 8 7-0 Factory Testing Reserved. R/W 0x24 Register 11 (0x0B): Global Control 9 7-4 Reserved N/A 0 3 PHY Power 0 = disable PHY power save mode. R/W 0 Save 1 = enable PHY power save mode. 2 Factory Setting Reserved. R/W 0 1 LED Mode 0 = led mode 0. R/W Pin SMRXD0 strap 1 = led mode 1. option. Pull-down(0): Enabled led mode 0. Pull-up(1): Enabled led mode 1. Note: SMRXD0 has internal pull-down 0. Mode 0 Mode 1 LEDX_2 Lnk/Act 100Lnk/Act LEDX_1 Fulld/Col 10Lnk/Act LEDX_0 Speed Fulld 0 Special TPID Mode Used for direct mode forwarding from port 5. R/W 0 See “Spanning Tree” functional description.

KS8995MA Micrel, Inc. M9999-051305 44 May 2005 Port Registers The following registers are used to enable features that are assigned on a per port basis. The register bit assignments are the same for all ports, but the address for each port is different, as indicated. Register 16 (0x10): Port 1 Control 0 Register 32 (0x20): Port 2 Control 0 Register 48 (0x30): Port 3 Control 0 Register 64 (0x40): Port 4 Control 0 Register 80 (0x50): Port 5 Control 0 Address Name Description Mode Default

7 Broadcast Storm 1, enable broadcast storm protection for ingress packets R/W 0

Protection Enable on the port. 0, disable broadcast storm protection.

6 DiffServ Priority 1, enable DiffServ priority classification for ingress R/W 0

Classification Enable packets on port. 0, disable DiffServ function. 5 802.1p Priority 1, enable 802.1p priority classification for ingress R/W 0 Classification Enable packets on port. 0, disable 802.1p.

4 Port-Based Priority 1, ingress packets on the port will be classified as high R/W 0

Classification Enable priority if “DiffServ” or “802.1p” classification is not enabled or fails to classify. 0, ingress packets on port will be classified as low priority if “DiffServ” or “802.1p” classification is not enabled or fails to classify. Note: “DiffServ”, “802.1p” and port priority can be enabled at the same time. The OR’ed result of 802.1p and DSCP overwrites the port priority. 3 Reserved Reserved. R/W 0

2 Tag Insertion 1, when packets are output on the port, the switch will R/W 0

add 802.1q tags to packets without 802.1q tags when received. The switch will not add tags to packets already tagged. The tag inserted is the ingress port’s “port VID.” 0, disable tag insertion.

1 Tag Removal 1, when packets are output on the port, the switch will R/W 0

remove 802.1q tags from packets with 802.1q tags when received. The switch will not modify packets received without tags. 0, disable tag removal.

0 Priority Enable 1, the port output queue is split into high and low R/W 0

priority queues. 0, single output queue on the port. There is no priority differentiation even though packets are classified into high or low priority. Register 17 (0x11): Port 1 Control 1 Register 33 (0x21): Port 2 Control 1 Register 49 (0x31): Port 3 Control 1 Register 65 (0x41): Port 4 Control 1 Register 81 (0x51): Port 5 Control 1 Address Name Description Mode Default

7 Sniffer Port 1, port is designated as sniffer port and will transmit R/W 0

packets that are monitored. 0, Port is a normal port.

6 Receive Sniff 1, all the packets received on the port will be marked R/W 0

as “monitored packets” and forwarded to the designated “sniffer port.” 0, no receive monitoring.

KS8995MA Micrel, Inc. Address Name Description Mode Default

5 Transmit Sniff 1, All the packets transmitted on the port will be marked R/W 0

as “monitored packets” and forwarded to the designated “sniffer port.” 0, no transmit monitoring. 4-0 Port VLAN Membership Define the port’s “Port VLAN membership.” Bit 4 stands R/W 0x1f for port 5, bit 3 for port 4...bit 0 for port 1. The port can only communicate within the membership. A ‘1’ includes a port in the membership, a ‘0’ excludes a port from membership. Register 18 (0x12): Port 1 Control 2 Register 34 (0x22): Port 2 Control 2 Register 50 (0x32): Port 3 Control 2 Register 66 (0x42): Port 4 Control 2 Register 82 (0x52): Port 5 Control 2 Address Name Description Mode Default 7 Reserved Reserved. 0x0 6 Ingress VLAN Filtering. 1, the switch will discard packets whose VID port R/W 0 membership in VLAN table bit[20:16] does not include the ingress port. 0, no ingress VLAN filtering. 5 Discard Non-PVID Packets. 1, the switch will discard packets whose VID does not R/W 0 match ingress port default VID. 0, no packets will be discarded.

4 Force Flow Control 1, will always enable Rx and Tx flow control on the port, R/W 0

regardless of AN result. For port 4 only, 0, the flow control is enabled based on AN result. there is a special Note: Setting a port for both half-duplex and forced configuration pin flow control is an illegal configuration. For half-duplex to set the default, enable back pressure. Pin PCOL strap option. Pull-down (0): No Force flow control. Pull-up (1): Force flow control. Note: PCOL has internal pull-down. 3 Back Pressure Enable 1, enable port’s half-duplex back pressure. R/W Pin PMRXD2 strap 0, disable port’s half-duplex back pressure. option. Pull-down (0): disable back pressure. Pull-up (1): enable back pressure. Note: PMRXD2 has internal pull-down. 2 Transmit Enable 1, enable packet transmission on the port. R/W 1 0, disable packet transmission on the port. 1 Receive Enable 1, enable packet reception on the port. R/W 1 0, disable packet reception on the port. 0 Learning Disable 1, disable switch address learning capability. R/W 0 0, enable switch address learning. Note: Bits 2-0 are used for spanning tree support. See “Spanning Tree Support” section.

KS8995MA Micrel, Inc. M9999-051305 46 May 2005 Register 19 (0x13): Port 1 Control 3 Register 35 (0x23): Port 2 Control 3 Register 51 (0x33): Port 3 Control 3 Register 67 (0x43): Port 4 Control 3 Register 83 (0x53): Port 5 Control 3 Address Name Description Mode Default 7-0 Default Tag [15:8] Port’s default tag, containing: R/W 0 7-5: user priority bits 4: CFI bit 3-0 : VID[11:8] Register 20 (0x14): Port 1 Control 4 Register 36 (0x24): Port 2 Control 4 Register 52 (0x34): Port 3 Control 4 Register 68 (0x44): Port 4 Control 4 Register 84 (0x54): Port 5 Control 4 Address Name Description Mode Default 7-0 Default Tag [7:0] Default port 1’s tag, containing: R/W 1 7-0: VID[7:0] Note: Registers 19 and 20 (and those corresponding to other ports) serve two purposes: (1) associated with the ingress untagged packets, and used for egress tagging; (2) default VID for the ingress untagged or null-VID-tagged packets, and used for address look-up. Register 21 (0x15): Port 1 Control 5 Register 37 (0x25): Port 2 Control 5 Register 53 (0x35): Port 3 Control 5 Register 69 (0x45): Port 4 Control 5 Register 85 (0x55): Port 5 Control 5 Address Name Description Mode Default 7-0 Transmit High Priority This along with port control 7, bits [3:0] form a 12-bit R/W 0 Rate Control [7:0] field to determine how many “32Kbps” high priority blocks can be transmitted (in a unit of 4K bytes in a one second period). Register 22 (0x16): Port 1 Control 6 Register 38 (0x26): Port 2 Control 6 Register 54 (0x36): Port 3 Control 6 Register 70 (0x46): Port 4 Control 6 Register 86 (0x56): Port 5 Control 6 Address Name Description Mode Default 7-0 Transmit Low Priority This along with port control 7, bits [7:4] form a 12-bit R/W 0 Rate Control [7:0] field to determine how many “32Kbps” low priority blocks can be transmitted (in a unit of 4K bytes in a one second period). Register 23 (0x17): Port 1 Control 7 Register 39 (0x27): Port 2 Control 7 Register 55 (0x37): Port 3 Control 7 Register 71 (0x47): Port 4 Control 7 Register 87 (0x57): Port 5 Control 7 Address Name Description Mode Default 7-4 Transmit Low Priority This along with port control 6, bits [7:0] form a 12-bit R/W 0 Rate Control [11:8] field to determine how many “32Kbps” low priority blocks can be transmitted (in a unit of 4K bytes in a one second period). 3-0 Transmit High Priority This along with port control 5, bits [7:0] form a 12-bit R/W 0 Rate Control [11:8] field to determine how many “32Kbps” high priority blocks can be transmitted (in unit of 4K bytes in a one second period).

KS8995MA Micrel, Inc. Register 24 (0x18): Port 1 Control 8 Register 40 (0x28): Port 2 Control 8 Register 56 (0x38): Port 3 Control 8 Register 72 (0x48): Port 4 Control 8 Register 88 (0x58): Port 5 Control 8 Address Name Description Mode Default 7-0 Receive High Priority This along with port control 10, bits [3:0] form a 12-bit R/W 0 Rate Control [7:0] field to determine how many “32Kbps” high priority blocks can be received (in a unit of 4K bytes in a one second period). Register 25 (0x19): Port 1 Control 9 Register 41 (0x29): Port 2 Control 9 Register 57 (0x39): Port 3 Control 9 Register 73 (0x49): Port 4 Control 9 Register 89 (0x59): Port 5 Control 9 Address Name Description Mode Default 7-0 Receive Low Priority This along with port control 10, bits [7:4] form a 12-bit R/W 0 Rate Control [7:0] field to determine how many “32Kbps” low priority blocks can be received (in a unit of 4K bytes in a one second period). Register 26 (0x1A): Port 1 Control 10 Register 42 (0x2A): Port 2 Control 10 Register 58 (0x3A): Port 3 Control 10 Register 74 (0x4A): Port 4 Control 10 Register 90 (0x5A): Port 5 Control 10 Address Name Description Mode Default 7-4 Receive Low Priority This along with port control 9, bits [7:0] form a 12-bit R/W 0 Rate Control [11:8] field to determine how many “32Kbps” low priority blocks can be received (in a unit of 4K bytes in a one second period). 3-0 Receive High Priority This along with port control 8, bits [7:0] form a 12-bit R/W 0 Rate Control [11:8] field to determine how many “32Kbps” high priority blocks can be received (in a unit of 4K bytes in a one second period). Register 27 (0x1B): Port 1 Control 11 Register 43 (0x2B): Port 2 Control 11 Register 59 (0x3B): Port 3 Control 11 Register 75 (0x4B): Port 4 Control 11 Register 91 (0x5B): Port 5 Control 11 Address Name Description Mode Default

7 Receive Differential 1, If bit 6 is also ‘1’ this will enable receive rate control R/W 0

Priority Rate Control for this port on low priority packets at the low priority rate. If bit 5 is also ‘1’, this will enable receive rate control on high priority packets at the high priority rate. 0, receive rate control will be based on the low priority rate for all packets on this port. 6 Low Priority Receive 1, enable port’s low priority receive rate control feature. R/W 0 Rate Control Enable 0, disable port’s low priority receive rate control.

5 High Priority Receive 1, If bit 7 is also ‘1’ this will enable the port’s high R/W 0

Rate Control Enable priority receive rate control feature. If bit 7 is a ‘0’ and bit 6 is a ‘1’, all receive packets on this port will be rate controlled at the low priority rate. 0, disable port’s high priority receive rate control feature.

4 Low Priority Receive Rate 1, flow control may be asserted if the port’s low priority R/W 0

Flow Control Enable receive rate is exceeded. 0, flow control is not asserted if the port’s low priority receive rate is exceeded.

KS8995MA Micrel, Inc. M9999-051305 48 May 2005 Address Name Description Mode Default

3 High Priority Receive 1, flow control may be asserted if the port’s high R/W 0

Rate Flow Control Enable priority receive rate is exceeded (to use this, differential receive rate control must be on). 0, flow control is not asserted if the port’s high priority receive rate is exceeded.

2 Transmit Differential 1, will do transmit rate control on both high and low R/W 0

Priority Rate Control priority packets based on the rate counters defined by the high and low priority packets respectively. 0, will do transmit rate control on any packets. The rate counters defined in low priority will be used.

1 Low Priority Transmit 1, enable the port’s low priority transmit rate control R/W 0

Rate Control Enable feature. 0, disable the port’s low priority transmit rate control feature.

0 High Priority Transmit 1, enable the port’s high priority transmit rate control R/W 0

Rate Control Enable feature 0, disable the port’s high priority transmit rate control feature. Register 28 (0x1C): Port 1 Control 12 Register 44 (0x2C): Port 2 Control 12 Register 60 (0x3C): Port 3 Control 12 Register 76 (0x4C): Port 4 Control 12 Register 92 (0x5C): Port 5 Control 12 Address Name Description Mode Default

7 Disable Auto-Negotiation 1, disable auto-negotiation, speed and duplex are R/W 0

decided by bit 6 and 5 of the same register. 0, auto-negotiation is on. 6 Forced Speed 1, forced 100BT if AN is disabled (bit 7). R/W 1 0, forced 10BT if AN is disabled (bit 7).

5 Forced Duplex 1, forced full-duplex if (1) AN is disabled or (2) AN is R/W 0

enabled but failed. For port 4 only, 0, forced half-duplex if (1) AN is disabled or (2) AN is there is a special enabled but failed. configure pin to set the default, Pin PCRS strap option. Pull-down (0): Force half-duplex. Pull-up (1): Force full-duplex. Note: PCRS has internal pull down. 4 Advertised Flow 1, advertise flow control capability. R/W 1 Control Capability 0, suppress flow control capability from transmission to link partner. 3 Advertised 100BT 1, advertise 100BT full-duplex capability. R/W 1 Full-Duplex Capability 0, suppress 100BT full-duplex capability from transmission to link partner. 2 Advertised 100BT 1, advertise 100BT half-duplex capability. R/W 1 Half-Duplex Capability 0, suppress 100BT half-duplex capability from transmission to link partner. 1 Advertised 10BT 1, advertise 10BT full-duplex capability. R/W 0 Full-Duplex Capability 0, suppress 10BT full-duplex capability from transmission to link partner.

KS8995MA Micrel, Inc. Address Name Description Mode Default 0 Advertised 10BT 1, advertise 10BT half-duplex capability. R/W 1 Half-Duplex Capability 0, suppress 10BT half-duplex capability from transmission to link partner. Note: Port Control 12 and 13, and Port Status 0 contents can be accessed by MIIM (MDC/MDIO) interface via the standard MIIM register definition. Register 29 (0x1D): Port 1 Control 13 Register 45 (0x2D): Port 2 Control 13 Register 61 (0x3D): Port 3 Control 13 Register 77 (0x4D): Port 4 Control 13 Register 93 (0x5D): Port 5 Control 13 Address Name Description Mode Default

7 LED Off 1, Turn off all port’s LEDs (LEDx_2, LEDx_1, LEDx_0, R/W 0

where “x” is the port number). These pins will be driven high if this bit is set to one. 0, normal operation. 6 Txids 1, disable port’s transmitter. R/W 0 0, normal operation. 5 Restart AN 1, restart auto-negotiation. R/W 0 0, normal operation. 4 Disable Far End Fault 1, disable far end fault detection and pattern transmission. R/W 0 0, enable far end fault detection and pattern transmission. 3 Power Down 1, power down. R/W 0 0, normal operation. 2 Disable Auto MDI/MDI-X 1, disable auto MDI/MDI-X function. R/W 0 0, enable auto MDI/MDI-X function.

1 Forced MDI 1, If auto MDI/MDI-X is disabled, force PHY into R/W 0

MDI mode. 0, Do not force PHY into MDI mode. 0 MAC Loopback 1, Perform MAC loopback. R/W 0 0, normal operation. Register 30 (0x1E): Port 1 Status 0 Register 46 (0x2E): Port 2 Status 0 Register 62 (0x3E): Port 3 Status 0 Register 78 (0x4E): Port 4 Status 0 Register 94 (0x5E): Port 5 Status 0 Address Name Description Mode Default 7 MDI-X Status 1, MDI. RO 0 0, MDI-X. 6 AN Done 1, AN done. RO 0 0, AN not done. 5 Link Good 1, link good. RO 0 0, link not good. 4 Partner Flow 1, link partner flow control capable. RO 0 Control Capability 0, link partner not flow control capable. 3 Partner 100BT 1, link partner 100BT full-duplex capable. RO 0 Full-Duplex Capability 0, link partner not 100BT full-duplex capable. 2 Partner 100BT 1, link partner 100BT half-duplex capable. RO 0 Half-Duplex Capability 0, link partner not 100BT half-duplex capable. 1 Partner 10BT 1, link partner 10BT full-duplex capable. RO 0 Full-Duplex Capability 0, link partner not 10BT full-duplex capable. 0 Partner 10BT 1, link partner 10BT half-duplex capable. RO 0 Half-Duplex Capability 0, link partner not 10BT half-duplex capable.

KS8995MA Micrel, Inc. M9999-051305 50 May 2005 Register 31 (0x1F): Port 1 Control 14 Register 47 (0x2F): Port 2 Control 14 Register 63 (0x3F): Port 3 Control 14 Register 79 (0x4F): Port 4 Control 14 Register 95 (0x5F): Port 5 Control 14 Address Name Description Mode Default 7 PHY Loopback 1, perform PHY loopback, i.e. loopback MAC’s Tx R/W 0 back to Rx. 0, normal operation. 6 Remote Loopback 1, perform remote loopback, i.e. loopback PHY’s Rx R/W 0 back to Tx. 0, normal operation. 5 PHY Isolate 1, electrical isolation of PHY from MII and Tx+/Tx-. R/W 0 0, normal operation. 4 Soft Reset 1, PHY soft reset. R/W 0 0, normal operation. 3 Force Link 1, Force link in the PHY. R/W 0 0, normal operation. 2-1 Reserved N/A RO 0 0 Far End Fault 1, Far end fault status detected. RO 0 0, no far end fault status detected. Advanced Control Registers The IPv4 TOS priority control registers implement a fully decoded 64 bit differentiated services code point (DSCP) register used to determine priority from the 6 bit TOS field in the IP header. The most significant 6 bits of the TOS field are fully decoded into 64 possibilities, and the singular code that results is compared against the corresponding bit in the DSCP register. If the register bit is a 1, the priority is high; if the register bit is a 0, the priority is low. Address Name Description Mode Default Register 96 (0x60): TOS Priority Control Register 0 7-0 DSCP[63:56] R/W 00000000 Register 97 (0x61): TOS Priority Control Register 1 7-0 DSCP[55:48] R/W 00000000 Register 98 (0x62): TOS Priority Control Register 2 7-0 DSCP[47:40] R/W 00000000 Register 99 (0x63): TOS Priority Control Register 3 7-0 DSCP[39:32] R/W 00000000 Register 100 (0x64): TOS Priority Control Register 4 7-0 DSCP[31:24] R/W 00000000 Register 101 (0x65): TOS Priority Control Register 5 7-0 DSCP[23:16] R/W 00000000 Register 102 (0x66): TOS Priority Control Register 6 7-0 DSCP[15:8] R/W 00000000 Register 103 (0x67): TOS Priority Control Register 7 7-0 DSCP[7:0] R/W 00000000 Registers 104 to 109 define the switching engine’s MAC address. This 48-bit address is used as the source address in MAC pause control frames. Register 104 (0x68): MAC Address Register 0 7-0 MACA[47:40] R/W 0x00 Register 105 (0x69): MAC Address Register 1 7-0 MACA[39:32] R/W 0x10

KS8995MA Micrel, Inc. Address Name Description Mode Default Register 106 (0x6A): MAC Address Register 2 7-0 MACA[31:24] R/W 0x A1 Register 107 (0x6B): MAC Address Register 3 7-0 MACA[23:16] R/W 0xff Register 108 (0x6C): MAC Address Register 4 7-0 MACA[15:8] R/W 0xff Register 109 (0X6D): MAC Address Register 5 7-0 MACA[7:0] R/W 0xff Use registers 110 and 111 to read or write data to the static MAC address table, VLAN table, dynamic address table, or the MIB counters. Address Name Description Mode Default Register 110 (0x6E): Indirect Access Control 0 7-5 Reserved Reserved. R/W 000 4 Read High Write Low 1, read cycle. R/W 0 0, write cycle. 3-2 Table Select 00 = static mac address table selected. R/W 0 01 = VLAN table selected. 10 = dynamic address table selected. 11 = MIB counter selected. 1-0 Indirect Address High Bit 9-8 of indirect address. R/W 00 Register 111 (0x6F): Indirect Access Control 1 7-0 Indirect Address Low Bit 7-0 of indirect address. R/W 00000000 Note: Write to Register 111 will actually trigger a command. Read or write access will be decided by bit 4 of Register 110. Address Name Description Mode Default Register 112 (0x70): Indirect Data Register 8 68-64 Indirect Data Bit 68-64 of indirect data. R/W 00000 Register 113 (0x71): Indirect Data Register 7 63-56 Indirect Data Bit 63-56 of indirect data. R/W 00000000 Register 114 (0x72): Indirect Data Register 6 55-48 Indirect Data Bit 55-48 of indirect data. R/W 00000000 Register 115 (0x73): Indirect Data Register 5 47-40 Indirect Data Bit 47-40 of indirect data. R/W 00000000 Register 116 (0x74): Indirect Data Register 4 39-32 Indirect Data Bit 39-32 of indirect data. R/W 00000000 Register 117 (0x75): Indirect Data Register 3 31-24 Indirect Data Bit of 31-24 of indirect data R/W 00000000 Register 118 (0x76): Indirect Data Register 2 23-16 Indirect Data Bit 23-16 of indirect data. R/W 00000000 Register 119 (0x77): Indirect Data Register 1 15-8 Indirect Data Bit 15-8 of indirect data. R/W 00000000 Register 120 (0x78): Indirect Data Register 0 7-0 Indirect Data Bit 7-0 of indirect data. R/W 00000000 Do not write or read to/from Register isters 121 to 127. Doing so may prevent proper operation. Micrel internal testing only.

KS8995MA Micrel, Inc. M9999-051305 52 May 2005 Address Name Description Mode Default Register 121 (0x79): Digital Testing Status 0 7-0 Factory Testing Reserved. RO 0x0 Qm_split status Register 122 (0x7A): Digital Testing Status 1 7-0 Factory Testing Reserved. RO 0x0 Dbg[7:0] Register 123 (0x7B): Digital Testing Control 0 7-0 Factory Testing Reserved. R/W 0x0 Dbg[12:8] Register 124 (0x7C): Digital Testing Control 1 7-0 Factory Testing Reserved. R/W 0x0 Register 125 (0x7D): Analog Testing Control 0 7-0 Factory Testing Reserved. R/W 0x0 Register 126 (0x7E): Analog Testing Control 1 7-0 Factory Testing Reserved. R/W 0x0 Register 127 (0x7F): Analog Testing Status 7-0 Factory Testing Reserved. RO 0x0

device does all addition, modification and deletion. Register bit assignments are different for static MAC table reads and static MAC table write, as shown in the two tables below. 0, use MAC only to look-up in static table.

54 Override 1, override spanning tree “transmit enable = 0” or RO 0

spanning tree implementation. 55 Use FID 1, use (FID+MAC) to look-up in static table.

54 Override 1, override spanning tree “transmit enable = 0” or W 0

spanning tree implementation. Table 12. Static MAC Address Table

KS8995MA Micrel, Inc. M9999-051305 54 May 2005 Examples: (1) Static Address Table Read (read the 2nd entry) Write to Register 110 with 0x10 (read static table selected) Write to Register 111 with 0x1 (trigger the read operation) Then Read Register 113 (60-56) Read Register 114 (55-48) Read Register 115 (47-40) Read Register 116 (39-32) Read Register 117 (31-24) Read Register 118 (23-16) Read Register 119 (15-8) Read Register 120 (7-0) (2) Static Address Table Write (write the 8th entry) Write Register 113 (59-56) Write Register 114 (55-48) Write Register 115 (47-40) Write Register 116 (39-32) Write Register 117 (31-24) Write Register 118 (23-16) Write Register 119 (15-8) Write Register 120 (7-0) Write to Register 110 with 0x00 (write static table selected) Write to Register 111 with 0x7 (trigger the write operation)

will be forwarded to ports specified in this field. E.g., 11001 means port 5, 4, and 1 are in this VLAN. Table 13. VLAN Table ingress port) of the VLAN. If FID+SA fails, the FID+SA is learned.

0, there are valid entries in the table. Table 14. Dynamic MAC Address Table This table is read only. The contents are maintained by the KS8995MA only.

0x0 RxLoPriorityByte Rx lo-priority (default) octet count including bad packets. 0x1 RxHiPriorityByte Rx hi-priority octet count including bad packets. 0x2 RxUndersizePkt Rx undersize packets w/good CRC. 0x3 RxFragments Rx fragment packets w/bad CRC, symbol errors or alignment errors. 0x4 RxOversize Rx oversize packets w/good CRC (max: 1536 or 1522 bytes). (depends on max packet size setting). 0x6 RxSymbolError Rx packets w/ invalid data symbol and legal packet size. (upper limit depends on max packet size setting). (upper limit depends on max packet size setting). 0x9 RxControl8808Pkts The number of MAC control frames received by a port with 88-08h in EtherType field. EtherType (88-08h), DA, control opcode (00-01), data length (64B min), and a valid CRC. 0xD RxUnicast Rx good unicast packets. 0xE Rx64Octets Total Rx packets (bad packets included) that were 64 octets in length. 0xF Rx65to127Octets Total Rx packets (bad packets included) that are between 65 and 127 octets in length. 0x10 Rx128to255Octets Total Rx packets (bad packets included) that are between 128 and 255 octets in length. 0x11 Rx256to511Octets Total Rx packets (bad packets included) that are between 256 and 511 octets in length. 0x12 Rx512to1023Octets Total Rx packets (bad packets included) that are between 512 and 1023 octets in length. (upper limit depends on max packet size setting). 0x14 TxLoPriorityByte Tx lo-priority good octet count, including PAUSE packets. 0x15 TxHiPriorityByte Tx hi-priority good octet count, including PAUSE packets. 0x16 TxLateCollision The number of times a collision is detected later than 512 bit-times into the Tx of a packet. 0x17 TxPausePkts The number of PAUSE frames transmitted by a port. 0x18 TxBroadcastPkts Tx good broadcast packets (not including errored broadcast or valid multicast packets). 0x1A TxUnicastPkts Tx good unicast packets. 0x1B TxDeferred Tx packets by a port for which the 1st Tx attempt is delayed due to the busy medium. 0x1C TxTotalCollision Tx total collision, half-duplex only. 0x1D TxExcessiveCollision A count of frames for which Tx fails due to excessive collisions. 0x1E TxSingleCollision Successfully Tx frames on a port for which Tx is inhibited by exactly one collision. 0x1F TxMultipleCollision Successfully Tx frames on a port for which Tx is inhibited by more than one collision. Table 15. Port-1 MIB Counter Indirect Memory Offsets

0, Counter value is not valid. 0x100 Port1 Tx Drop Packets Tx packets dropped due to lack of resources. 0x101 Port2 Tx Drop Packets Tx packets dropped due to lack of resources. 0x102 Port3 Tx Drop Packets Tx packets dropped due to lack of resources. 0x103 Port4 Tx Drop Packets Tx packets dropped due to lack of resources. 0x104 Port5 Tx Drop Packets Tx packets dropped due to lack of resources. 0x105 Port1 Rx Drop Packets Rx packets dropped due to lack of resources. 0x106 Port2 Rx Drop Packets Rx packets dropped due to lack of resources. 0x107 Port3 Rx Drop Packets Rx packets dropped due to lack of resources. 0x108 Port4 Rx Drop Packets Rx packets dropped due to lack of resources. 0x109 Port5 Rx Drop Packets Rx packets dropped due to lack of resources. Table 16. All Port Dropped Packet MIB Counters All port dropped packet MIB counters do not indicate overflow or validity; therefore the application must keep track of overflow and valid conditions.

KS8995MA Micrel, Inc. (2) MIB counter read (read port 2 rx 64 counter) Write to Register 110 with 0x1c (read MIB counter selected) Write to Register 111 with 0x2e (trigger the read operation ) Then Read Register 117 (counter value 31-24) // If bit 31 = 1, there was a counter overflow // If bit 30 = 0, restart (reread) from this register Read Register 118 (counter value 23-16) Read Register 119 (counter value 15-8) Read Register 120 (counter value 7-0) (3) MIB counter read (read port 1 tx drop packets) Write to Register 110 with 0x1d Write to Register 111 with 0x00 Then Read Register 119 (counter value 15-8) Read Register 120 (counter value 7-0) Note: To read out all the counters, the best performance over the SPI bus is (160+3)× 8 × 200 = 260ms, where there are 160 registers, 3 overhead, 8 clocks per access, at 5MHz. In the heaviest condition, the byte counter will overflow in 2 minutes. It is recommended that the software read all the counters at least every 30 seconds. The per port MIB counters are designed as “read clear.” A per port MIB counter will be cleared after it is accessed. All port dropped packet MIB counters are not cleared after they are accessed. The application needs to keep track of overflow and valid conditions on these counters.

KS8995MA Micrel, Inc. M9999-051305 60 May 2005 Address Name Description Mode Default Register 0: MII Control 15 Soft Reset 1, PHY soft reset. R/W 0 0, Normal operation. 14 Loop Back 1, Loop back mode (loopback at MAC). R/W 0 0, Normal operation. 13 Force 100 1, 100Mbps. R/W 1 0, 10Mbps. 12 AN Enable 1, Auto-negotiation enabled. R/W 1 0, Auto-negotiation disabled. 11 Power Down 1, Power down. R/W 0 0, Normal operation. 10 PHY Isolate 1, Electrical PHY isolation of PHY from Tx+/Tx-. R/W 0 0, Normal operation. 9 Restart AN 1, Restart Auto-negotiation. R/W 0 0, Normal operation. 8 Force Full Duplex 1, Full duplex. R/W 0 0, Half duplex. 7 Collision Test Not supported. RO 0

6 Reserved RO 0

5 Reserved RO 0

4 Force MDI 1, Force MDI. R/W 0 0, Normal operation. 3 Disable Auto MDI/MDI-X 1, Disable auto MDI/MDI-X. R/W 0 0, Normal operation. 2 Disable Far End Fault 1, Disable far end fault detection. R/W 0 0, Normal operation. 1 Disable Transmit 1, Disable transmit. R/W 0 0, Normal operation. 0 Disable LED 1, Disable LED. R/W 0 0, Normal operation. MIIM Registers All the registers defined in this section can be also accessed via the SPI interface. Note: different mapping mechanisms used for MIIM and SPI. The “PHYAD” defined in IEEE is assigned as “0x1” for port 1, “0x2” for port 2, “0x3” for port 3, “0x4” for port 4, and “0x5” for port 5. The “REGAD” supported are 0,1,2,3,4,5.

KS8995MA Micrel, Inc. Address Name Description Mode Default Register 1: MII Status 15 T4 Capable 0, Not 100 BASET4 capable. RO 0 14 100 Full Capable 1, 100BASE-TX full-duplex capable. RO 1 0, Not capable of 100BASE-TX full-duplex. 13 100 Half Capable 1, 100BASE-TX half-duplex capable. RO 1 0, Not 100BASE-TX half-duplex capable. 12 10 Full Capable 1, 10BASE-T full-duplex capable. RO 1 0, Not 10BASE-T full-duplex capable. 11 10 Half Capable 1, 10BASE-T half-duplex capable. RO 1 0, 10BASE-T half-duplex capable. 10-7 Reserved RO 0 6 Preamble Suppressed Not supported. RO 0 5 AN Complete 1, Auto-negotiation complete. RO 0 0, Auto-negotiation not completed. 4 Far End Fault 1, Far end fault detected. RO 0 0, No far end fault detected. 3 AN Capable 1, Auto-negotiation capable. RO 1 0, Not auto-negotiation capable. 2 Link Status 1, Link is up. RO 0 0, Link is down. 1 Jabber Test Not supported. RO 0 0 Extended Capable 0, Not extended register capable. RO 0 Register 2: PHYID HIGH 15-0 Phyid High High order PHYID bits. RO 0x0022 Register 3: PHYID LOW 15-0 Phyid Low Low order PHYID bits. RO 0x1450 Register 4: Advertisement Ability 15 Next Page Not supported. RO 0

14 Reserved RO 0

13 Remote Fault Not supported. RO 0 12-11 Reserved RO 0 10 Pause 1, Advertise pause ability. R/W 1 0, Do not advertise pause ability.

9 Reserved R/W 0

8 Adv 100 Full 1, Advertise 100 full-duplex ability. R/W 1 0, Do not advertise 100 full-duplex ability. 7 Adv 100 Half 1, Advertise 100 half-duplex ability. R/W 1 0, Do not advertise 100 half-duplex ability. 6 Adv 10 Full 1, Advertise 10 full-duplex ability. R/W 1 0, Do not advertise 10 full-duplex ability. 5 Adv 10 Half 1, Advertise 10 half-duplex ability. R/W 1 0, Do not advertise 10 half-duplex ability. 4-0 Selector Field 802.3 RO 00001

KS8995MA Micrel, Inc. M9999-051305 62 May 2005 Address Name Description Mode Default Register 5: Link Partner Ability 15 Next Page Not supported. RO 0 14 LP ACK Not supported. RO 0 13 Remote Fault Not supported. RO 0 12-11 Reserved RO 0 10 Pause Link partner pause capability. RO 0

9 Reserved RO 0

8 Adv 100 Full Link partner 100 full capability. RO 0 7 Adv 100 Half Link partner 100 half capability. RO 0 6 Adv 10 Full Link partner 10 full capability. RO 0 5 Adv 10 Half Link partner 10 half capability. RO 0 4-0 Reserved RO 00001

KS8995MA Micrel, Inc. Absolute Maximum Ratings(1) Supply Voltage Storage Temperature (T Operating Ratings(2) Supply Voltage Ambient Temperature (TA) Package Thermal Resistance(3) Electrical Characteristics(4, 5) Symbol Parameter Condition Min Typ Max Units 100BASE-TX Operation — All Ports 100% Utilization IDX 100BASE-TX (Transmitter) V DDAT 229 250 mA IDDC 100BASE-TX (Digital Core/PLL + Analog Rx)VDDC, VDDAP, VDDAR 157 230 mA IDDIO 100BASE-TX (Digital IO) V DDIO 17 30 mA 10BASE-TX Operation — All Ports 100% Utilization IDX 10BASE-TX (Transmitter) V DDAT 350 375 mA IDDC 10BASE-TX (Digital Core + Analog Rx) VDDC, VDDAP 102 180 mA IDDIO 10BASE-TX (Digital IO) V DDIO 61 5 m A Auto-Negotiation Mode IDX 10BASE-TX (Transmitter) V DDAT 25 40 mA IDDC 10BASE-TX (Digital Core + Analog Rx) VDDC, VDDAP 108 180 mA IDDIO 10BASE-TX (Digital IO) V DDIO 17 20 mA TTL Inputs VIH Input High Voltage +2.0 V VIL Input Low Voltage +0.8 V IIN Input Current V IN = GND ~ VDDIO –10 10 V (Excluding Pull-up/Pull-down) TTL Outputs VOH Output High Voltage I OH = –8mA +2.4 V VOL Output Low Voltage I OL = 8mA +0.4 V |IOZ| Output Tri-State Leakage V IN = GND ~ VDDIO 10 µA 100BASE-TX Transmit (measured differentially after 1:1 transformer) VO Peak Differential Output Voltage 100 Ω termination on the differential output 0.95 1.05 V VIMB Output Voltage Imbalance 100 Ω termination on the differential output 2 % tr, tt Rise/Fall Time 35 n s Rise/Fall Time Imbalance 0 0.5 ns Notes: 1. Exceeding the absolute maximum rating may damage the device. 2. The device is not guaranteed to function outside its operating rating. Unused inputs must always be tied to an appropriate logic voltage level (ground to VDD). 3. No heat spreader in package. 4. Specification for packaged product only. 5. Measurements were taken within operating ratings.

KS8995MA Micrel, Inc. M9999-051305 64 May 2005 Symbol Parameter Condition Min Typ Max Units 100BASE-TX Transmit (measured differentially after 1:1 transformer) Duty Cycle Distortion ±0.5 ns Overshoot 5% VSET Reference Voltage of ISET 0.5 V Output Jitters Peak-to-peak 0.7 1.4 ns 10BASE-TX Receive VSQ Squelch Threshold 5MHz square wave 400 mV 10BASE-T Transmit (measured differentially after 1:1 transformer) VDDAT = 2.5V VP Peak Differential Output Voltage 100 Ω termination on the differential output 2.3 V Jitters Added 100 Ω termination on the differential output 16 ns Rise/Fall Times 28 30 ns

Figure 20. SPI Input Timing Table 21. SPI Input Timing Parameters

Figure 21. SPI Output Timing Table 22. SPI Output Timing Parameters

choke is recommended for exceeding FCC requirements. The following table gives recommended transformer characteristics. can be compensated by increasing the line drive current by means of reducing the ISET resistor value. Table 24. Qualified Magnetics Vendors

KS8995MA Micrel, Inc.

Package Information

128-Pin PQFP (PQ) MICREL INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA TEL + 1 (408) 944-0800 FAX + 1 (408) 474-1000 WEB http://www.micrel.com This information furnished by Micrel in this data sheet is believed to be accurate and reliable. However no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser’s own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. © 2003 Micrel, Incorporated.