KS8995E

KS8995E MICREL | Alldatasheet

Document overview

• Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
• PDF pages: 41

Technical content

5-Port 10/100 Integrated Switch with PHY and Frame Buffer Rev. 1.10 General Description The KS8995E contains five 10/100 physical layer transceiv- ers, five MAC (Media Access Control) units with an integrated layer 2 switch. The device runs in two modes. The first mode is a five port integrated switch and the second is as a five port switch with the fifth port decoupled from the physical port. In this mode access to the fifth MAC is provided using an MII (Media Independent Interface). Useful configurations include a stand alone five port switch as well as a four port switch with a routing element connected to the extra MII port. The additional port is also useful for a public network interfacing. The KS8995E is designed to reside in an unmanaged design not requiring processor intervention. This is achieved through I/O strapping or EEPROM programming at system reset time. Micrel, Inc. • 1849 Fortune Drive • San Jose, CA 95131 • USA • tel + 1 (408) 944-0800 • fax + 1 (408) 944-0970 • http://www.micrel.com Functional Diagram Physical Transceiver MAC Look Up Engine (1K Entries) SRAM Buffers (32Kx32) MII / SNI (exclusive) External Interface Physical Transceiver MAC Physical Transceiver MAC Physical Transceiver MAC Physical Transceiver MAC FIFO and Flow Control Queue Management Buffer Management LED and Programming Interface MRXD[3:0] MRXDV MCOL MTXD[3:0] MTXEN MTXER MII_CLK RXP[1], RXM[1] RXP[2], RXM[2] RXP[3], RXM[3] RXP[4], RXM[4] RXP[5], RXM[5]TXP[1], TXM[1] TXP[2], TXM[2] TXP[3], TXM[3] TXP[4], TXM[4] TXP[5], TXM[5] LED[1][3:0] LED[2][3:0] LED[3][3:0] LED[4][3:0] LED[5][3:0] MRXD[0] MRXDV MCOL MTXD[0] MTXEN MII_CLK S N I M I I EEPROM Interface SCL SDA On the media side, the KS8995E supports 10BaseT, 100BaseTX and 100BaseFX as specified by the IEEE 802.3 committee. Physical signal transmission and reception are enhanced through use of analog circuitry that makes the design more efficient and allows for lower power consumption and smaller chip die size. The major enhancements from the KS8995 to the KS8995E are support for VLAN, traffic priority queuing, EEPROM programming for expanded control, MDI/MDI-X auto cross- over. Data sheets and support documentation can be found on Micrel’s web site at www.micrel.com.

Ordering Information

Part Number Temperature Range Package KS8995E 0 °C to +70°C 128-Pin PQFP

Features

• 5-port 10/100 integrated switch with physical layer transceivers
• 128k Byte of SRAM on chip for frame buffering
• 1.4Gbps high performance memory bandwidth
• 10BaseT, 100BaseTX and 100BaseFX modes of operation
• Superior analog technology for reduced power and die size
• Supports port based VLAN
• QoS feature!! Supports DiffServ priority, 802.1p based priority or port-based priority
• Support for UTP or fiber installations
• Indicators for link, activity, full/half-duplex and speed
• Unmanaged operation via strapping or EEPROM at system reset time
• Hardware based 10/100, full/half, flow control and auto- negotiation
• Individual port forced modes (full-duplex, 100BaseTX) when auto-negotiation is disabled
• Wire speed reception and transmission
• Integrated address look-up engine, supports 1K abso- lute MAC addresses
• Automatic address learning, address aging and address migration
• Broadcast storm protection
• Full duplex IEEE 802.3x flow control
• Half duplex back pressure flow control
• Comprehensive LED support
• External MAC interface (MII or SNI) for router applica- tions
• Supports MDI/MDI-X auto crossover
• Single 2.5V power supply
• 700mA (1.75W) including physical transmit drivers
• Commercial temperature range: 0°C to +70°C
• Available in 128-pin PQFP package

Revision History

Revision Date Summary of Changes 1.00 7/28/00 Document origination. 1.01 8/21/00 Change LED programming. 1.02 10/30/00 Update voltage ratings. 1.03 2/02/01 Update transformer recommendations. 1.04 3/27/01 Update maximum frame length values. 1.05 4/20/01 Correct timing information. 1.06 5/03/01 Correct I/O definition. 1.07 5/11/01 Add MDI/MDI-X description. 1.08 7/25/01 Update timing information. 1.09 8/09/01 Add appendix D & MII timing. Add 10BaseTX power dissipation. 1.10 8/29/03 Convert to new format.

5 Port

Figure 1. KS8995E Applications

Pin Number Pin Name Type (Note 1) Port Pin Function

1 N/C Not used - float for normal operation (no connect)

2 TXP[1] O 1 Physical transmit signal + (differential)

3 TXM[1] O 1 Physical transmit signal - (differential)

4 GND_TX[1] GND 1 Ground for transmit circuitry

5 VDD_TX[1:2] P 2.5V for transmit circuitry

6 GND_TX[2] GND 2 Ground for transmit circuitry

7 TXP[2] O 2 Physical transmit signal + (differential)

8 TXM[2] O 2 Physical transmit signal - (differential)

9 N/C Not used - float for normal operation (no connect)

10 VDD_RX[2] P 2 2.5V for equalizer

11 RXP[2] I 2 Physical receive signal + (differential)

12 RXM[2] I 2 Physical receive signal - (differential)

13 GND_RX[2] GND 2 Ground for equalizer

14 VDD_BG P 2.5V for analog circuitry

15 ISET O Set physical transmit output current

16 GND_BG GND Ground for analog circuitry

17 GND_RX[3] GND 3 Ground for equalizer

18 RXP[3] I 3 Physical receive signal + (differential)

19 RXM[3] I 3 Physical receive signal - (differential)

20 VDD_RX[3] P 3 2.5V for equalizer

21 N/C Not used - float for normal operation (no connect)

22 TXP[3] O 3 Physical transmit signal + (differential)

23 TXM[3] O 3 Physical transmit signal - (differential)

24 GND_TX[3] GND 3 Ground for transmit circuitry

25 VDD_TX[3:4] P 2.5V for transmit circuitry

26 GND_TX[4] GND 4 Ground for transmit circuitry

27 TXP[4] O 4 Physical transmit signal + (differential)

28 TXM[4] O 4 Physical transmit signal - (differential)

29 N/C Not used - float for normal operation (no connect)

30 VDD_RX[4] P 4 2.5V for equalizer

31 RXP[4] I 4 Physical receive signal + (differential)

32 RXM[4] I 4 Physical receive signal - (differential)

33 GND_RX[4] GND 4 Ground for equalizer

34 GND_RX[5] GND 5 Ground for equalizer

35 RXP[5] I 5 Physical receive signal + (differential)

36 RXM[5] I 5 Physical receive signal - (differential)

37 VDD_RX[5] P 5 2.5V for equalizer

38 GND_ANA GND Analog ground

Note 1. P = power supply GND = ground I = input O = output I/O = bi-directional

Pin Number Pin Name Type (Note 1) Port Pin Function

39 N/C Not used - float for normal operation (no connect)

40 TXP[5] O 5 Physical transmit signal + (differential)

41 TXM[5] O 5 Physical transmit signal - (differential)

42 GND_TX[5] GND 5 Ground for transmit circuitry

43 VDD_TX[5] P 5 2.5V for transmit circuitry

44 FXSD[2] I 2 Fiber signal detect

45 FXSD[3] I 3 Fiber signal detect

46 FXSD[4] I 4 Fiber signal detect

47 FXSD[5] I 5 Fiber signal detect

48 GND_RCV[5] GND 5 Ground for clock recovery circuitry

49 VDD_RCV[5] P 5 2.5V for clock recovery circuitry 50 VDD_RCV[4] P 4 2.5V for clock recovery circuitry

51 GND_RCV[4] GND 4 Ground for clock recovery circuitry

52 GND_RCV[3] GND 3 Ground for clock recovery circuitry

53 VDD_RCV[3] P 3 2.5V for clock recovery circuitry

54 TEST[1] I Factory test pin – float for normal operation

55 TEST[2] I Factory test pin – float for normal operation

56 SCL O Clock for EEPROM

57 SDA I/O Serial data for EEPROM

58 VDD P 2.5V for core digital circuitry

59 GND GND Ground for digital circuitry

60 MTXEN I 5 MII transmit enable

61 MTXD[3] I 5 MII transmit bit 3

62 MTXD[2] I 5 MII transmit bit 2

63 MTXD[1] I 5 MII transmit bit 1

64 MTXD[0] I 5 MII transmit bit 0

65 MTXER I 5 MII transmit error

66 MII_CLK O 5 MII clock

67 MRXDV O 5 MII receive data valid

68 MRXD[3] O 5 MII receive bit 3

69 MRXD[2] O 5 MII receive bit 2

70 MRXD[1] O 5 MII receive bit 1

71 MRXD[0] O 5 MII receive bit 0

72 MCOL O MII collision detect

73 VDD-IO P 2.5V or 3.3V for MII interface

74 GND GND Ground for digital circuitry

75 P5EXT I 5 External port 5 selector

76 P5SNI I 5 External port 5 mode selector

Note 1. P = power supply GND = ground I = input O = output I/O = bi-directional

Pin Number Pin Name Type (Note 1) Port Pin Function

77 MODESEL[3] I Selects LED and test modes

78 MODESEL[2] I Selects LED and test modes

79 VDD P 2.5V for core digital circuitry

80 GND GND Ground for digital circuitry

81 MODESEL[1] I Selects LED and test modes

82 MODESEL[0] I Selects LED and test modes

83 TESTEN I Factory test pin – tie to ground for normal operation

84 SCANEN I Factory test pin – tie to ground for normal operation

85 RST# I Reset – active low

86 LED[1][3] I/O 1 LED indicator 3

87 LED[1][2] I/O 1 LED indicator 2

88 LED[1][1] I/O 1 LED indicator 1

89 LED[1][0] I/O 1 LED indicator 0

90 LED[2][3] I/O 2 LED indicator 3

91 LED[2][2] I/O 2 LED indicator 2

92 LED[2][1] I/O 2 LED indicator 1

93 LED[2][0] I/O 2 LED indicator 0

94 VDD P 2.5V for core digital circuitry

95 GND GND Ground for digital circuitry

96 LED[3][3] I/O 3 LED indicator 3

97 LED[3][2] I/O 3 LED indicator 2

98 LED[3][1] I/O 3 LED indicator 1

99 LED[3][0] I/O 3 LED indicator 0

100 VDD-IO P 2.5V or 3.3V for MII interface

101 GND GND Ground for digital circuitry

102 LED[4][3] I/O 4 LED indicator 3

103 LED[4][2] I/O 4 LED indicator 2

104 LED[4][1] I/O 4 LED indicator 1

105 LED[4][0] I/O 4 LED indicator 0

106 LED[5][3] I/O 5 LED indicator 3

107 LED[5][2] I/O 5 LED indicator 2

108 LED[5][1] I/O 5 LED indicator 1 /

109 LED[5][0] I/O 5 LED indicator 0 /

110 VDD P 2.5V for core digital circuitry

111 GND GND Ground for digital circuitry

112 X2 O Connect to crystal

113 X1 I Crystal or clock input

114 VDD_PLL P 2.5V for phase locked loop circuitry

115 GND_PLL GND Ground for phase locked loop circuitry

Note 1. P = power supply GND = ground I = input O = output I/O = bi-directional

Pin Number Pin Name Type (Note 1) Port Pin Function

116 GND_RCV[2] GND 2 Ground for clock recovery circuitry

117 VDD_RCV[2] P 2 2.5V for clock recovery circuitry 118 VDD_RCV[1] P 1 2.5V for clock recovery circuitry

119 GND_RCV[1] GND 1 Ground for clock recovery circuitry

120 MUX[2] I Factory test pin – float for normal operation

121 MUX[1] I Factory test pin – float for normal operation

122 FXSD[1] I Fiber signal detect

123 AOUT O Factory test output – float for normal operation

124 GND_RX[1] GND 1 Ground for equalizer

125 RXP[1] I 1 Physical receive signal + (differential)

126 RXM[1] I 1 Physical receive signal - (differential)

127 VDD_RX[1] P 1 2.5V for equalizer

128 GND_ANA GND Analog ground

Note 1. P = power supply GND = ground I = input O = output I/O = bi-directional

MII Media Independant Interface SNI Serial Network Interface IND LED Indicators UP Unmanaged Programmable CTRL Control and Miscellaneous TEST Test (Factory) PWR/GND Power and Ground

Group I/O Names Active Status Description PHY RXP[1:5] Analog Differential inputs (receive) for connection to media (transformer or fiber module) RXM[1:5] TXP[1:5] Analog Differential outputs (transmit) for connection to media (transformer or fiber module) TXM[1:5] FXSD[1:5] H Fiber signal detect - connect to fiber signal detect output on fiber module. Tie low for 100TX mode. ISET Analog Transmit Current Set. Connecting an external reference resistor to set transmitter output current. This pin connects a 1% 3KΩ resistor if a transformer of turns ratio of 1:1 is used. MII MRXD[0:3] H Four bit wide data bus for receiving MAC frames MRXDV H Receive data valid MCOL H Receive collision detection MTXD[0:3] H Four bit wide data bus for transmitting MAC frames MTXEN H Transmit enable MTXER H Transmit error MII_CLK Clock MII interface clock SNI MTXD[0] H Serial transmit data MTXEN H Transmit enable MRXD[0] H Serial receive data MRXDV H Receive carrier sense/data valid MCOL H Collision detection MII_CLK Clock SNI interface clock IND LED[1:5][0] L Output (after reset) Mode 0: Speed (on = 100/off = 10) Mode 1: Speed (on = 100/off = 10) Mode 2: Speed (on = 100/off = 10) Mode 3: Speed (on = 100/off = 10) LED[1:5][1] L Output (after reset) Mode 0: Full Duplex (on = full/off = half) Mode 1: Link (on = connected/off = not connected) Mode 2: Link (on = connected/off = not connected) Mode 3: Reserved LED[1:5][2] L Output (after reset) Mode 0: Collision (on = collision / off = no collision) Mode 1: Transmit Activity (on during transmission) Mode 2: Full Duplex + Collision (constant on = full-duplex / intermittent on = collision/off = half-duplex with no collision) Mode 3: Full Duplex + Collision (constant on = full-duplex / intermittent on = collision/off = half-duplex with no collision) LED[1:5][3] L Output (after reset) Mode 0: Link + Activity Mode 1: Receive Activity (on = receiving/off = not receiving) Mode 2: Activity (on = transmit or receive activity/off = no activity) Mode 3: Link + Activity Note: Mode is set by MODESEL[3:0] ; please see description in UP (unmanaged programming) section.

Group I/O Names Active Status Description (Note 1) UP MODESEL[3:0] H Mode select at reset time. LED mode is selected by using the table below. Note that under normal operation MODESEL[3:2] must be tied low. MODESEL 3 2 1 0 Operation 0 0 0 0 LED mode 0 0 0 0 1 LED mode 1 0 0 1 0 LED mode 2 0 0 1 1 LED mode 3 0 1 0 0 Used for factory testing 0 1 0 1 Used for factory testing 0 1 1 0 Used for factory testing 0 1 1 1 Used for factory testing 1 0 0 0 Used for factory testing 1 0 0 1 Used for factory testing 1 0 1 0 Used for factory testing 1 0 1 1 Used for factory testing 1 1 0 0 Used for factory testing 1 1 0 1 Used for factory testing 1 1 1 0 Used for factory testing 1 1 1 1 Used for factory testing LED[1][3] Programs flow control on all PHY ports at reset time. D = No flow control F/U = Flow control LED[1][2] Programs flow control on the external MAC port at reset time. D = No flow control U = Flow control LED[1][1:0] Programs buffer allocation per port at reset time. Use the following table to select the option: LED[1] 0 1 Description D D 205 buffers max per port (default) D U 512 buffers max per port U D 768 buffers max per port U U 512 buffers (adaptive) per port LED[2][3] Programs MAC address aging in the address look-up table at reset time. Aging eliminates old entries from the table. D = No aging F/U = 5 minute aging LED[2][2] Pull-down for normal operation. LED[2][1] Programs back pressure in half-duplex at reset time. D = No back pressure F/U = Back pressure enabled LED[2][0] Programs aggressive back off in half-duplex at reset time. D = Standard back off F/U = Aggressive mode enabled LED[3][3] Programs no excessive collision drop at reset time. D = Drop after 16 collisions F/U = No drop after 16 collisions LED[3][2] Programs a limit for broadcast frames at reset time. D = No limit U = 25% - 3% limit of broadcast frames Note: EEPROM programming can limit broadcast frames at 25%, 12%, 6% or 3%. See “EEPROM Register” 7 bits 7-6. Note 1. All unmanaged programming takes place at reset time only. For unmanaged programming: F = Float, D = Pull-down, U = Pull-up. See “Reference Circuits” section.

Group I/O Names Active Status Description (Note 1) LED[3][1:0] Programs force 100BaseTX / 10BaseT mode at reset time. Disable auto-negotiation LED[4][3:1] to use this force mode. Use the table below to set this mode on the appropriate port. Signal Port Force 10BaseT Force 100BaseTX Auto-negotiation w/o Auto-negotiation w/o Auto-negotiation enabled LED[3][1] 5 D U F LED[3][0] 4 D U F LED[4][3] 3 D U F LED[4][2] 2 D U F LED[4][1] 1 D U F LED[4][0] Programs force full / half-duplex mode at reset time. Disable auto-negotiation to use LED[5][3:0] this force mode. Use the table below to set this mode on the appropriate port. Signal Port Force half-duplex Force full-duplex Auto-negotiation w/o Auto-negotiation w/o Auto-negotiation enabled LED[4][0] 5 D U F LED[5][3] 4 D U F LED[5][2] 3 D U F LED[5][1] 2 D U F LED[5][0] 1 D U F MRXD[0:3] Programs auto-negotiation enable / disable at reset time. Use the table below to set MCOL this mode on the appropriate port. Signal Port Enable Disable auto-negotiation auto-negotiation MRXD[3] 5 D U MRXD[2] 4 D U MRXD[1] 3 D U MRXD[0] 2 D U MCOL 1 D U Note 1. To use external MII on port 5 disable auto-negotiation by pulling MRXD[3] up. Note 2. Use the “disable auto-negotiation” mode in conjunction with force 10/100 and force full/half-duplex to get the desired configuration. See above descriptions for force modes. CTRL P5EXT H Port 5 external selection. D = 5 port IS mode U = External MAC interface enabled and no longer connected to internal port 5 PHY. P5SNI H Port 5 interface protocol. This is only relevant when P5EXT is tied high. D = MII interface U = SNI interface X1 Clock External crystal or clock input. X2 Clock Used when other polarity of crystal is needed. This is unused for a normal clock input. SCL Clock Clock for EEPROM. SDA Serial data for EEPROM. RST# L System reset. TEST TESTEN H Factory test input: tie to ground for normal operation. SCANEN H Factory test input: tie to ground for normal operation. MUX[1:2] H Factory test input: leave open. AOUT H Factory test output: leave open. TEST[1:2] H Factory test inputs: leave open. Note 1. All unmanaged programming takes place at reset time only. For unmanaged programming: F = Float, D = Pull-down, U = Pull-up. See “Reference Circuits” section.

Group I/O Names Active Status Description PWR VDD-RX[1:5] 2.5V for equalizer. GND-RX[1:5] Ground for equalizer. VDD-TX[1:2] 2.5V for transmit circuitry. VDD-TX[3:4] 2.5V for transmit circuitry. VDD-TX[5] 2.5V for transmit circuitry. GND-TX[1:5] Ground for transmit circuitry. VDD-RCV[1:5] 2.5V for clock recovery circuitry. GND-RCV[1:5] Ground for clock recovery. VDD-PLL 2.5V for phase locked loop circuitry. GND-PLL Ground for phase locked loop circuitry. GND-ANA Analog ground. VDD_BG 2.5V for analog circuits. GND-BG Analog ground. VDD 2.5V for core digital circuitry. VDD-IO 2.5V or 3.3V for MII interface. GND Ground for digital circuitry.

TXP[1] TXM[1] GND_TX[1] VDD_TX[1:2] GND_TX[2] TXP[2] TXM[2] NC VDD_RX[2] RXP[2] RXM[2] GND_RX[2] VDD_BG ISET GND_BG GND_RX[3] RXP[3] RXM[3] VDD_RX[3] NC TXP[3] TXM[3] GND_TX[3] VDD_TX[3:4] GND_TX[4] TXP[4] TXM[4] NC VDD_RX[4] RXP[4] RXM[4] GND_RX[4] GND_RX[5] RXP[5] RXM[5] VDD_RX[5] GND_ANA LED[4][3] GND VDD_IO LED[3][0] LED[3][1] LED[3][2] LED[3][3] GND VDD LED[2][0] LED[2][1] LED[2][2] LED[2][3] LED[1][0] LED[1][1] LED[1][2] LED[1][3] RST# SCANEN TESTEN MODESEL[0] MODESEL[1] GND VDD MODESEL[2] MODESEL[3] P5SNI P5EXT GND VDD_IO MCOL MRXD[0] MRXD[1] MRXD[2] MRXD[3] MRXDV MII_CLK MTXER MTXD[0] MTXD[1] MTXD[2] MTXD[3] MTXEN GND VDD SDA SCL TEST[2] TEST[1] VDD_RCV[3] GND_RCV[3] GND_RCV[4] VDD_RCV[4] VDD_RCV[5] GND_RCV[5] FXSD[5] FXSD[4] FXSD[3] FXSD[2] VDD_TX[5] GND_TX[5] TXM[5] TXP[5] NC LED[4][2] LED[4][1] LED[4][0] LED[5][3] LED[5][2] LED[5][1] LED[5][0] VDD GND VDD_PLL GND_PLL GND_RCV[2] VDD_RCV[2] VDD_RCV[1] GND_RCV[1] MUX[2] MUX[1] FXSD[1] AOUT GND_RX[1] RXP[1] RXM[1] VDD_RX[1] GND_ANA 391 103 128-Pin PQFP (PQ)

Functional Overview: Physical Layer Transceiver 100BaseTX Transmit The 100BaseTX transmit function performs parallel to serial conversion, 4B/5B coding, scrambling, NRZ to NRZI conversion, MLT3 encoding and transmission. The circuit starts with a parallel to serial conversion, which converts the RMII or SMII data from the MAC into a 125MHz serial bit stream. The data and control stream is then converted into 4B/5B coding followed by a scrambler. The serialized data is further converted from NRZ to NRZI format, then transmitted in MLT3 current output. The output current is set by an external 1% 3.01kΩ resistor for the 1:1 transformer ratio. It has a typical rise/fall time of 4 ns and complies to the ANSI TP-PMD standard regarding amplitude balance, overshoot and timing jitters. The wave-shaped 10BaseT output is also incorporated into the 100BaseTX transmitter. 100BaseTX Receive The 100BaseTX receiver function performs adaptive equalization, DC restoration, MLT3 to NRZI conversion, data and clock recovery, NRZI to NRZ conversion, de-scrambling, 4B/5B decoding and serial to parallel conversion. The receiving side starts with the equalization filter to compensate inter-symbol interference (ISI) over the twisted pair cable. Since the amplitude loss and phase distortion is a function of the length of the cable, the equalizer has to adjust its characteristics to optimize the performance. In this design, the variable equalizer will make an initial estimation based on comparisons of incoming signal strength against some known cable characteristics, then tunes itself for optimization. This is an ongoing process and can self adjust against the environmental changes such as temperature variations. The equalized signal then goes through a DC restoration and data conversion block. The DC restoration circuit is used to compensate for the effect of base line wander and improve the dynamic range. The differential data conversion circuit converts the MLT3 format back to NRZI. The slicing threshold is also adaptive. The clock recovery circuit extracts the 125MHz clock from the edges of the NRZI signal. This recovered clock is then used to convert the NRZI signal into the NRZ format. The signal is then sent through the de-scrambler followed by the 4B/5B decoder. Finally, the NRZ serial data is converted to the RMII or SMII formats and provided as the input data to the MAC. PLL Clock Synthesizer The KS8995E generates 125MHz, 42MHz, 25MHz and 10MHz clocks for system timing. Internal clocks are generated from an external 25MHz crystal. Scrambler/De-Scrambler (100BaseTX only) The purpose of the scrambler is to spread the power spectrum of the signal in order to reduce EMI and baseline wander. The data is scrambled by the use of an 11-bit wide linear feedback shift register (LFSR). This can generate a 2047-bit non-repetitive sequence. The receiver will then de-scramble the incoming data stream with the same sequence at the transmitter. 100BaseFX Operation 100BaseFX operation is very similar to 100BaseTX operation with the differences being that the scrambler / de-scrambler and MLT3 encoder/decoder are bypassed on transmission and reception. In this mode the auto-negotiation feature is bypassed since there is no standard that supports fiber auto-negotiation. 100BaseFX Signal Detection The physical port runs in 100BaseFX mode if FXSDx >0.6V. This signal is referenced to VREFx which is set at 1/2 Vdd but can be overridden by an external level. VREFx can be connected to the “minus” signal of a differential pair coming from the fiber module (“plus connects to FXSDx) used to convey signal detect. When FXSDx is below 0.6V then 100BaseFX mode is disabled. 100BaseFX Far End Fault Far end fault occurs when the signal detection is logically false from the receive fiber module. When this occurs, the transmission side signals the other end of the link by sending 84 1’s followed by a zero in the idle period between frames. 10BaseT Transmit The output 10BaseT driver is incorporated into the 100BaseT driver to allow transmission with the same magnetics. They are internally wave-shaped and pre-emphasized into outputs with a typical 2.3V amplitude. The harmonic contents are at least 27dB below the fundamental when driven by an all-ones Manchester-encoded signal. 10BaseT Receive On the receive side, input buffer and level detecting squelch circuits are employed. A differential input receiver circuit and a PLL perform the decoding function. The Manchester-encoded data stream is separated into clock signal and NRZ data. A squelch circuit rejects signals with levels less than 400mV or with short pulse widths in order to prevent noises at the RXP or RXM input from falsely triggering the decoder. When the input exceeds the squelch limit, the PLL locks onto the incoming signal and the KS8995E decodes a data frame. The receiver clock is maintained active during idle periods in between data reception.

individual port basis. In other words, the KS8995E will shutdown most of the internal circuits to save power if there is no link. save on an additional uplink configuration connection. The flow for the link set up is depicted below. Figure 2. Auto-Negotiation

Functional Overview: Switch Core Address Look Up The internal look-up table stores MAC addresses and their associated information. It contains 1K full CAM with 48-bit address plus switching information. The KS8995E is guaranteed to learn 1K addresses and distinguishes itself from hash-based look- up tables which, depending on the operating environment and probabilities, may not guarantee the absolute number of addresses it can learn. Learning The internal look-up engine will update its table with a new entry if the following conditions are met:

• The received packet’s SA does not exist in the look-up table.
• The received packet is good; the packet has no receiving errors, and is of legal length. The look-up engine will insert the qualified SA into the table, along with the port number, time stamp. If the table is full, the last entry of the table will be deleted first to make room for the new entry. Migration The internal look-up engine also monitors whether a station is moved. If it happens, it will update the table accordingly. Migration happens when the following conditions are met:
• The received packet’s SA is in the table but the associated source port information is different.
• The received packet is good; the packet has no receiving errors, and is of legal length. The look-up engine will update the existing record in the table with the new source port information. Aging The look-up engine will update time stamp information of a record whenever the corresponding SA appears. The time stamp is used in the aging process. If a record is not updated for a period of time, the look-up engine will then remove the record from the table. The look-up engine constantly performs the aging process and will continuously remove aging records. The aging period is 300 seconds. This feature can be enabled or disabled by external pull-up or pull-down resistors. Forwarding The KS8995E will forward packets as follows:
• If the DA look-up results is a “match”, the KS8995E will use the destination port information to determine where the packet goes.
• If the DA look-up result is a “miss”, the KS8995E will forward the packet to all other ports except the port that received the packet.
• All the multicast and broadcast packets will be forwarded to all other ports except the source port. The KS8995E will not forward the following packets:
• Error packets. These include framing errors, FCS errors, alignment errors, and illegal size packet errors.
• 802.3x pause frames. The KS8995E will intercept these packets and do the appropriate actions.
• “ Local” packets. Based on destination address (DA) look-up. If the destination port from the look-up table matches the port where the packet was from, the packet is defined as “local”. Switching Engine The KS8995E has a very high performance switching engine to move data to and from the MAC’s, packet buffers. It operates in store and forward mode, while the efficient switching mechanism reduces overall latency. The KS8995E has in internal buffer for frames that is 32Kx32 (128KB). This resource is shared between the five ports. Buffer sizing per port can be programmed at system reset time by using the unmanaged program mode (I/O strapping). Each buffer is sized at 128B and therefore there are a total of 1024 buffers available. A per port maximum can be set at 205 (equal allocation), 512 or 768. There is also an adaptive 512 size mode that reacts to port traffic. MAC (Media Access Controller) Operation The KS8995E strictly abides by IEEE 802.3 standard to maximize compatibility. Inter Packet Gap (IPG) If a frame is successfully transmitted, the 96-bit time IPG is measured between the two consecutive MTXEN. If the current packet is experiencing collision, the 96-bit time IPG is measured from MCRS and the next MTXEN. Backoff Algorithm The KS8995E implements the IEEE Std 802.3 binary exponential back-off algorithm, and optional “aggressive mode” back off. After 16 collisions, the packet will be optionally dropped depending on the chip configuration.

If a transmit packet experiences collisions after 512-bit times of the transmission, the packet will be dropped. Illegal Frames The KS8995E discards frames less than 64 bytes and can be programmed to accept frames up to 1536 bytes. Since the KS8995E supports VLAN tags, the maximum sizing is adjusted when these tags are present. See the “EEPROM ” section for programming options. Flow Control The KS8995E supports standard 802.3x flow control frames on both transmit and receive sides. On the receive side, if the KS8995E receives a pause control frame, the KS8995E will not transmit the next normal frame until the timer, specified in the pause control frame, expires. If another pause frame is received before the current timer expires, the timer will be updated with the new value in the second pause frame. During this period (being flow controlled), only flow control packets from the KS8995E will be transmitted. On the transmit side, the KS8995E has intelligent and efficient ways to determine when to invoke flow control. The flow control is based on availability of the system resources, including available buffers, available transmit queues and available receive queues. The KS8995E will flow control a port, which just received a packet, if the destination port resource is being used up. The KS8995E will issue a flow control frame (XOFF), containing the maximum pause time defined in IEEE standard 802.3x. Once the resource is freed up, the KS8995E will send out the other flow control frame (XON) with zero pause time to turn off the flow control (turn on transmission to the port). A hysterisis feature is provided to prevent flow control mechanism from being activated and deactivated too many times. The KS8995E will flow control all ports if the receive queue becomes full. Half Duplex Back Pressure Half duplex back pressure option (Note: not in 802.3 standards) is also provided. The activation and deactivation conditions are the same as the above in full-duplex mode. If back pressure is required, the KS8995E will send preambles to defer other stations’ transmission (carrier sense deference). To avoid jabber and excessive deference defined in 802.3 standard, after a certain time it will discontinue the carrier sense but it will raise the carrier sense quickly. This short silent time (no carrier sense) is to prevent other stations from sending out packets and keeps other stations in carrier sense deferred state. If the port has packets to send during a back pressure situation, the carrier sense type back pressure will be interrupted and those packets will be transmitted instead. If there are no more packets to send, carrier sense type back pressure will be active again until switch resources free up. If a collision occurs, the binary exponential back-off algorithm is skipped and carrier sense is generated immediately, reducing the chance of further colliding and maintaining carrier sense to prevent reception of packets. Broadcast Storm Protection The KS8995E has an intelligent option to protect the switch system from receiving too many broadcast packets. Broadcast packets will be forwarded to all ports except the source port, and thus will use too many switch resources (bandwidth and available space in transmit queues). The KS8995E will discard broadcast or multicast packets if the number of those packets exceeds the threshold (configured by strapping during reset and EEPROM settings) in a preset period of time. If the preset period expires it will then resume receiving broadcast or multicast packets until the threshold is reached. The options are 25%, 12%, 6% or 3% of network line rate for the maximum broadcast/multicast receiving threshold or unlimited (feature off).

one being for transmission and the other for receiving. The table below describes the signals used in this interface. Table 1. MII Signals indicators that convey when the data is valid and without physical layer errors. For half-duplex operation there is a signal that indicate a collision has occurred during transmission. has a MRXER pin, this should be tied low on the other device.

Table 2. SNI Signal transmit side indicates when data is valid. Likewise, the receive side has an indicator that conveys when the data is valid. For half-duplex operation there is a signal that indicate a collision has occurred during transmission. be effective, the high and low priority queues must be enabled on the destination port or egress point. inbound traffic to the IP phone is all of the same priority to the IP phone. code point can have either a high or low priority. A larger spectrum of priority flows can be defined with this larger code space. is high and if 0, the priority is low. the buffer is shared between all traffic. contained in registers 3-7 bits 5-3 and 0.

The table below briefly summarizes priority features. For more detailed settings see the EEPROM register description. 3 7-6 Global Priority Control Scheme: Transmit buffer high/low interleave control. 5 7 Global Priority Buffer Reserve: Reserves 12KB of the buffer for high priority traffic. 3-7 5 Port Enable Port DSCP: Looks at DSCP field in IP header to decide high or low priority. DSCP field (6 bits) in the IP header. 2 7-0 Global Priority Classification: Determines which tag values have high priority. 3-7 3 Port Enable Port Priority: Determines which ports have high priority traffic. Table 3. Priority Control

1. If this bit is set then unicast frames only see ports within their VLAN. If this bit is cleared unicast frames can traverse VLAN ’s.

“EEPROM Memory Map ” section. bit in each of the registers (sliding position). Table 4. VLAN Control

MAC source address can be programmed as used in flow control frames. either a 200Mb or 400Mb path. This allows high throughput where needed. The frame length enforcement control allows filtering of frames that exceed 1518 bytes for non-VLAN or 1522 bytes for VLAN. The maximum frame size is capped at 1536 bytes. Of course minimum frame size of 64 bytes is always enforced. 4 7-6 Global Port Trunk Control: Allows ports to be aggregated together for higher throughput. 6 6 Global Maximum Frame Length Enforcement: Allows frames up to 1536 bytes to be passed. 7 7-6 Global Broadcast Storm Protection: Allows as much as 25% to as little as 3% broadcast frames. duplex flow control mechanisms. Table 5. Misc Control all other data will be ignored. changes during the clock low time. found in the Atmel AT24C01A specification. clocking. Switch core clocking is now fixed at 42MHz and is no longer adjustable.

Register Bit(s) Description Default (chip) Value 0 7-0 Signature byte 1. Value = “55” 0x55 1 7-0 Signature byte 2. Value = “95” 0x95 Priority Classification Control - 802.1p tag field 2 7 1 = State “111” is high priority 0 0 = State “111” is low priority 2 6 1 = State “110” is high priority 0 0 = State “110” is low priority 2 5 1 = State “101” is high priority 0 0 = State “101” is low priority 2 4 1 = State “100” is high priority 0 0 = State “100” is low priority 2 3 1 = State “011” is high priority 0 0 = State “011” is low priority 2 2 1 = State “010” is high priority 0 0 = State “010” is low priority 2 1 1 = State “001” is high priority 0 0 = State “001” is low priority 2 0 1 = State “000” is high priority 0 0 = State “000” is low priority Control Register 1 3 7-6 Priority control scheme (all ports) 00 00 = Transmit all high priority before any low priority 01= Transmit high and low priority at a 10:1 ratio 10 = Transmit high and low priority at a 5:1 ratio 11 = Transmit high and low priority at a 2:1 ratio 3 5 TOS priority classification enable for port 1 0 1 = Enable, 0 = Disable 3 4 802.1p priority classification enable for port 1 0 1 = Enable, 0 = Disable 3 3 Port based priority classification for port 1 0 1 = Enable, 0 = Disable 3 2 Insert VLAN tags for port 1 if non-existent 0 1 = Enable, 0 = Disable 3 1 Strip VLAN tags for port 1 if existent 0 1 = Enable, 0 = Disable 3 0 Enable high and low output priority queues for port 1 0 1 = Enable, 0 = Disable Control Register 2 4 7-6 Port trunk (link aggregation) control 00 00 = Disable 01 = Ports 1 and 2 are trunked 10 = Ports 1 and 2 are trunked, ports 3 and 4 are trunked 11 = Ports 1, 2, 3, 4 are trunked 4 5 TOS priority classification enable for port 2 0 1 = Enable, 0 = Disable 4 4 802.1p priority classification enable for port 2 0 1 = Enable, 0 = Disable 4 3 Port based priority classification for port 2 0 1 = Enable, 0 = Disable

Register Bit(s) Description Default (chip) Value 4 2 Insert VLAN tags for port 2 if non-existent 0 1 = Enable, 0 = Disable 4 1 Strip VLAN tags for port 2 if existent 0 1 = Enable, 0 = Disable 4 0 Enable high and low output priority queues for port 2 0 1 = Enable, 0 = Disable Control Register 3 5 7 Priority buffer reserve for high priority traffic 0 1 = Reserve 12KB of buffer space for high priority 0 = None reserved 5 6 VLAN enforcement 0 1 = All unicast frames adhere to VLAN configuration 0 = Unicast frames ignore VLAN configuration 5 5 TOS priority classification enable for port 3 0 1 = Enable, 0 = Disable 5 4 802.1p priority classification enable for port 3 0 1 = Enable, 0 = Disable 5 3 Port based priority classification for port 3 0 1 = Enable, 0 = Disable 5 2 Insert VLAN tags for port 3 if non-existent 0 1 = Enable, 0 = Disable 5 1 Strip VLAN tags for port 3 if existent 0 1 = Enable, 0 = Disable 5 0 Enable high and low output priority queues for port 3 0 1 = Enable, 0 = Disable Control Register 4 6 7 Reserved 0 6 6 Maximum frame length enforcement 1 1 = Pass non-VLAN frames between 64-1518 bytes and VLAN frames between 64-1522 bytes 0 = Pass any frame between 64-1536 bytes 6 5 TOS priority classification enable for port 4 0 1 = Enable, 0 = Disable 6 4 802.1p priority classification enable for port 4 0 1 = Enable, 0 = Disable 6 3 Port based priority classification for port 4 0 1 = Enable, 0 = Disable 6 2 Insert VLAN tags for port 4 if non-existent 0 1 = Enable, 0 = Disable 6 1 Strip VLAN tags for port 4 if existent 0 1 = Enable, 0 = Disable 6 0 Enable high and low output priority queues for port 4 0 1 = Enable, 0 = Disable Control Register 5 7 7-6 Broadcast storm protection control 00 00 = Allow 25% broadcast frames 01 = Allow 12% broadcast frames 10 = Allow 6% broadcast frames 11 = Allow 3% broadcast frames 7 5 TOS priority classification enable for port 5 0 1 = Enable, 0 = Disable

Register Bit(s) Description Default (chip) Value 7 4 802.1p priority classification enable for port 5 0 1 = Enable, 0 = Disable 7 3 Port based priority classification for port 5 0 1 = Enable, 0 = Disable 7 2 Insert VLAN tags for port 5 if non-existent 0 1 = Enable, 0 = Disable 7 1 Strip VLAN tags for port 5 if existent 0 1 = Enable, 0 = Disable 7 0 Enable high and low output priority queues for port 5 0 1 = Enable, 0 = Disable Port 1 VLAN Mask Register 8 7-5 Reserved 000 8 4 Port 5 inclusion 1 1 = Port 5 in the same VLAN as port 1 0 = Port 5 not in the same VLAN as port 1 8 3 Port 4 inclusion 1 1 = Port 4 in the same VLAN as port 1 0 = Port 4 not in the same VLAN as port 1 8 2 Port 3 inclusion 1 1 = Port 3 in the same VLAN as port 1 0 = Port 3 not in the same VLAN as port 1 8 1 Port 2 inclusion 1 1 = Port 2 in the same VLAN as port 1 0 = Port 2 not in the same VLAN as port 1 8 0 Reserved 1 Port 2 VLAN Mask Register 9 7-5 Reserved 000 9 4 Port 5 inclusion 1 1 = Port 5 in the same VLAN as port 2 0 = Port 5 not in the same VLAN as port 2 9 3 Port 4 inclusion 1 1 = Port 4 in the same VLAN as port 2 0 = Port 4 not in the same VLAN as port 2 9 2 Port 3 inclusion 1 1 = Port 3 in the same VLAN as port 2 0 = Port 3 not in the same VLAN as port 2 9 1 Reserved 1 9 0 Port 1 inclusion 1 1 = Port 1 in the same VLAN as port 2 0 = Port 1 not in the same VLAN as port 2 Port 3 VLAN Mask Register 10 7-5 Reserved 000 10 4 Port 5 inclusion 1 1 = Port 5 in the same VLAN as port 3 0 = Port 5 not in the same VLAN as port 3 10 3 Port 4 inclusion 1 1 = Port 4 in the same VLAN as port 3 0 = Port 4 not in the same VLAN as port 3 10 2 Reserved 1

Register Bit(s) Description Default (chip) Value 10 1 Port 2 inclusion 1 1 = Port 2 in the same VLAN as port 3 0 = Port 2 not in the same VLAN as port 3 10 0 Port 1 inclusion 1 1 = Port 1 in the same VLAN as port 3 0 = Port 1 not in the same VLAN as port 3 Port 4 VLAN Mask Register 11 7-5 Reserved 000 11 4 Port 5 inclusion 1 1 = Port 5 in the same VLAN as port 4 0 = Port 5 not in the same VLAN as port 4 11 3 Reserved 1 11 2 Port 3 inclusion 1 1 = Port 3 in the same VLAN as port 4 0 = Port 3 not in the same VLAN as port 4 11 1 Port 2 inclusion 1 1 = Port 2 in the same VLAN as port 4 0 = Port 2 not in the same VLAN as port 4 11 0 Port 1 inclusion 1 1 = Port 1 in the same VLAN as port 4 0 = Port 1 not in the same VLAN as port 4 Port 5 VLAN Mask Register 12 7-5 Reserved 000 12 4 Reserved 1 12 3 Port 4 inclusion 1 = Port 4 in the same VLAN as port 5 0 = Port 4 not in the same VLAN as port 5 1 12 2 Port 3 inclusion 1 = Port 3 in the same VLAN as port 5 0 = Port 3 not in the same VLAN as port 5 1 12 1 Port 2 inclusion 1 = Port 2 in the same VLAN as port 5 0 = Port 2 not in the same VLAN as port 5 1 12 0 Port 1 inclusion 1 = Port 1 in the same VLAN as port 5 0 = Port 1 not in the same VLAN as port 5 1 Port 1 VLAN Tag Insertion Value Registers 13 7-5 User priority [2:0] 000 13 4 CFI 0 13 3-0 VID [11:8] 0x0 14 7-0 VID [7:0] 0x00 Port 2 VLAN Tag Insertion Value Registers 15 7-5 User priority [2:0] 000 15 4 CFI 0 15 3-0 VID [11:8] 0x0 16 7-0 VID [7:0] 0x00

Register Bit(s) Description Default (chip) Value Port 3 VLAN Tag Insertion Value Registers 17 7-5 User priority [2:0] 000 17 4 CFI 0 17 3-0 VID [11:8] 0x0 18 7-0 VID [7:0] 0x00 Port 4 VLAN Tag Insertion Value Registers 19 7-5 User priority [2:0] 000 19 4 CFI 0 19 3-0 VID [11:8] 0x0 20 7-0 VID [7:0] 0x00 Port 5 VLAN Tag Insertion Value Registers 21 7-5 User priority [2:0] 000 21 4 CFI 0 21 3-0 VID [11:8] 0x0 22 7-0 VID [7:0] 0x00 Diff Serv Code Point Registers 23 7-0 DSCP[63:56] 0x00 24 7-0 DSCP[55:48] 0x00 25 7-0 DSCP[47:40] 0x00 26 7-0 DSCP[39:32] 0x00 27 7-0 DSCP[31:24] 0x00 28 7-0 DSCP[23:16] 0x00 29 7-0 DSCP[15:8] 0x00 30 7-0 DSCP[7:0] 0x00 Station MAC Address Registers (all ports - MAC control frames only) 31 7-0 MAC address [47:40] 0x00 32 7-0 MAC address [39:32] 0x40 33 7-0 MAC address [31:24] 0x05 34 7-0 MAC address [23:16] 0x43 35 7-0 MAC address [15:8] 0x5E 36 7-0 MAC address [7:0] 0xFE Note. The MAC address is reset to the value in the above table, but can set to any value via the EEPROM interface. This MAC address is used as the source address in MAC control frames that execute flow control between link peers.

Absolute Maximum Ratings (Note 1) Supply Voltage Operating Ratings (Note 2) Package Thermal Resistance (Note 3) Electrical Characteristics (Note 4) VDD = 2.5V to 2.75V; TA = 0°C to +70°C; unless noted. Symbol Parameter Condition Min Typ Max Units VDD Supply Voltage 2.375 2.5 2.625 V Total Supply Current (including TX output driver current) IDD1 Normal 100BaseTX 0.5 A IDD2 Normal 10BaseT 0.7 A TTL Inputs VIH Input High Voltage V DD (I/O) –0.8 V VIL Input Low Voltage 0.8 V IIN Input Current V IN = GND ~ VDD –10 10 µA TTL Outputs VOH Output High Voltage I OH = –4mA V DD (I/O) –0.4 V VOL Output Low Voltage I OL = 4mA 0.4 V |IOZ | Output Tri-State Leakage 10 µA 100BaseTX Receive VB RXP/RXM Input Bias Voltage 1.9 V 100BaseTX Transmit (measured differentially after 1:1 transformer) VO Peak Differential Output Voltage 50Ω from each output to VDD 0.95 1.05 V VIMB Output Voltage Imbalance 50 Ω from each output to VDD 2% tr, tt Rise/Fall Time 35 n s Rise/Fall Time Imbalance 0.5 ns Duty Cycle Distortion ±0.5 ns Overshoot 5% VSET Reference Voltage of ISET 0.75 V Output Jitters Peak-to-peak 0.7 1.4 ns 10BaseTX Receive VSQ Squelch Threshold 5MHz square wave 400 mV Note 1. Exceeding the absolute maximum rating may damage the device. Note 2. The device is not guaranteed to function outside its operating rating. Unused inputs must always be tied to an appropriate logic voltage level (Ground to VDD ). Note 3. No HS (heat spreader) in package. Note 4. Specification for packaged product only.

Symbol Parameter Condition Min Typ Max Units 10BaseTX Transmit (measured differentially after 1:1 transformer) VP Peak Differential Output Voltage 50Ω from each output to VDD 2.3 V Jitters Added 50 Ω from each output to VDD ±3.5 ns Rise/Fall Time 25 ns

Figure 6. Reverse MII Timing–Receive Data from MII Table 10. Reverse MII Timing–Receive Data from MII Parameters

Figure 7. Reverse MII Timing–Transmit Data to MII Table 11. Reverse MII Timing–Transmit Data to MII Parameters

See “I/O Description” section for pull-up/pull-down and float information. Figure 8. Unmanaged Programming Circuit Table 12. Magnetic Vendor List

Table 13. 4B/5B Coding

Figure 9. MLT3 coding Table 14. MAC Frame for 802.3 The MAC (Media Access Control) fields are described in the table below.

Figure 10. 802.1q and 802.1p Frame Format

Selection of Isolation Transformer(Note 1) One simple 1:1 isolation transformer is needed at the line interface. An isolation transformer with integrated common-mode choke is recommended for exceeding FCC requirements. The following table gives recommended transformer characteristics. Characteristics Name Value Test Condition Turns Ratio 1 CT : 1 CT Open-Circuit Inductance (min.) 350 µH 100mV, 100KHz, 8mA Leakage Inductance (max.) 0.4 µH 1MHz (min.) Inter-Winding Capacitance (max.) 12pF D.C. Resistance (max.) 0.9 Ω Insertion Loss (max.) 1.0dB 0MHz to 65MHz HIPOT (min.) 1500Vrms Note 1. The IEEE 802.3u standard for 100BaseTX assumes a transformer loss of 0.5dB. For the transmit line transformer, insertion loss of up to 1.3dB can be compensated by increasing the line drive current by means of reducing the ISET resistor value. Selection of Reference Crystal An oscillator or crystal with the following typical characteristics is recommended. Characteristics Name Value Units Frequency 25.00000 MHz Frequency Tolerance (max.) ±100 ppm Jitter (max.) 150 ps(pk-pk)

Package Information

128-Pin PQFP (PQ) MICREL, INC. 1849 FORTUNE DRIVE SAN JOSE, CA 95131 USA TEL + 1 (408) 944-0800 FAX + 1 (408) 944-0970 WEB http://www.micrel.com The information furnished by Micrel in this datasheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser’s own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. © 2003 Micrel, Incorporated.