KS8721B

KS8721B MICREL | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 32

Technical content

Features

• Single chip 100BaseTX/100BaseFX/10BaseT physical layer solution
• 2.5V CMOS design, power consumption <200mW (excluding output driver current )
• Fully compliant to IEEE 802.3u standard
• Supports Media Independent Interface (MII) and Reduced MII (RMII)
• Supports 10BaseT, 100BaseTX and 100BaseFX with Far_End_Fault Detection
• Supports power down mode and power saving mode
• Configurable through MII serial management ports or via external control pins
• Supports auto-negotiation and manual selection for 10/100Mbps speed and full/half-duplex mode
• On-chip built-in analog front end filtering for both 100BaseTX and 10BaseT Micrel, Inc. • 1849 Fortune Drive • San Jose, CA 95131 • USA • tel + 1 (408) 944-0800 • fax + 1 (408) 944-0970 • http://www.micrel.com Functional Diagram Pulse Shaper NRZ/NRZI MLT3 Encoder Parallel/Serial Manchester Encoder 4B/5B Encoder Scrambler Parallel/SerialTransmitterTX+ TX- Adaptive EQ Base Line Wander Correction MLT3 Decoder NRZI/NRZ Clock Recovery 4B/5B Decoder Descrambler Serial/Parallel Auto Negotiation 10BaseT Receiver Manchester Decoder Serial/Parallel PLL LED Driver MII/RMII Registers and Controller InterfaceRX- RX+ XI XO SPD FDX COL LINK Power Down or Saving PWRDWN RXC TXD3 TXD0 TXD1 TXD2 RXD3 TXEN TXC TXER MDC MDIO COL CRS RXER RXD0 RXD1 RXD2 RXDV

Features (continued)

• LED outputs for link, activity, full/half duplex, collision and speed
• Supports back to back, FX to TX for media converter

applications

• Supports MDI/MDI-X auto crossover
• 2.5V/3.3V tolerance on I/O
• Commercial temperature range: 0°C to +70°C
• Industrial temperature range: –40°C to +85°C
• Available in 48-pin SSOP and TQFP

Ordering Information

Part Number Temperature Range Package KS8721B 0 °C to +70°C 48-Pin SSOP KS8721BI –40 °C to +85°C 48-Pin SSOP KSZ8721B 0 °C to +70°C 48-Pin SSOP Lead Free KS8721BT 0 °C to +70°C 48-Pin TQFP KSZ8721BT 0 °C to +70°C 48-Pin TQFP Lead Free

Revision History

Revision Date Summary of Changes 1.0 2/29/02 Document Origination (Preliminary) 2.0 4/01/02 Update timing Spec from page 33 to page 37 Change Revision ID from 1000 to 1001 Add new control register bit, Control Register 0 Bit 0, to control transmit enable/disable Add 8h register map on the table Editorial Change on FXSD/FXEN pin34 Change on duplex pin38 0=half and 1=full duplex Change on the 10BT MII transmit timing 1.0us to 2.5us and Tlat 2.5us to 4BT Add the TEST description mode on pin26 2.1 1/31/03 Add part number ordering information & remove pinout diagram Edited pin description on the IO cloumn Change the company logo, disclaimer, & contact info Editorial changes on Stapping option description Change on Register0h bit0, 1=disable and 0=enable Add remote fault register4h bit13. Add normal operating condition table & Thermal data for SSOP48 table Add Reset Timing table & Transformer Lists Add 48 TQFP pinout diagram & RMII AC Charateristics Add ordering info for 48 Pin TQFP package, KS8721B/BTI industrial temperature, KSY8721B/KSY8721BT environmentally friendly part number 2.2 8/29/03 Change part number from KS8721B to KS8721B/BT. Change ordering info. from “KSY” to “KSZ” for lead free. Change pin name from RMII_LPBK to RMII_BTB Convert to new format.

Pin Number Pin Name Type (Note 1) Pin Function

1 MDIO I/O Management Interface (MII) Data I/O: This pin requires an external 10K pull-up

resistor.

2 MDC I Management Interface (MII) Clock Input: This pin is synchronous to the MDIO

3 RXD3/ Ipd/O MII Receive Data Output: RXD [3..0], these bits are synchronous with RXCLK. PHYAD1 When RXDV is asserted, RXD [3..0] presents valid data to MAC through the MII. RXD [3..0] is invalid when RXDV is de-asserted. The pull-up/pull-down value is latched as PHYADDR [1] during reset. See “Strapping Options” section for details.

4 RXD2/ Ipd/O MII Receive Data Output: The pull-up/pull-down value is latched as PHYADDR [2]

PHYAD2 during reset. See “Strapping Options” section for details.

5 RXD1/ Ipd/O MII Receive Data Output: The pull-up/pull-down value is latched as PHYADDR [3]

PHYAD3 during reset. See “Strapping Options” section for details.

6 RXD0/ Ipd/O MII Receive Data Output: The pull-up/pull-down value is latched as PHYADDR [4]

PHYAD4 during reset. See “Strapping Options” section for details. 7 VDDIO Pwr Digital IO 2.5 /3.3V tolerance power supply. 8 GND GND Ground.

9 RXDV/ Ipd/O MII Receive Data Valid Output: The pull-up/pull-down value is latched as

CRSDV/ pcs_lpbk during reset. See “Strapping Options” section for details. PCS_LPBK 10 RXC O MII Receive Clock Output: Operating at 25MHz = 100Mbps, 2.5MHz = 10Mbps.

11 RXER/ISO Ipd/O MII Receive Error Output: The pull-up/pull-down value is latched as ISOLATE

during reset. See “Strapping Options” section for details. 12 GND GND Ground. 13 VDDC Pwr Digital core 2.5V only power supply. 14 TXER Ipd MII Transmit Error Input. 15 TXC/ Ipu/O MII Transmit Clock Output: RMII Reference Clock Input. REFCLK

16 TXEN Ipd MII Transmit Enable Input

17 TXD0 Ipd MII Transmit Data Input

18 TXD1 Ipd MII Transmit Data Input

19 TXD2 Ipd MII Transmit Data Input

20 TXD3 Ipd MII Transmit Data Input

21 COL/RMII Ipd/O MII Collision Detect Output: The pull-up/pull-down value is latched as RMII select

during reset. See “Strapping Options” section for details. 24 VDDIO Pwr Digital IO 2.5/3.3V tolerance power supply. Note 1. Pwr = power supply GND = ground I = input O = output I/O = bi-directional Gnd = ground Ipu = input w/ internal pull-up Ipd = input w/ internal pull-down Ipd/O = input w/ internal pull-down during reset, output pin otherwise Ipu/O = input w/ internal pull-up during reset, output pin otherwise PU = strap pin pull-up PD = strap pin pull-down NC = No connect

Pin Number Pin Name Type (Note 1) Pin Function

25 INT#/ Ipu/O Management Interface (MII) Interrupt Out: Latched as PHYAD[0] during power up

PHYAD0 /reset. See “Strapping Options” section for details.

22 CRS/ Ipd/O MII Carrier Sense Output: The pull-up/pull-down value is latched as RMII BTB

RMII_BTB during reset when RMII mode is selected. See “Strapping Options” section for details. 23 GND GND Ground.

26 LED0/TEST Ipu/O Link/Activity LED Output:

Lnk/Act Pin State LED Definition No Link H “off” Link L “on” Act — “Toggle” The external pull-down enable test mode and only used for the factory test. 27 LED1/ Ipu/O Speed LED Output: Latched as SPEED (Register 0, bit 13) during power-up/reset. SPD100/ See “Strapping Options” section for details. noFEF Speed Pin State LED Definition 10BT H “off” 100BT L “on”

28 LED2/ Ipu/O Full-duplex LED Output: Latched as DUPLEX (register 0h, bit 8) during power-up/

DUPLEX reset. See “Strapping Options” section for details. Duplex Pin State LED Definition Half H “off” Full L “on”

29 LED3/ Ipu/O Collision LED Output: Latched as ANEG_EN (register 0h, bit 12) during power-up/

NWAYEN reset. See “Strapping Options” section for details. Collison Pin State LED Definition No Collision H “off” Collision L “on” 30 PD# Ipu Power Down. 1 = Normal operation, 0=Power down, Active low. 31 VDDRX Pwr Analog 2.5V power supply. 32 RX- I Receive Input: Differential receive input pins for FX, 100BaseTX or 10BaseT. 33 RX+ I Receive Input: Differential receive input pin for FX, 100BaseTX or 10BaseT. 34 FXSD/FXEN Ipd/O Fiber Mode Enable / Signal Detect in Fiber Mode. If FXEN = 0, FX mode is disable. The default is “0”. See “100BT FX Mode” section for more details. 35 GND GND Ground. 36 GND GND Ground. Note 1. Pwr = power supply GND = ground I = input O = output I/O = bi-directional Ipu = input w/ internal pull-up Ipd = input w/ internal pull-down Ipd/O = input w/ internal pull-down during reset, output pin otherwise Ipu/O = input w/ internal pull-up during reset, output pin otherwise PU = strap pin pull-up PD = strap pin pull-down NC = No connect

Pin Number Pin Name Type (Note 1) Pin Function 37 REXT I External resistor (6.49k Ω ) connects to REXT and GNDRX. 38 VDDRCV Pwr Analog 2.5V power supply.

39 GND GND Ground

40 TX- O Transmit Outputs: Differential transmit output for 100BaseTX/FX or 10BaseT. 41 TX+ O Transmit Outputs: Differential transmit output for FX, 100BaseTX/FX or 10BaseT. 42 VDDTX Pwr Transmitter 2.5V power supply. 43 GND GND Ground. 44 GND GND Ground. 45 XO O XTAL feedback: Used with XI for Xtal application.

46 XI I Crystal Oscillator Input: Input for a crystal or an external 25MHz clock

47 VDDPLL Pwr Analog PLL 2.5V power supply.

48 RST# Ipu Chip Reset: Active low, minimum of 50 µs pulse is required

Note 1. Pwr = power supply GND = ground I = input O = output I/O = bi-directional Ipu = input w/ internal pull-up Ipd = input w/ internal pull-down Ipd/O = input w/ internal pull-down during reset, output pin otherwise Ipu/O = input w/ internal pull-up during reset, output pin otherwise PU = strap pin pull-up PD = strap pin pull-down NC = No connect

Strapping Options(Note 1) Pin Number Pin Name Type (Note 2) Description 6,5, PHYAD[4:1]/ Ipd/O PHY Address latched at power-up/reset. The default PHY address is 00001. 4,3 RXD[0:3]

25 PHYAD0/ Ipu/O

INT# 9 PCS_LPBK/ Ipd/O Enables PCS_LPBK mode at power-up/reset. PD (default) = Disable, PU = Enable. RXDV 11 ISO/RXER Ipd/O Enables ISOLATE mode at power-up/reset. PD (default) = Disable, PU = Enable. 21 RMII/COL Ipd/O Enables RMII mode at power-up/reset. PD (default) = Disable, PU = Enable. 22 RMII_BTB Ipd/O Enable RMII_BTB mode at power-up/reset. PD (default) = Disable, PU = Enable. CRS 27 SPD100/ Ipu/O Latched into Register 0h bit 13 during power-up/reset. PD = 10Mbps, PU (default) No FEF/ = 100Mbps. If SPD100 is asserted during power-up/reset, this pin also latched as LED1 the Speed Support in register 4h. (If FXEN is pulled up, the latched value 0 means no Far_End _Fault.) 28 DUPLEX/ Ipu/O Latched into Register 0h bit 8 during power-up/reset. PD = Half duplex, PU LED2 (default) = Full duplex. If Duplex is pulled up during reset, this pin also latched as the Duplex support in register 4h. 29 NWAYEN/ Ipu/O Nway (auto-negotiation) Enable. Latched into Register 0h bit 12 during power-up/ LED3 reset. PD = Disable Auto-Negotiation, PU (default) = Enable Auto-Negotiation. 30 PD# Ipu Power Down Enable. PU (default) = Normal operation, PD = Power down mode. Note 1. Strap-in is latched during power-up or reset. Note 2. Ipu = input w/ internal pull-up Ipd = input w/ internal pull-down Ipd/O = input w/ internal pull-down during reset, output pin otherwise Ipu/O = input w/ internal pull-up during reset, output pin otherwise PU = strap pin pull-up PD = strap pin pull-down

VDDIO INT#/PHYAD0 2524 GND LED0/TEST 2623 13VDDC TXER TXC/REF_CLK TXEN TXD0 TXD1 TXD2 TXD3 COL/RMII CRS/RMII_BTB

36 GND

PD# LED3/NWAYEN LED2/DUPLEX LED1/SPD100 GND REXT 3712 RXER/ISO VDDRCV 3811 1MDIO MDC R3D3/PHYAD1 RXD2/PHYAD2 RXD1/PHYAD3 RXD0/PHYAD4 VDDIO GND RXDV/PCS_LPBK RXC

48 RST#

48-Pin SSOP (SM) TXD0 TXEN TXC/REF_CLK TXER VDDC TXD1 TXD2 TXD3 MDIO MDC RXD3/PHYAD1 RXD2/PHYAD2 RXD1/PHYAD3 RXD0/PHYAD4 VDDIO GND 13 14 15 16 17 18 19 20 RXDV/PCS_LPBK RXC RXER/ISO GND COL/RMII CRS/RMII_BTB GND VDDIO 21 22 23 24 GND GND FXSD/FXEN RX+ RX — VDDRX PD# LED3/NWAYEN LED2/DUPLEX LED1/SPD100 LED0/TEST INT#/PHYAD0 GND VDDPLL RST# GND VDDTX TX+ 48 47 46 45 44 43 42 41 TX — GND VDDRCV REXT 40 39 38 37 48-Pin TQFP (TQ)

The 100BaseTX transmit function performs parallel to serial conversion, NRZ to NRZI conversion, MLT-3 encoding and transmission. The circuitry starts with a parallel to serial conversion, which converts the 25MHz, 4-bit nibbles into a 125 MHz serial bit stream. The incoming data is clocked in at the positive edge of the TXC signal. The serialized data is further converted from NRZ to NRZI format, and then transmitted in MLT3 current output. The output current is set by an external 1% 6.49kΩ resistor for the 1: 1 transformer ratio. It has a typical rise/fall times of 4 ns and complies to the ANSI TP-PMD standard regarding amplitude balance, overshoot and timing jitters. The wave-shaped 10BaseT output driver is also incorporated into the 100BaseTX driver. 100BaseTX Receive The 100BaseTX receive function performs adaptive equalization, DC restoration, MLT-3 to NRZI conversion, data and clock recovery, NRZI to NRZ conversion, and serial to parallel conversion. The receiving side starts with the equalization filter to compensate inter-symbol interference (ISI) over the twisted pair cable. Since the amplitude loss and phase distortion are a function of the length of the cable, the equalizer has to adjust its characteristic to optimize the performance. In this design, the variable equalizer will make an initial estimation based on comparisons of incoming signal strength against some known cable characteristics, then tunes itself for optimization. This is an ongoing process and can self adjust against the environmental changes such as temperature variations. The equalized signal then goes through a DC restoration and data conversion block. The DC restoration circuit is used to compensate effect of base line wander and improve the dynamic range. The differential data conversion circuit converts the MLT3 format back to NRZI. The slicing threshold is also adaptive. The clock recovery circuit extracts the 125MHz clock from the edges of the NRZI signal. This recovered clock is then used to convert the NRZI signal into the NRZ format. Finally, the NRZ serial data is converted to 4-bit parallel 4B nibbles. A synchronized 25MHz RXC is generated so that the 4B nibbles is clocked out at the negative edge of RCK25 and is valid for the receiver at the positive edge. When no valid data is present, the clock recovery circuit is locked to the 25MHz reference clock and both TXC and RXC clocks continue to run. PLL Clock Synthesizer The KS8721B/BT generates 125MHz, 25MHz and 20MHz clocks for system timing. An internal crystal oscillator circuit provides the reference clock for the synthesizer. Scrambler/De-scrambler (100BaseTX only) The purpose of the scrambler is to spread the power spectrum of the signal in order to reduce EMI and baseline wander. 10BaseT Transmit When TXEN (transmit enable) goes high, data encoding and transmission will begin. The KS8721B/BT will continue to encode and transmit data as long as TXEN remains high. The data transmission will end when TXEN goes low. The last transition occurs at the boundary of the bit cell if the last bit is zero, or at the center of the bit cell if the last bit is one. The output driver is incorporated into the 100Base driver to allow transmission with the same magnetics. They are internally wave-shaped and pre-emphasized into outputs with a typical 2.5V amplitude. The harmonic contents are at least 27dB below the fundamental when driven by an all-ones Manchester-encoded signal. 10BaseT Receive On the receive side, input buffer and level detecting squelch circuits are employed. A differential input receiver circuit and a PLL performs the decoding function. The Manchester-encoded data stream is separated into clock signal and NRZ data. A squelch circuit rejects signals with levels less than 300mV or with short pulse widths in order to prevent noises at the RX+ or RX- input from falsely trigger the decoder. When the input exceeds the squelch limit, the PLL locks onto the incoming signal and the KS8721B/BT decodes a data frame. This activates the carrier sense (CRS) ad RXDV signals and makes the receive data (RXD) available. The receive clock is maintained active during idle periods in between data reception. SQE and Jabber Function (10BaseT only) In 10BaseT operation, a short pulse will be put out on the COL pin after each packet is transmitted. This is required as a test of the 10BaseT transmit/receive path and is called SQE test. The 10BaseT transmitter will be disabled and COL will go high if TXEN is High for more than 20ms (Jabbering). If TXEN then goes low for more than 250ms, the 10BaseT transmitter will be re-enabled and COL will go Low. Auto-Negotiation The KS8721B/BT performs auto-negotiation by hardware strapping option (pin 29) or software (Register 0.12). It will automatically choose its mode of operation by advertising its abilities and comparing them with those received from its link partner whenever auto-negotiation is enabled. It can also be configured to advertise 100BaseTX or 10BaseT in either full- or half-duplex mode (please refer to “Auto-Negotiation” ). The auto-negotiation is disabled in the FX mode.

During auto-negotiation, the contents of Register 4, coded in Fast Link Pulse (FLP), will be sent to its link partner under the conditions of power-on, link-loss or re-start. At the same time, the KS8721B/BT will monitor incoming data to determine its mode of operation. Parallel detection circuit will be enabled as soon as either 10BaseT NLP (Normal Link Pulse) or 100BaseTX idle is detected. The operation mode is configured based on the following priority: Priority 1: 100BaseTX, full-duplex Priority 2: 100BaseTX, half-duplex Priority 3: 10BaseT, full-duplex Priority 4: 10BaseT, half-duplex When the KS8721B/BT receives a burst of FLP from its link partner with 3 identical link code words (ignoring acknowledge bit), it will store these code words in Register 5 and wait for the next 3 identical code words. Once the KS8721B/BT detects the second code words, it then configures itself according to above-mentioned priority. In addition, the KS8721B/BT also checks 100BaseTX idle or 10BaseT NLP symbol. If either is detected, the KS8721B/BT automatically configures to match the detected operating speed. MII Management Interface The KS8721B/BT supports the IEEE 802.3 MII Management Interface, also known as the Management Data Input / Output (MDIO) Interface. This interface allows upper-layer devices to monitor and control the state of the KS8721B/BT. The MDIO interface consists of the following:

• A physical connection including a data line (MDIO), a clock line (MDC) and an optional interrupt line (INTRPT)
• A specific protocol that runs across the above-mentioned physical connection and it also allows one controller to communicate with multiple KS8721B/BT devices. Each KS8721B/BT assigned an MII address between 0 and 31 by the PHYAD inputs.
• An internal addressable set of fourteen 16-bit MDIO registers. Register [0:6] are required and their functions are specified by the IEEE 802.3 specifications. Additional registers are provided for expanded functionality. The INTPRT pin functions as a management data interrupt in the MII. An active Low or High in this pin indicates a status change on the KS8721B/BT based on 1fh.9 level control. Register bits at 1bh[15:8] are the interrupt enable bits. Register bits at 1bh[7:0] are the interrupt condition bits. This interrupt is cleared by reading Register 1bh. MII Data Interface The data interface consists of separate channels for transmitting data from a 10/100 802.3 compliant Media Access Controller (MAC) to the KS8721B/BT, and for receiving data from the line. Normal data transmission is implemented in 4B Nibble Mode (4-bit wide nibbles). Transmit Clock (TXC):The transmit clock is normally generated by the KS8721B/BT from an external 25MHz reference source at the X1 input. The transmit data and control signals must always be synchronized to the TXC by the MAC. The KS8721B/BT normally samples these signals on the rising edge of the TXC. Receive Clock (RXC):For 100BaseTX links, the receive clock is continuously recovered from the line. If the link goes down, and auto-negotiation is disabled, the receive clock operates off the master input clock (X1 or TXC). For 10BaseT links, the receive clock is recovered from the line while carrier is active, and operates from the master input clock when the line is idle. The KS8721B/BT synchronizes the receive data and control signals on the falling edge of RXC in order to stabilize the signals at the rising edge of the clock with 10ns setup and hold times. Transmit Enable:The MAC must assert TXEN at the same time as the first nibble of the preamble, and de-assert TXEN after the last bit of the packet. Receive Data Valid:The KS8721B/BT asserts RXDV when it receives a valid packet. Line operating speed and MII mode will determine timing changes in the following way:
• For 100BaseTX link with the MII in 4B mode, RXDV is asserted from the first nibble of the preamble to the last nibble of the data packet.
• For 10BaseT links, the entire preamble is truncated. RXDV is asserted with the first nibble of the SFD “ 5D” and remains asserted until the end of the packet. Error Signals:Whenever the KS8721B/BT receives an error symbol from the network, it asserts RXER and drives “1110” (4B) on the RXD pins. When the MAC asserts TXER, the KS8721B/BT will drive “H ” symbols (a Transmit Error define in the IEEE 802.3 4B/5B code group) out on the line to force signaling errors. Carrier Sense (CRS):For 100TX links, a start-of-stream delimiter, or /J/K symbol pair causes assertion of Carrier Sense (CRS). An end-of-stream delimiter, or /T/R symbol pair causes de-assertion of CRS. The PMA layer will also de-assert CRS if IDLE symbols are received without /T/R, yet in this case RXER will be asserted for one clock cycle when CRS is de-asserted. For 10T links, CRS assertion is based on reception of valid preamble, and de-assertion on reception of an end-of-frame (EOF) marker.

Collision:Whenever the line state is half-duplex and the transmitter and receiver are active at the same time, the KS8721B/ BT asserts its collision signal, which is asynchronous to any clock. RMII (Reduced MII) Data Interface RMII interface specifies a low pin count (Reduced) Media Independent Interface (RMII) intended for use between Ethernet PHYs and Switch or Repeater ASICs. It is fully compliant with IEEE 802.3u [2]. This interface has the following characteristics:

• It is capable of supporting 10Mbps and 100Mbps data rates.
• A single clock reference is sourced from the MAC to PHY (or from an external source).
• It provides independent 2-bit wide (di-bit) transmit and receive data paths.
• It uses TTL signal levels, compatible with common digital CMOS ASIC processes. RMII Signal Definition Direction Direction Signal Name (w/ respect to the PHY) (w/ respect to the MAC) Use REF_CLK Input Input or Output Synchronous clock reference for receive, transmit and control interface CRS_DV Output Input Carrier Sense/Receive Data Valid RXD[1:0] Output Input Receive Data TX_EN Input Output Transit Enable TXD[1:0] Input Output Transit Data RX_ER Output Input (Not Required) Receive Error Note 1. Unused MII signals, TXD[3:2], TXER need to tie to GND when RMII is using. Reference Clock (REF_CLK) REF_CLK is a continuous 50MHz clock that provides the timing reference for CRS_DV, RXD[1:0], TX_EN, TXD[1:0], and RX_E. REF_CLK is sourced by the MAC or an external source. Switch implementations may choose to provide REF_CLK as an input or an output depending on whether they provide a REF_CLK output or rely on an external clock distribution device. Each PHY device shall have an input corresponding to this clock but may use a single clock input for multiple PHYs implemented on a single IC. Carrier Sense/Receive Data Valid (CRS_DV) CRS_DV is asserted asynchronously on detection of carrier due to the criteria relevant to the operating mode. That is, in 10BASE-T mode, when squelch is passed or in 100BASE-X mode when 2 non-contiguous zeroes in 10 bits are detected carrier is said to be detected. Loss of carrier shall result in the de-assertion of CRS_DV synchronous to REF_CLK. So long as carrier criteria are being met, CRS_DV shall remain asserted continuously from the first recovered di-bit of the frame through the final recovered di-bit and shall be negated prior to the first REF_CLK that follows the final di-bit. The data on RXD[1:0] is considered valid once CRS_DV is asserted. However, since the assertion of CRS_DV is asynchronous relative to REF_CLK, the data on RXD[1:0] shall be “00” until proper receive signal decoding takes place (see definition of RXD[1:0] behavior). Receive Data [1:0] (RXD[1:0]) RXD[1:0] shall transition synchronously to REF_CLK. For each clock period in which CRS_DV is asserted, RXD[1:0] transfers two bits of recovered data from the PHY. In some cases (e.g. before data recovery or during error conditions) a pre-determined value for RXD[1:0] is transferred instead of recovered data. RXD[1:0] shall be “00” to indicate idle when CRS_DV is de- asserted. Values of RXD[1:0] other than “00” when CRS_DV is de-asserted are reserved for out-of-band signalling (to be defined). Values other than “00” on RXD[1:0] while CRS_DV is de-asserted shall be ignored by the MAC/repeater. Upon assertion of CRS_DV, the PHY shall ensure that RXD[1:0]=00 until proper receive decoding takes place. Transmit Enable (TX_EN) Transmit Enable TX_EN indicates that the MAC is presenting di-bits on TXD[1:0] on the RMII for trans-mission. TX_EN shall be asserted synchronously with the first nibble of the preamble and shall remain asserted while all di-bits to be transmitted are presented to the RMII. TX_EN shall be negated prior to the first REF_CLK following the final di-bit of a frame. TX_EN shall transition synchronously with respect to REF_CLK.

Transmit Data [1:0] (TXD[1:0]) Transmit Data TXD[1:0] shall transition synchronously with respect to REF_CLK. When TX_EN is asserted, TXD[1:0] are accepted for transmission by the PHY. TXD[1:0] shall be “00” to indicate idle when TX_EN is de-asserted. Values of TXD[1:0] other than “00” when TX_EN is de-asserted are reserved for out-of-band signalling (to be defined). Values other than “00” on TXD[1:0] while TX_EN is deasserted shall be ignored by the PHY. Collision Detection Since the definition of CRS_DV and TX_EN both contain an accurate indication of the start of frame, the MAC can reliably regenerate the COL signal of the MII by ANDing TX_EN and CRS_DV. During the IPG time following the successful transmission of a frame, the COL signal is asserted by some transceivers as a self-test. The Signal Quality Error (SQE) function will not be supported by the reduced MII due to the lack of the COL signal. Historically, SQE was present to indicate that a transceiver located physically remote from the MAC was functioning. Since the reduced MII only supports chip-to-chip connections on a PCB, SQE functionality is not required. RX_ER The PHY shall provide RX_ER as an output according to the rules specified in IEEE 802.3u [2] (see Clause 24, Figure 24-11 - Receive State Diagram). RX_ER shall be asserted for one or more REF_CLK periods to indicate that an error (e.g. a coding error or any error that a PHY is capable of detecting, and that may otherwise be undetectable by the MAC sublayer) was detected somewhere in the frame presently being transferred from the PHY. RX_ER shall transition synchronously with respect to REF_CLK. While CRS_DV is de-asserted, RX_ER shall have no effect on the MAC. RMII AC Characteristics Symbol Parameter Min Typ Max Units REF_CLK Frequency 50 MHz REF_CLK Duty Cycle 35 65 % tSU TXD[1:0]. TX_EN, RXD[1:0], CRS_DV, 4 ns RX_ER Data Set-Up to REF_CLK Rising tH TXD[1:0]. TX_EN, RXD[1:0], CRS_DV, 2 ns RXER Data Hold from REF_CLK Rising Edge

• Power Down Mode: This mode can be achieved by writing to Register 0.11 or pulling pin 30 PD# Low.
• Power Saving Mode:This mode can be disabled by writing to Register 1fh.10. The KS8721B/BT will then turn off everything except for the Energy Detect and PLL circuits when the cable is not installed. In other words, the KS8721B/BT will shutdown most of the internal circuits to save power if there is no link. Power saving mode will be in his most effective state when auto-negotiation mode is enable. 100BT FX Mode 100BT FX mode is activated when FXSD/FXEN is higher 0.6V (This pin has a default pull down). Under this mode, the auto- negotiation and auto-MDIX features are disabled. In fiber operation FXSD pin should connect to the SD (signal detect) output of the fiber module. The internal threshold of FXSD is around 1/2 V DD ±50mV (1.25V ±0.05V). Above this level, it is considered fiber signal detected, and the operation is summarized in the following table: FXSD/FXEN Condition Less than 0.6V 100TX mode Less than 1.25V, FX mode but greater than 0.6V No signal detected FEF generated Greater than 1.25 FX mode signal detected

Table 1. 100BT FX Mode is recommended to adjust the SD voltage range. transmit pattern from MAC. FEF can be disabled by strapping pin 27 low. Refer to “Strapping Options” section. at TX mode and the other in FX mode. Both parts can share a common 50MHz oscillator. RXD3 let float. Please contact Micrel FAE for Application Note.

50 MHz

Figure 3. Fiber Module

Register No. Description 0h Basic Control Register 1h Basic Status Register 2h PHY Identifier I 3h PHY Identifier II 4h Auto-Negotiation Advertisement Register 5h Auto-Negotiation Link Partner Ability Register 6h Auto-Negotiation Expansion Register 7h Auto-Negotiation Next Page Register 8h Link Partner Next Page Ability 15h RXER Counter Register 1bh Interrupt Control/Status Register 1fh 100BaseTX PHY Control Register Address Name Description Mode (Note 1) Default Register 0h - Basic Control 0.15 Reset 1 = software reset. Bit is self-clearing RW/SC 0

0.14 Loop-back 1 = loop-back mode; 0 = normal operation RW 0

0.13 Speed Select (LSB) 1 = 100Mbps; 0 = 10Mbps RW Set by

Ignored if Auto-Negotiation is enabled (0.12 = 1) SPD100 0.12 Auto-Negotiation Enable 1 = enable auto-negotiation process (override 0.13 and 0.8) RWSet by 0 = disable auto-negotiation process NWAYEN

0.11 Power Down 1 = power down mode; 0 = normal operation RW 0

0.10 Isolate 1 = electrical isolation of PHY from MII and TX+/TX- RW Set by ISO

0 = normal operation

0.9 Restart Auto-Negotiation 1 = restart auto-negotiation process RW/SC 0

0 = normal operation. Bit is self-clearing

0.8 Duplex Mode 1 = full duplex; 0 = half duplex RW Set by

0.7 Collision Test 1 = enable COL test; 0 = disable COL test RW 0

0.6:1 Reserved RO 0

0.0 Disable 0 = enable transmitter R/W 0

Transmitter 1 = disable transmitter Register 1h - Basic Status 1.15 100BaseT4 1 = T4 capable; 0 = not T4 capable RO 0 1.14 100BaseTX Full Duplex 1 = capable of 100BaseX full duplex RO 1 0 = not capable of 100BaseX full duplex 1.13 100BaseTX Half Duplex 1 = capable of 100BaseX half duplex RO 1 0 = not capable of 100BaseX half duplex 1.12 10BaseT Full Duplex 1 = 10Mbps with full duplex RO 1 0 = no 10Mbps with full duplex capability 1.11 10BaseT Half Duplex 1 = 10Mbps with half duplex RO 1 0 = no 10Mbps with half duplex capability Note 1. RW: Read/Write, RO: Read only, SC: Self clear, LH: Latch High, LL: Latch Low. Some of the default values are set by strap-in. See “Srapping Options.”

Address Name Description Mode (Note 1) Default 1.10:7 Reserved RO 0

1.6 No Preamble 1 = preamble suppression; 0 = normal preamble RO 1

1.5 Auto-Negotiation Complete 1 = auto-negotiation process completed RO 0

0 = auto-negotiation process not completed

1.4 Remote Fault 1 = remote fault; 0 = no remote fault RO/LH 0

1.3 Auto-Negotiation Ability 1 = capable to perform auto-negotiation RO 1

0 = unable to perform auto-negotiation

1.2 Link Status 1 = link is up; 0 = link is down RO/LL 0

1.1 Jabber Detect 1 = jabber detected; 0 = jabber not detected. Default is Low RO/LH 0

1.0 Extended Capability 1 = supports extended capabilities registers RO 1

Register 2h - PHY Identifier 1 2.15:0 PHY ID Number Assigned to the 3rd through 18th bits of the Organizationally RO0022h Unique Identifier (OUI). Micrel’s OUI is 0010A1 (hex) Register 3h - PHY Identifier 2 3.15:10 PHY ID Number Assigned to the 19th through 24th bits of the Organizationally RO000101 Unique Identifier (OUI). Micrel’s OUI is 0010A1 (hex) 3.9:4 Model Number Six bit manufacturer ’s model number RO 100001 3.3:0 Revision Number Four bit manufacturer ’s model number RO 1001 Register 4h - Auto-Negotiation Advertisement 4.15 Next Page 1 = next page capable; 0 = no next page capability. RW 0

4.14 Reserved RO 0

4.13 Remote Fault 1 = remote fault supported; 0 = no remote fault RW 0

4.12 : 11 Reserved RO 0

4.10 Pause 1 = pause function supported; 0 = no pause function RW 0

4.9 100BaseT4 1 = T4 capable; 0 = no T4 capability RO 0 4.8 100BaseTX Full Duplex 1 = TX with full duplex; 0 = no TX full duplex capability RW Set by SPD100 & DUPLEX 4.7 100BaseTX 1 = TX capable; 0 = no TX capability RW Set by SPD100 4.6 10BaseT Full Duplex 1 = 10Mbps with full duplex RW Set by 0 = no 10Mbps full duplex capability DUPLEX 4.5 10BaseT 1 = 10Mbps capable; 0 = no 10Mbps capability RW 1 4.4:0 Selector Field [00001] = IEEE 802.3 RW 00001 Register 5h - Auto-Negotiation Link Partner Ability

5.15 Next Page 1 = next page capable; 0 = no next page capability RO 0

5.14 Acknowledge 1 = link code word received from partner

0 = link code word not yet received RO 0

5.13 Remote Fault 1 = remote fault detected; 0 = no remote fault RO 0

5.12 Reserved RO 0

Note 1. RW: Read/Write, RO: Read only, SC: Self clear, LH: Latch High, LL: Latch Low. Some of the default values are set by strap-in. See “Srapping Options.”

Address Name Description Mode (Note 1) Default 5.11:10 Pause 5.10 5 .11 RO 0 No PAUSE Asymmetric PAUSE (link partner) Symmetric PAUSE Symmetric & Asymmetric PAUSE (local device) 5.9 100 BaseT4 1 = T4 capable; 0 = no T4 capability RO 0 5.8 100BaseTX Full Duplex 1 = TX with full duplex; 0 = no TX full duplex capability RO 0 5.7 100BaseTX 1 = TX capable; 0 = no TX capability RO 0 5.6 10BaseT Full Duplex 1 = 10Mbps with full duplex RO 0 0 = no 10Mbps full duplex capability 5.5 10BaseT 1 = 10Mbps capable; 0 = no 10Mbps capability RO 0 5.4:0 Selector Field [00001] = IEEE 802.3 RO 00001 Register 6h - Auto-Negotiation Expansion 6.15:5 Reserved RO 0

6.4 Parallel Detection Fault 1 = fault detected by parallel detection RO/LH 0

0 = no fault detected by parallel detection.

6.3 Link Partner Next 1 = link partner has next page capability RO 0

Page Able 0 = link partner does not have next page capability

6.2 Next Page Able 1 = local device has next page capability RO 1

0 = local device does not have next page capability

6.1 Page Received 1 = new page received; 0 = new page not yet received RO/LH 0

6.0 Link Partner 1 = link partner has auto-negotiation capability RO 0

Auto-Negotiation Able 0 = link partner does not have auto-negotiation capability Register 7h - Auto-Negotiation Next Page

7.15 Next Page 1 = additional next page(s) will follow; 0 = last page RW 0

7.14 Reserved RO 0

7.13 Message Page 1 = message page; 0 = unformatted page RW 1

7.12 Acknowledge2 1 = will comply with message RW 0

0 = cannot comply with message

7.11 Toggle 1 = previous value of the transmitted link code word RO 0

equaled logic One; 0 = logic Zero 7.10:0 Message Field 11-bit wide field to encode 2048 messages RW 001 Register 8h - Link Partner Next Page Ability

8.15 Next Page 1 = additional Next Page(s) will follow; 0 = last page RO 0

8.14 Acknowledge 1 = successful receipt of link word RO 0

0 = no successful receipt of link word

8.13 Message Page 1 = Message Page; 0 = Unformatted Page RO 0

8.12 Acknowledge2 1 = able to act on the information RO 0

0 = not able to act on the information

8.11 Toggle 1 = previous value of transmitted Link Code Word equal RO 0

to logic zero; 0 = previous value of transmitted Link Code Word equal to logic one 8.10:0 Message Field RO 0 Note 1. RW: Read/Write, RO: Read only, SC: Self clear, LH: Latch High, LL: Latch Low. Some of the default values are set by strap-in. See “Srapping Options.”

Address Name Description Mode (Note 1) Default Register 15h - RXER Counter 15.15:0 RXER Counter RX Error counter for the RX_ER in each package RO 0000 Register 1bh - Interrupt Control/Status Register 1b.15 Jabber Interrupt Enable 1 = Enable Jabber Interrupt; 0=Disable Jabber Interrupt RW 0 1b.14 Receive Error 1 = Enable Receive Error Interrupt RW 0 Interrupt Enable 0 = Disable Receive Error Interrupt 1b.13 Page Received 1 = Enable Page Received Interrupt RW 0 Interrupt Enable 0 = Disable Page Received Interrupt 1b.12 Parallel Detect Fault 1 = Enable Parallel Detect Fault Interrupt RW 0 Interrupt Enable 0 = Disable Parallel Detect Fault Interrupt 1b.11 Link Partner Acknowledge 1 = Enable Link Partner Acknowledge Interrupt RW 0 Interrupt Enable 0 = Disable Link Partner Acknowledge Interrupt 1b.10 Link Down 1 = Enable Link Down Interrupt RW 0 Interrupt Enable 0 = Disable Link Down Interrupt 1b.9 Remote Fault 1 = Enable Remote Fault Interrupt RW 0 Interrupt Enable 0 = Disable Remote Fault Interrupt 1b.8 Link Up Interrupt Enable 1 = Enable Link Up Interrupt RW 0 0 = Disable Link Up Interrupt 1b.7 Jabber Interrupt 1 = Jabber Interrupt Occurred RO 0 0 = Jabber Interrupt Does Not Occurred 1b.6 Receive Error Interrupt 1 = Receive Error Occurred RO 0 0 = Receive Error Does Not Occurred 1b.5 Page Receive Interrupt 1 = Page Receive Occurred RO 0 0 = Page Receive Does Not Occurred 1b.4 Parallel Detect 1 = Parallel Detect Fault Occurred RO 0 Fault Interrupt 0 = Parallel Detect Fault Does Not Occurred 1b.3 Link Partner 1 = Link Partner Acknowledge Occurred RO 0 Acknowledge Interrupt 0 = Link Partner Acknowledge Does Not Occurred 1b.2 Link Down Interrupt 1 = Link Down Occurred RO 0 0 = Link Down Does Not Occurred 1b.1 Remote Fault Interrupt 1 = Remote Fault Occurred RO 0 0 = Remote Fault Does Not Occurred 1b.0 Link Up Interrupt 1 = Link Up Interrupt Occurred RO 0 0 = Link Up Interrupt Does Not Occurred Register 1fh - 100BaseTX PHY Controller 1f.15:14 Reserved 1f:13 Pairswap Disable 1 = Disable MDI/MDIX; 0 = Enable MDI/MDIX R/W 0 1f.12 Energy Detect 1 = Presence of Signal on RX+/- Analog Wire Pair RO 0 0 = No Signal Setected on RX+/- 1f.11 Force Link 1 = Force Link Pass; 0 = Normal Link Operation R/W 0 This bit bypasses the control logic and allow transmitter to send pattern even if there is no link. 1f.10 Power Saving 1 = Enable Ppower Saving; 0 = Disable RW 1 1f.9 Interrupt Level 1 = Interrupt Pin Active High; 0 = Active Low RW 0 1f.8 Enable Jabber 1 = Enable Jabber Counter; 0 = Disable RW 1 1f.7 Auto-Negotiation Complete 1 = Auto-Negotiation Complete; 0 = Not Nomplete RW 0 Note 1. RW: Read/Write, RO: Read only, SC: Self clear, LH: Latch High, LL: Latch Low. Some of the default values are set by strap-in. See “Srapping Options.”

Address Name Description Mode (Note 1) Default 1f.6 Enable Pause 1 = flow control capable; 0 = no flow control RO 0 (Flow-Control Result) 1f.5 PHY Isolate 1 = PHY in isolate mode; 0 = not isolated RO 0 1f.4:2 Operation Mode Indication[000] = still in auto-negotiation RO 0 [001] = 10BaseT half duplex [010] = 100BaseTX half duplex [011] = default [101] = 10BaseT full duplex [110] = 100BaseTX full duplex [111] = PHY/MII isolate 1f.1 Enable SQE Test 1 = enable SQE test; 0 = disable RW 0 1f.0 Disable Data Scrambling 1 = disable scrambler; 0 = enable RW 0 Note 1. RW: Read/Write, RO: Read only, SC: Self clear, LH: Latch High, LL: Latch Low. Some of the default values are set by strap-in. See “Srapping Options.”

Absolute Maximum Ratings (Note 1) Supply Voltage (VDDC , VDD_PLL , VDD_TX , VDD_RCV , Operating Ratings (Note 2) Supply Voltage (VDDC , VDD_PLL , VDD_TX , VDD_RCV , Package Thermal Resistance (Note 3) Electrical Characteristics (Note 4) VDD = 2.5V ±5%; TA = 0°C to +70°C; unless noted; bold values indicate –40°C ≤ TA ≤ +85°C; unless noted. Symbol Parameter Condition Min Typ Max Units Total Supply Current (including TX output driver current) IDD1 Normal 100BaseTX 110 130 mA IDD2 Normal 10BaseT (50% utilization) 150 180 mA IDD3 Power Saving Mode 100BaseTX 40 60 mA IDD5 Power Down Mode 5m A TTL Inputs VIH Input High Voltage V DD (I/O) V –0.8 VIL Input Low Voltage 0.8 V IIN Input Current V IN = GND ~ VDD –10 10 µA TTL Outputs VOH Output High Voltage I OH = –4mA V DD (I/O) V –0.4 VOL Output Low Voltage I OL = 4mA 0.4 V |IOZ | Output Tr-State Leakage 10 µA 100BaseTX Receive R IN RX+/RX – Differential Input 8 k Ω Resistance Propagation Delay from magnetics to RDTX 50 110 ns 100BaseTX Transmit (measured differentially after 1:1 transformer) VO Peak Differential Output Voltage 50Ω from each output to VDD 0.95 1.05 V VIMB Output Voltage Imbalance 50 Ω from each output to VDD 2% tr, tt Rise/Fall Time 35 n s Rise/Fall Time Imbalance 0 0.5 ns 100BaseTX Transmit (measured differentially after 1:1 transformer) Duty Cycle Distortion ±0.5 V Overshoot 5% VSET Reference Voltage of ISET 0.75 ns Propagation Delay from TDTX to magentics 45 60 ns Jitters 0.7 1.4 ns (pk-pk Note 1. Exceeding the absolute maximum rating may damage the device. Note 2. The device is not guaranteed to function outside its operating rating. Unused inputs must always be tied to an appropriate logic voltage level (Ground to VDD ). Note 3. No HS (heat spreader) in package. Note 4. Specification for packaged product only.

Symbol Parameter Condition Min Typ Max Units 10BaseTX Receive R IN RX+/RX – Differential 8k Ω Input Resistance VSQ Squelch Threshold 5MHz square wave 400 mV 10BaseTX Transmit (measured differentially after 1:1 transformer) VP Peak Differential Output Voltage 50Ω from each output to VDD 2.2 2.8 V Jitters Added 50 Ω from each output to VDD ±3.5 ns tr, tt Rise/Fall Time 25 ns Clock Outputs X1, X2 Crystal Oscillator 25 MHZ RXC 100 Receive Clock, 100TX 25 MHZ RXC 10 Receive Clock, 10T 2.5 MHZ Receive Clock Jitters 3.0 ns (pk-pk) TXC 100 Transmit Clock, 100TX 25 MHZ TXC 10 Transmit Clock, 10T 2.5 MHZ Transmit Clock Jitters 1.8 ns (pk-pk)

Figure 4. 10BaseT MII Transmit Timing Table 2. 10BaseT MII Transmit Timing Parameters

Figure 5. 100BaseT MII Transmit Timing Table 3. 100BaseT MII Transmit Timing Parameters

Figure 6. 100BaseT MII Receivce Timing Table 4. 100BaseT MII Receive Timing Parameters

Figure 7. Auto-Negotiation/Fast Link Pulse Timing Table 5. Auto-Negotiation/Fast Link Pulse Timing

Figure 8. Serial Management Interface Timing Table 6. Serial Management Interface Timing

Figure 9. Reset Timing Table 7. Reset Timing Parameters

choke is recommended for exceeding FCC requirements. The following table gives recommended transformer characteristics. 1.3dB can be compensated by increasing the line drive current by means of reducing the ISET resistor value. An oscillator or crystal with the following typical characteristics is recommended. Table 8. Qualified Transformer Lists

Package Information

48-Pin SSOP (SM)

48-Pin TQFP (TQ) MICREL, INC. 1849 FORTUNE DRIVE SAN JOSE, CA 95131 USA TEL + 1 (408) 944-0800 FAX + 1 (408) 944-0970 WEB http://www.micrel.com The information furnished by Micrel in this datasheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser’s own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. © 2003 Micrel, Incorporated.