KBMF STMICROELECTRONICS | Alldatasheet
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EMI FILTER AND LINE TERMINATION FOR PS/2 MOUSE OR KEYBOARD PORTS REV. 2 SOT23-6L (Plastic) October 2004 MAIN APPLICATIONS EMI Filter and line termination for mouse and key- board ports on: ■ Desktop computers ■ Notebooks ■ Workstations ■ Servers
FEATURES
■ Integrated low pass filters for Data and Clock lines ■ Integrated ESD protection ■ Integrated pull-up resistors ■ Small package size ■ Breakdown voltage: VBR = 6V min.
DESCRIPTION
On the implementation of computer systems, the radiated and conducted EMI should be kept within the required levels as stated by the FCC regulations. In addition to the requirements of EMC compatibility, the computing devices are required to tolerate ESD events and remain operational without user intervention. The KBMF implements a low pass filter to limit EMI levels and provide ESD protection which exceeds IEC 61000-4-2 level 4 standard. The device also implements the pull up resistors needed to bias the data and clock lines. The package is the SOT23-6L which is ideal for situations where board space is at a premium. BENEFITS ■ EMI / RFI noise suppression ■ ESD protection exceeding IEC61000-4-2 level 4 ■ High flexibility in the design of high density boards IPAD™ Dat In Clk In Gnd Dat Out Clk Out +Vcc Rs C Rp C +Vcc Rs C Rp C +Vcc Rs Rp C Code 01 39 Ω 4.7kΩ 120pF Tolerance ±10% ±10% ±20% Figure 1: Functional Diagram Table 1: Order Code Part Number Marking KBMF01SC6 KM1 TM: IPAD is a trademark of STMicroelectronics. COMPLIES WITH THE FOLLOWING ESD STANDARDS: IEC 61000-4-2 (R = 330Ω C = 150pF) Level 4 ±15 kV (air discharge) ±8 kV (contact discharge) MIL STD 883C, Method 3015-6 Class 3 C = 100pF R = 1500 Ω 3 positive strikes and 3 negative strikes (F = 1 Hz)
Table 2: Absolute Maximum Ratings (Tamb = 25°C) Table 3: Electrical Characteristics (Tamb = 25°C) TECHNICAL INFORMATION 1. EMI FILTERING The KBMFxxSC6 ensure a filtering protection against ElectroMagnetic and RadioFrequency Interferences thanks to its low-pass filter structure. This filter is characterized by the following parameters : - cut-off frequency - Insertion loss - high frequency rejection Symbol Parameter Value Unit V PP ESD discharge R = 330W C = 150pF contact discharge ESD discharge - MIL STD 883 - Method 3015-6 ±12 ±25 kV Tj Junction temperature 150 °C Tstg Storage temperature range - 55 to +150 °C TL Lead solder temperature (10 second duration) 260 °C Top Operating temperature Range 0 to 70 °C Pr Power rating per resistor 100 mW Symbol Parameters Test conditions Min Typ Max Unit IR Diode leakage current VRM = 5.0V 10 µA VBR Diode breakdown voltage IR = 1mA 6V VF Diode forward voltage drop IF = 50mA 0.9 V Figure 2: Measurements configuration Figure 3: KBMF attenuation curve 50 Ω RF IN Vg 50 Ω TG OUT TEST BOARD KM1 1 10 100 1000 -40 -30 -20 -10 F (MHz) Insertion loss (dB)
- ESD PROTECTION The KBMFxxSC6 is particularly optimized to perform ESD protection. ESD protection is based on the use of device which clamps at: Voutput = VBR + Rd.IPP This protection function is splitted in 2 stages. As shown in figure 4, the ESD strikes are clamped by the first stage S1 and then its remaining overvoltage is applied to the second stage through the resistor R. Such a configuration makes the output voltage very low at the Voutput level. To have a good approximation of the remaining voltages at both V input and V output stages, we give the typical dynamical resistance value Rd. By taking into account these following hypothesis : R t>Rd, Rg>Rd and Rload>Rd, it gives these formulas: The results of the calculation done for VPP=8kV, Rg=330Ω (IEC 61000-4-2 standard), VBR=7V (typ.) and Rd = 1Ω (typ.) give: Vinput = 31.2 V Voutput = 7.8 V This confirms the very low remaining voltage across the device to be protected. It is also important to note that in this approximation the parasitic inductance effect was not taken into account. This could be few tenths of volts during few ns at the input side. This parasitic effect is not present at the output side due the low current involved after the resistance R The measurements done here after show very clearly (figure 6) the high efficiency of the ESD protection : - no influence of the parasitic inductances on output stage - V output clamping voltage very close to VBR (positive strike) and -VF (negative strike) Figure 4: ESD clamping behavior ESD Surge Vinput Voutput Rload Rg RsS1 Rd VBR VBR VPP Device to be protectedKBMFxxSC6 Rd Vinput = Rg VBR Rd Vg ⋅+⋅ Rg Voutput = Rs VBR Rd Vinput ⋅+⋅ Rt
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publicati on are subject to change without notice. This publication supersedes and replac es all information previously supplied. STMicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectro nics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners © 2004 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Ital y - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America