K70P256M150SF3

K70P256M150SF3 FREESCALE | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 92

Technical content

Features

• Operating Characteristics – Voltage range: 1.71 to 3.6 V – Flash write voltage range: 1.71 to 3.6 V – Temperature range (ambient): -40 to 105°C
• Performance – Up to 150 MHz ARM Cortex-M4 core with DSP instructions delivering 1.25 Dhrystone MIPS per MHz
• Memories and memory interfaces – Up to 1024 KB program flash memory on non- FlexMemory devices – Up to 512 KB program flash memory on FlexMemory devices – Up to 512 KB FlexNVM on FlexMemory devices – 16 KB FlexRAM on FlexMemory devices – Up to 128 KB RAM – Serial programming interface (EzPort) – FlexBus external bus interface – DDR controller interface – NAND flash controller interface
• Clocks – 3 to 32 MHz crystal oscillator – 32 kHz crystal oscillator – Multi-purpose clock generator
• System peripherals – 10 low-power modes to provide power optimization based on application requirements – Memory protection unit with multi-master protection – 32-channel DMA controller, supporting up to 128 request sources – External watchdog monitor – Software watchdog – Low-leakage wakeup unit
• Security and integrity modules – Hardware CRC module to support fast cyclic redundancy checks – Tamper detect and secure storage – Hardware random-number generator – Hardware encryption supporting DES, 3DES, AES, MD5, SHA-1, and SHA-256 algorithms – 128-bit unique identification (ID) number per chip
• Human-machine interface – Graphic LCD controller – Low-power hardware touch sensor interface (TSI) – General-purpose input/output
• Analog modules – Four 16-bit SAR ADCs – Programmable gain amplifier (PGA) (up to x64) integrated into each ADC – Two 12-bit DACs – Four analog comparators (CMP) containing a 6-bit DAC and programmable reference input – Voltage reference
• Timers – Programmable delay block – Two 8-channel motor control/general purpose/PWM timers – Two 2-channel quadrature decoder/general purpose timers – IEEE 1588 timers – Periodic interrupt timers – 16-bit low-power timer – Carrier modulator transmitter – Real-time clock Freescale Semiconductor Document Number: K70P256M150SF3 Data Sheet: Advance Information Rev. 3, 2/2012 This document contains information on a new product. Specifications and information herein are subject to change without notice. © 2012 Freescale Semiconductor, Inc. Preliminary

• Communication interfaces – Ethernet controller with MII and RMII interface to external PHY and hardware IEEE 1588 capability – USB high-/full-/low-speed On-the-Go controller with ULPI interface – USB full-/low-speed On-the-Go controller with on-chip transceiver – Two Controller Area Network (CAN) modules – Three SPI modules – Two I2C modules – Six UART modules – Secure Digital host controller (SDHC) – Two I2S modules K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012. 2 Preliminary Freescale Semiconductor, Inc.

3.6 Relationship between ratings and operating

6.8.7 DSPI switching specifications (limited voltage

6.8.8 DSPI switching specifications (full voltage

K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012. Freescale Semiconductor, Inc. Preliminary 3

K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012. 4 Preliminary Freescale Semiconductor, Inc.

1 Ordering parts

1.1 Determining valid orderable parts

Valid orderable part numbers are provided on the web. To determine the orderable part numbers for this device, go to http://www.freescale.com and perform a part number search for the following device numbers: PK70 and MK70.

2 Part identification

2.1 Description

Part numbers for the chip have fields that identify the specific part. You can use the values of these fields to determine the specific part you have received.

2.2 Format

Part numbers for this device have the following format: Q K## A M FFF T PP CC N

2.3 Fields

This table lists the possible values for each field in the part number (not all combinations are valid): Field Description Values Q Qualification status • M = Fully qualified, general market flow

• P = Prequalification K## Kinetis family • K70 A Key attribute • D = Cortex-M4 w/ DSP
• F = Cortex-M4 w/ DSP and FPU M Flash memory type • N = Program flash only
• X = Program flash and FlexMemory Table continues on the next page... Ordering parts K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012. Freescale Semiconductor, Inc. Preliminary 5

FFF Program flash memory size • 32 = 32 KB

• 64 = 64 KB
• 128 = 128 KB
• 256 = 256 KB
• 512 = 512 KB
• 1M0 = 1 MB T Temperature range (°C) • V = –40 to 105
• C = –40 to 85 CC Maximum CPU frequency (MHz) • 15 = 150 MHz N Packaging type • R = Tape and reel
• (Blank) = Trays

2.4 Example

This is an example part number: MK70FN1M0VMJ15

3 Terminology and guidelines

3.1 Definition: Operating requirement

An operating requirement is a specified value or range of values for a technical characteristic that you must guarantee during operation to avoid incorrect operation and possibly decreasing the useful life of the chip.

3.1.1 Example

This is an example of an operating requirement, which you must meet for the accompanying operating behaviors to be guaranteed: Symbol Description Min. Max. Unit VDD 1.0 V core supply voltage 0.9 1.1 V Terminology and guidelines K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012. 6 Preliminary Freescale Semiconductor, Inc.

3.2 Definition: Operating behavior

An operating behavior is a specified value or range of values for a technical characteristic that are guaranteed during operation if you meet the operating requirements and any other specified conditions.

3.2.1 Example

This is an example of an operating behavior, which is guaranteed if you meet the accompanying operating requirements: Symbol Description Min. Max. Unit IWP Digital I/O weak pullup/ pulldown current 10 130 µA

3.3 Definition: Attribute

An attribute is a specified value or range of values for a technical characteristic that are guaranteed, regardless of whether you meet the operating requirements.

3.3.1 Example

This is an example of an attribute: Symbol Description Min. Max. Unit CIN_D Input capacitance: digital pins — 7 pF

3.4 Definition: Rating

A rating is a minimum or maximum value of a technical characteristic that, if exceeded, may cause permanent chip failure:

• Operating ratings apply during operation of the chip.
• Handling ratings apply when the chip is not powered. Terminology and guidelines K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012. Freescale Semiconductor, Inc. Preliminary 7

3.4.1 Example

This is an example of an operating rating: Symbol Description Min. Max. Unit VDD 1.0 V core supply voltage –0.3 1.2 V

3.5 Result of exceeding a rating

Failures in time (ppm) The likelihood of permanent chip failure increases rapidly as soon as a characteristic begins to exceed one of its operating ratings.

3.6 Relationship between ratings and operating requirements

• No permanent failure - Correct operation Normal operating range Limited operating range - No permanent failure - Possible decreased life - Possible incorrect operation Fatal range - Probable permanent failure Limited operating range - No permanent failure - Possible decreased life - Possible incorrect operation Handling range - No permanent failure Fatal range - Probable permanent failure Operating or handling rating (max.)Operating requirement (max.)Operating requirement (min.)Operating or handling rating (min.)

3.7 Guidelines for ratings and operating requirements

Follow these guidelines for ratings and operating requirements:

• Never exceed any of the chip’s ratings. Terminology and guidelines K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012. 8 Preliminary Freescale Semiconductor, Inc.

• During normal operation, don’t exceed any of the chip’s operating requirements.
• If you must exceed an operating requirement at times other than during normal operation (for example, during power sequencing), limit the duration as much as possible.

3.8 Definition: Typical value

A typical value is a specified value for a technical characteristic that:

• Lies within the range of values specified by the operating behavior
• Given the typical manufacturing process, is representative of that characteristic during operation when you meet the typical-value conditions or other specified conditions Typical values are provided as design guidelines and are neither tested nor guaranteed.

3.8.1 Example 1

This is an example of an operating behavior that includes a typical value: Symbol Description Min. Typ. Max. Unit IWP Digital I/O weak pullup/pulldown current 10 70 130 µA

3.8.2 Example 2

This is an example of a chart that shows typical values for various voltage and temperature conditions: Terminology and guidelines K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012. Freescale Semiconductor, Inc. Preliminary 9

150 °C 105 °C 25 °C –40 °C VDD (V) I (μA)DD_STOP TJ

3.9 Typical value conditions

Typical values assume you meet the following conditions (or other conditions as specified): Symbol Description Value Unit TA Ambient temperature 25 °C VDD 3.3 V supply voltage 3.3 V

4 Ratings

4.1 Thermal handling ratings

Symbol Description Min. Max. Unit Notes TSTG Storage temperature –55 150 °C 1 TSDR Solder temperature, lead-free — 260 °C 2 1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life. 2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices. Ratings K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012. 10 Preliminary Freescale Semiconductor, Inc.

4.2 Moisture handling ratings

Symbol Description Min. Max. Unit Notes MSL Moisture sensitivity level — 3 — 1 1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices.

4.3 ESD handling ratings

Symbol Description Min. Max. Unit Notes VHBM Electrostatic discharge voltage, human body model -2000 +2000 V 1 VCDM Electrostatic discharge voltage, charged-device model -500 +500 V 2 ILAT Latch-up current at ambient temperature of 105°C -100 +100 mA 1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM). 2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.

4.4 Voltage and current operating ratings

Symbol Description Min. Max. Unit VDD Digital supply voltage1 –0.3 3.8 V VDD_INT Core supply voltage –0.3 3.8 V VDD_DDR DDR I/O supply voltage –0.3 3.8 V IDD Digital supply current — 300 mA IDD_INT Core supply current — 185 mA IDD_DDR DDR supply current — 220 mA VDIO Digital input voltage (except RESET, EXTAL0/XTAL0, and EXTAL1/XTAL1) 2 –0.3 5.5 V VDTamper Tamper input voltage –0.3 VBAT + 0.3 V VDDDR DDR input voltage –0.3 VDD_DDR + 0.3 V VAIO Analog3, RESET, EXTAL0/XTAL0, and EXTAL1/XTAL1 input voltage –0.3 VDD + 0.3 V Table continues on the next page... Ratings K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012. Freescale Semiconductor, Inc. Preliminary 11

1. It applies for all port pins except Tamper pins.
2. It covers digital pins except Tamper pins and DDR pins.
3. Analog pins are defined as pins that do not have an associated general purpose I/O port function.

5 General

5.1 AC electrical characteristics

Figure 1. Input signal measurement reference

• have C L=30pF loads,
• are configured for fast slew rate (PORTx_PCRn[SRE]=0), and
• are configured for high drive strength (PORTx_PCRn[DSE]=1) 2. input pins
• have their passive filter disabled (PORTx_PCRn[PFE]=0) General K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012. 12 Preliminary Freescale Semiconductor, Inc.

5.2 Nonswitching electrical specifications

5.2.1 Voltage and current operating requirements

Table 1. Voltage and current operating requirements

• DDR1
• DDR2/LPDDR 2.3 1.7 2.7 1.9 V V VREF_DDR Input reference voltage (DDR1/DDR2) 0.49 × VDD_DDR 0.51 × VDD_DDR V VDDA Analog supply voltage 1.71 3.6 V VDD – VDDA VDD-to-VDDA differential voltage –0.1 0.1 V VSS – VSSA VSS-to-VSSA differential voltage –0.1 0.1 V VBAT RTC battery supply voltage 1.71 3.6 V VIH Input high voltage (digital pins except Tamper pins and DDR pins)
• 2.7 V ≤ V DD ≤ 3.6 V
• 1.7 V ≤ V DD ≤ 2.7 V 0.7 × VDD 0.75 × VDD V V VIL Input low voltage (digital pins except Tamper pins and DDR pins)
• 2.7 V ≤ V DD ≤ 3.6 V
• 1.7 V ≤ V DD ≤ 2.7 V 0.35 × VDD 0.3 × VDD V V VIH_DDR Input high voltage (DDR pins)
• DDR1
• DDR2
• LPDDR VREF_DDR + 0.15 VREF_DDR + 0.125 0.7 × VDD_DDR V V V Table continues on the next page... General K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012. Freescale Semiconductor, Inc. Preliminary 13

Table 1. Voltage and current operating requirements (continued)

• DDR1
• DDR2
• LPDDR VREF_DDR – 0.15 VREF_DDR – 0.125 0.3 × VDD_DDR V V V VIH_Tamper Tamper input high voltage
• 2.7 V ≤ V BAT ≤ 3.6 V
• 1.7 V ≤ V BAT ≤ 2.7 V 0.7 × VBAT 0.75 × VBAT V V VIL_Tamper Tamper input low voltage
• 2.7 V ≤ V BAT ≤ 3.6 V
• 1.7 V ≤ V BAT ≤ 2.7 V 0.35 × VBAT 0.3 × VBAT V V VHYS Input hysteresis (digital pins except Tamper pins and DDR pins) 0.06 × VDD — V VHYS_Tamper Input hysteresis (Tamper pins) 0.06 × VBAT — V IICDIO Digital pin (except Tamper pins and DDR pins) negative DC injection current — single pin
• V IN < VSS-0.3V -5 — mA IICDIO_DDR DDR pin negative DC injection current -- single pin
• TBD TBD TBD mA IICDIO_Tamper Tamper pin negative DC injection current — single pin
• V IN < VSS-0.3V
• V IN > VBAT -0.2 2.0 mA mA IICAIO Analog2, EXTAL0/XTAL0, and EXTAL1/XTAL1 pin DC injection current — single pin
• V IN < VSS-0.3V (Negative current injection)
• V IN > VDD+0.3V (Positive current injection) mA IICcont Contiguous pin DC injection current —regional limit, includes sum of negative injection currents or sum of positive injection currents of 16 contiguous pins
• Negative current injection
• Positive current injection -25 +25 mA VRAM VDD (VDD_INT) voltage required to retain RAM 1.2 — V VRFVBAT VBAT voltage required to retain the VBAT register file VPOR_VBAT — V 1. All 5 V tolerant digital I/O pins are internally clamped to VSS through a ESD protection diode. There is no diode connection to VDD. If VIN greater than VDIO_MIN (=VSS-0.3V) is observed, then there is no need to provide current limiting resistors at General K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012. 14 Preliminary Freescale Semiconductor, Inc.

limiting resistor is calculated as R=(VDIO_MIN-VIN)/|IIC|.

1. Analog pins are defined as pins that do not have an associated general purpose I/O port function.
2. All analog pins are internally clamped to VSS and VDD through ESD protection diodes. If VIN is greater than VAIO_MIN

calcualted as R=(VIN-VAIO_MAX)/|IIC|. Select the larger of these two calculated resistances.

5.2.2 LVD and POR operating requirements

Table 2. LVD and POR operating requirements

• Level 1 falling (LVWV=00)
• Level 2 falling (LVWV=01)
• Level 3 falling (LVWV=10)
• Level 4 falling (LVWV=11) 2.62 2.72 2.82 2.92 2.70 2.80 2.90 3.00 2.78 2.88 2.98 3.08 V V V V VHYSH Low-voltage inhibit reset/recover hysteresis — high range — ±80 — mV VLVDL Falling low-voltage detect threshold — low range (LVDV=00) 1.54 1.60 1.66 V VLVW1L VLVW2L VLVW3L VLVW4L Low-voltage warning thresholds — low range
• Level 1 falling (LVWV=00)
• Level 2 falling (LVWV=01)
• Level 3 falling (LVWV=10)
• Level 4 falling (LVWV=11) 1.74 1.84 1.94 2.04 1.80 1.90 2.00 2.10 1.86 1.96 2.06 2.16 V V V V VHYSL Low-voltage inhibit reset/recover hysteresis — low range — ±60 — mV VBG Bandgap voltage reference 0.97 1.00 1.03 V tLPO Internal low power oscillator period factory trimmed 900 1000 1100 μs 1. Rising thresholds are falling threshold + hysteresis voltage

Table 3. VBAT power operating requirements K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.

5.2.3 Voltage and current operating behaviors

Table 4. Voltage and current operating behaviors

• 2.7 V ≤ V DD ≤ 3.6 V, IOH = -9mA
• 1.71 V ≤ V DD ≤ 2.7 V, IOH = -3mA VDD – 0.5 VDD – 0.5 V V Output high voltage — low drive strength
• 2.7 V ≤ V DD ≤ 3.6 V, IOH = -2mA
• 1.71 V ≤ V DD ≤ 2.7 V, IOH = -0.6mA VDD – 0.5 VDD – 0.5 V V IOHT Output high current total for all ports — 100 mA IOHT_io60 Output high current total for fast digital ports — 100 mA VOH_DDR Output high voltage for DDR pins
• DDR1 (I OH = -16.2 mA)
• DDR2 half strength (I OH = TBD mA)
• DDR2 full strength (I OH = -13.4 mA)
• LPDDR half strength (I OH = -0.1 mA)
• LPDDR full strength (I OH = -0.1 mA) VDD_DDR - 0.36 VDD_DDR - 0.28 VDD_DDR - 0.28 0.9 x VDD_DDR 0.9 x VDD_DDR V V V V V IOHT_DDR Output high current total for DDR pins
• DDR1
• DDR2
• LPDDR — TBD mA VOH_Tamper Output high voltage — high drive strength
• 2.7 V ≤ V BAT ≤ 3.6 V, IOH = -10mA
• 1.71 V ≤ V BAT ≤ 2.7 V, IOH = -3mA VBAT – 0.5 VBAT – 0.5 V V Output high voltage — low drive strength
• 2.7 V ≤ V BAT ≤ 3.6 V, IOH = -2mA
• 1.71 V ≤ V BAT ≤ 2.7 V, IOH = -0.6mA VBAT – 0.5 VBAT – 0.5 V V IOH_Tamper Output high current total for Tamper pins — TBD mA Table continues on the next page... General K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012. 16 Preliminary Freescale Semiconductor, Inc.

Table 4. Voltage and current operating behaviors (continued)

• 2.7 V ≤ V DD ≤ 3.6 V, IOL = 9mA
• 1.71 V ≤ V DD ≤ 2.7 V, IOL = 3mA 0.5 0.5 V V Output low voltage — low drive strength
• 2.7 V ≤ V DD ≤ 3.6 V, IOL = 2mA
• 1.71 V ≤ V DD ≤ 2.7 V, IOL = 0.6mA 0.5 0.5 V V IOLT Output low current total for all ports — TBD mA IOLT_io60 Output low current total for fast digital ports — TBD mA VOL_DDR Output low voltage for DDR pins
• DDR1 (I OL = 16.2 mA)
• DDR2 half strength (I OL = TBD mA)
• DDR2 full strength (I OL = 13.4 mA)
• LPDDR half strength (I OL = 0.1 mA)
• LPDDR full strength (I OL = 0.1 mA) 0.37 0.28 0.28 0.1 x VDD_DDR 0.1 x VDD_DDR V V V V V IOLT_DDR Output low current total for DDR pins
• DDR1
• DDR2
• LPDDR — TBD mA VOL_Tamper Output low voltage — high drive strength
• 2.7 V ≤ V BAT ≤ 3.6 V, IOL = 10mA
• 1.71 V ≤ V BAT ≤ 2.7 V, IOL = 3mA 0.5 0.5 V V Output low voltage — low drive strength
• 2.7 V ≤ V BAT ≤ 3.6 V, IOL = 2mA
• 1.71 V ≤ V BAT ≤ 2.7 V, IOL = 0.6mA 0.5 0.5 V V IOL_Tamper Output low current total for Tamper pins — TBD mA IIN Input leakage current (per pin) for full temperature range — 1 μA 1 IIN Input leakage current (per pin) at 25°C — 0.025 μA 1 IIN_DDR Input leakage current (per DDR pin) for full temperature range — 1 μA IIN_DDR Input leakage current (per DDR pin) at 25°C — 0.025 μA IIN_Tamper Input leakage current (per Tamper pin) for full temperature range — TBD μA IIN_Tamper Input leakage current (per Tamper pin) at 25°C — 0.025 μA Table continues on the next page... General K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012. Freescale Semiconductor, Inc. Preliminary 17

• R tt1(eff) - 75 Ω
• R tt2(eff) - 150 Ω 120 180 Ω Ω 1. Measured at VDD=3.6V 2. Measured at VDD supply voltage = VDD min and Vinput = VSS 3. Measured at VDD supply voltage = VDD min and Vinput = VDD

5.2.4 Power mode transition operating behaviors

• CPU and system clocks = 150 MHz
• Bus clock = 75 MHz
• FlexBus clock = 50 MHz
• Flash clock = 25 MHz

Table 5. Power mode transition operating behaviors across the operating temperature range of the chip.

• VLLS1 → RUN — 126 μs
• VLLS2 → RUN — 82 μs
• VLLS3 → RUN — 82 μs
• LLS → RUN — 5.0 μs Table continues on the next page... General K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012. 18 Preliminary Freescale Semiconductor, Inc.

Table 5. Power mode transition operating behaviors (continued)

• VLPS → RUN — TBD μs
• STOP → RUN — TBD μs 1. Normal boot (FTFE_FOPT[LPBOOT]=1)

5.2.5 Power consumption operating behaviors

Table 6. Power consumption operating behaviors

• @ 1.8V
• @ 3.0V TBD TBD mA mA IDD_RUN Run mode current — all peripheral clocks enabled, code executing from flash
• @ 1.8V
• @ 3.0V TBD TBD mA mA IDD_WAIT Wait mode high frequency current at 3.0 V — all peripheral clocks disabled — 37 TBD mA 2 IDD_WAIT Wait mode reduced frequency current at 3.0 V — all peripheral clocks disabled — 21 TBD mA 4 IDD_STOP Stop mode current at 3.0 V
• @ –40 to 25°C
• @ 70°C
• @ 105°C TBD TBD TBD TBD TBD TBD mA mA mA IDD_VLPR Very-low-power run mode current at 3.0 V — all peripheral clocks disabled — 2.3 TBD mA 5 IDD_VLPR Very-low-power run mode current at 3.0 V — all peripheral clocks enabled — 3.1 TBD mA 6 IDD_VLPW Very-low-power wait mode current at 3.0 V — 1.8 TBD mA 7 IDD_VLPS Very-low-power stop mode current at 3.0 V
• @ –40 to 25°C
• @ 70°C
• @ 105°C 200 TBD TBD TBD TBD TBD μA μA μA Table continues on the next page... General K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012. Freescale Semiconductor, Inc. Preliminary 19

Table 6. Power consumption operating behaviors (continued)

• @ –40 to 25°C
• @ 70°C
• @ 105°C 200 TBD TBD TBD TBD TBD μA μA μA IDD_VLLS3 Very low-leakage stop mode 3 current at 3.0 V
• @ –40 to 25°C
• @ 70°C
• @ 105°C 6.5 37.4 148.3 TBD TBD TBD μA μA μA IDD_VLLS2 Very low-leakage stop mode 2 current at 3.0 V
• @ –40 to 25°C
• @ 70°C
• @ 105°C 3.4 13.4 58.5 TBD TBD TBD μA μA μA IDD_VLLS1 Very low-leakage stop mode 1 current at 3.0 V
• @ –40 to 25°C
• @ 70°C
• @ 105°C 2.9 9.8 44.7 TBD TBD TBD μA μA μA IDD_VBAT Average current when CPU is not accessing RTC registers at 3.0 V
• @ –40 to 25°C
• @ 70°C
• @ 105°C 0.91 1.5 4.3 1.1 1.85 4.3 μA μA μA 1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See each module's specification for its supply current. 2. 150 MHz core and system clock, 75 MHz bus, 50 MHz FlexBus clock, and 25 MHz flash clock. MCG configured for PEE mode. All peripheral clocks disabled. 3. 150 MHz core and system clock, 75 MHz bus, 50 MHz FlexBus clock, and 25 MHz flash clock. MCG configured for PEE mode. All peripheral clocks enabled, but peripherals are not in active operation. 4. 25 MHz core and system clock, 25 MHz bus clock, and 12.5 MHz FlexBus and flash clock. MCG configured for FEI mode. 5. 4 MHz core, system, 2 MHz FlexBus, and 2 MHz bus clock and 1 MHz flash clock. MCG configured for BLPE mode. All peripheral clocks disabled. 6. 4 MHz core, system, 2 MHz FlexBus, and 2 MHz bus clock and 1 MHz flash clock. MCG configured for BLPE mode. All peripheral clocks disabled. 7. 4 MHz core, system, 2 MHz FlexBus, and 2 MHz bus clock and 1 MHz flash clock. MCG configured for BLPE mode. All peripheral clocks disabled. 8. Includes 32kHz oscillator current and RTC operation.

5.2.5.1 Diagram: Typical IDD_RUN operating behavior

K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012. 20 Preliminary Freescale Semiconductor, Inc.

• MCG in FBE mode for 50 MHz and lower frequencies. MCG in FEE mode at greater than 50 MHz frequencies. MCG in PEE mode is greater than 100 MHz frequencies.
• USB regulator disabled
• No GPIOs toggled
• Code execution from flash with cache enabled
• For the ALLOFF curve, all peripheral clocks are disabled except FTFL

Figure 2. Run mode supply current vs. core frequency K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.

Figure 3. VLPR mode supply current vs. core frequency

5.2.6 EMC radiated emissions operating behaviors

Table 7. EMC radiated emissions operating behaviors for 256MAPBGA

1. Determined according to IEC Standard 61967-1, Integrated Circuits - Measurement of Electromagnetic Emissions, 150

K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012. 22 Preliminary Freescale Semiconductor, Inc.

measured orientations in each frequency range.

1. Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and Wideband

5.2.7 Designing with radiated emissions in mind

1. Go to http://www.freescale.com.
2. Perform a keyword search for “EMC design.”

5.2.8 Capacitance attributes

Table 8. Capacitance attributes

5.3 Switching specifications

5.3.1 Device clock specifications

Table 9. Device clock specifications

• 10 Mbps
• 100 Mbps MHz fBUS Bus clock — 75 MHz Table continues on the next page... General K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012. Freescale Semiconductor, Inc. Preliminary 23

Table 9. Device clock specifications (continued)

1. The frequency limitations in VLPR mode here override any frequency specification listed in the timing specification for any

5.3.2 General switching specifications

CAN, CMT, IEEE 1588 timer, and I2C signals. Table 10. General switching specifications

• Slew disabled
• Slew enabled TBD TBD ns ns tio50 Port rise and fall time (low drive strength)
• Slew disabled
• Slew enabled TBD TBD ns ns Table continues on the next page... General K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012. 24 Preliminary Freescale Semiconductor, Inc.

Table 10. General switching specifications (continued)

• Slew disabled
• Slew enabled TBD TBD ns ns tio60 Port rise and fall time (low drive strength)
• Slew disabled
• Slew enabled TBD TBD ns ns ttamper Port rise and fall time (high drive strength)
• Slew disabled
• Slew enabled TBD TBD ns ns ttamper Port rise and fall time (low drive strength)
• Slew disabled
• Slew enabled TBD TBD ns ns tddr Port rise time
• DDR1
• DDR2
• LPDDR TBD TBD TBD ns ns ns tddr Port fall time
• DDR1
• DDR2
• LPDDR TBD TBD TBD ns ns ns 1. The greater synchronous and asynchronous timing must be met. 2. This is the shortest pulse that is guaranteed to be recognized. 3. 25pF load 4. 15pF load 5. 75pF load 6. 15pF load 7. 75pF load 8. 15pF load 9. DDR —rise and fall times at 50 Ω transmission line impedance terminated to 0.5 × VDD_DDR + 5 pF load. 10. Rising slew rate measured between 0.5 × VDD_DDR and 0.5 × VDD_DDR + 250 mV for all modes. 11. Falling slew rate measured between 0.5 × VDD_DDR and 0.5 × VDD_DDR – 250 mV for all modes.

5.4 Thermal specifications

K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.

5.4.1 Thermal operating requirements

Table 11. Thermal operating requirements

5.4.2 Thermal attributes

1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site
2. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental

Conditions—Natural Convection (Still Air) with the single layer board horizontal. Board meets JESD51-9 specification.

1. Determined according to JEDEC Standard JESD51-6, Integrated Circuits Thermal Test Method Environmental

Conditions—Forced Convection (Moving Air) with the board horizontal.

1. Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental

Conditions—Junction-to-Board. Board temperature is measured on the top surface of the board near the package. K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012. 26 Preliminary Freescale Semiconductor, Inc.

1. Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate

between the top of the package and the cold plate.

1. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental

Conditions—Natural Convection (Still Air).

6 Peripheral operating requirements and behaviors

6.1 Core modules

6.1.1 Debug trace timing specifications

Table 12. Debug trace operating behaviors Figure 4. TRACE_CLKOUT specifications Figure 5. Trace data specifications K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.

6.1.2 JTAG electricals

Table 13. JTAG voltage range electricals

• JTAG
• CJTAG MHz J2 TCLK cycle period 1/J1 — ns J3 TCLK clock pulse width
• JTAG
• CJTAG 100 200 ns ns ns J4 TCLK rise and fall times — 1 ns J5 TMS input data setup time to TCLK rise
• JTAG
• CJTAG 112 — ns J6 TDI input data setup time to TCLK rise 8 — ns J7 TMS input data hold time after TCLK rise
• JTAG
• CJTAG 3.4 3.4 — ns J8 TDI input data hold time after TCLK rise 3.4 — ns J9 TCLK low to TMS data valid
• JTAG
• CJTAG — 48 ns J10 TCLK low to TDO data valid — 48 ns J11 Output data hold/invalid time after clock edge1 — 3 ns 1. They are common for JTAG and CJTAG. J3 J3 J4 J4 TCLK (input)

Figure 6. Test clock input timing K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012. 28 Preliminary Freescale Semiconductor, Inc.

Figure 9. TRST timing

6.2 System modules

There are no specifications necessary for the device's system modules.

6.3 Clock modules

6.3.1 MCG specifications

Table 14. MCG specifications

4 MHz

Table continues on the next page... K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012. 30 Preliminary Freescale Semiconductor, Inc.

Table 14. MCG specifications (continued)

• f VCO = 48 MHz
• f VCO = 98 MHz 180 150 ps Jacc_fll FLL accumulated jitter of DCO output over a 1µs time window — TBD — ps tfll_acquire FLL target frequency acquisition time — — 1 ms 6 PLL0,1 fpll_ref PLL reference frequency range 8 — 16 MHz fvcoclk_2x VCO output frequency 180 — 360 MHz fvcoclk PLL output frequency 90 — 180 MHz fvcoclk_90 PLL quadrature output frequency 90 — 180 MHz Ipll PLL operating current (fast) — TBD — µA 7 Table continues on the next page... Peripheral operating requirements and behaviors K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012. Freescale Semiconductor, Inc. Preliminary 31

1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock
2. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=0.
3. The resulting system clock frequencies should not exceed their maximum specified values. The DCO frequency deviation

(Δfdco_t) over voltage and temperature should be considered.

1. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=1.
2. The resulting clock frequency must not exceed the maximum specified clock frequency of the device.
3. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed,

FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running.

1. Excludes any oscillator currents that are also consuming power while PLL is in operation.
2. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled
3. Accumulated jitter will depend on VCO frequency and VDIV.

6.3.2 Oscillator electrical specifications

This section provides the electrical characteristics of the module.

6.3.2.1 Oscillator DC electrical specifications

Table 15. Oscillator DC electrical specifications

• 32 kHz
• 4 MHz
• 8 MHz (RANGE=01)
• 16 MHz
• 24 MHz
• 32 MHz 500 200 300 950 1.2 1.5 nA μA μA μA mA mA Table continues on the next page... Peripheral operating requirements and behaviors K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012. 32 Preliminary Freescale Semiconductor, Inc.

Table 15. Oscillator DC electrical specifications (continued)

• 32 kHz
• 4 MHz
• 8 MHz (RANGE=01)
• 16 MHz
• 24 MHz
• 32 MHz 400 500 2.5 μA μA μA mA mA mA Cx EXTAL load capacitance — — — 2, 3 Cy XTAL load capacitance — — — 2, 3 RF Feedback resistor — low-frequency, low-power mode (HGO=0) — — — MΩ 2, 4 Feedback resistor — low-frequency, high-gain mode (HGO=1) — 10 — MΩ Feedback resistor — high-frequency, low-power mode (HGO=0) — — — MΩ Feedback resistor — high-frequency, high-gain mode (HGO=1) — 1 — MΩ RS Series resistor — low-frequency, low-power mode (HGO=0) — — — kΩ Series resistor — low-frequency, high-gain mode (HGO=1) — 200 — kΩ Series resistor — high-frequency, low-power mode (HGO=0) — — — kΩ Series resistor — high-frequency, high-gain mode (HGO=1) kΩ Vpp5 Peak-to-peak amplitude of oscillation (oscillator mode) — low-frequency, low-power mode (HGO=0) — 0.6 — V Peak-to-peak amplitude of oscillation (oscillator mode) — low-frequency, high-gain mode (HGO=1) — VDD — V Peak-to-peak amplitude of oscillation (oscillator mode) — high-frequency, low-power mode (HGO=0) — 0.6 — V Peak-to-peak amplitude of oscillation (oscillator mode) — high-frequency, high-gain mode (HGO=1) — VDD — V 1. VDD=3.3 V, Temperature =25 °C 2. See crystal or resonator manufacturer's recommendation 3. Cx,Cy can be provided by using either the integrated capacitors or by using external components. 4. When low power mode is selected, RF is integrated and must not be attached externally. Peripheral operating requirements and behaviors K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012. Freescale Semiconductor, Inc. Preliminary 33

1. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to any

6.3.2.2 Oscillator frequency specifications

Table 16. Oscillator frequency specifications

1. Frequencies less than 8 MHz are not in the PLL range.
2. Other frequency limits may apply when external clock is being used as a reference for the FLL or PLL.
3. When transitioning from FBE to FEI mode, restrict the frequency of the input clock so that, when it is divided by FRDIV, it

remains within the limits of the DCO input clock frequency.

1. Proper PC board layout procedures must be followed to achieve specifications.
2. Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S register

This section describes the module electrical characteristics. Table 17. 32kHz oscillator DC electrical specifications Table continues on the next page... K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012. 34 Preliminary Freescale Semiconductor, Inc.

Table 17. 32kHz oscillator DC electrical specifications (continued)

1. The EXTAL32 and XTAL32 pins should only be connected to required oscillator components and must not be connected to

Table 18. 32kHz oscillator frequency specifications

1. Proper PC board layout procedures must be followed to achieve specifications.

6.4 Memories and memory interfaces

6.4.1 Flash (FTFE) electrical specifications

This section describes the electrical characteristics of the FTFE module.

6.4.1.1 Flash timing specifications — program and erase

active and do not include command overhead. Table 19. NVM program/erase timing specifications

1. Maximum time based on expectations at cycling end-of-life.

K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.

6.4.1.2 Flash timing specifications — commands

Table 20. Flash command timing specifications

• control code 0x01
• control code 0x02
• control code 0x04
• control code 0x08 185 TBD TBD TBD TBD μs μs μs μs tpgmpart Program Partition for EEPROM execution time — TBD TBD ms tsetram64k tsetram128k tsetram256k tsetram512k Set FlexRAM Function execution time:
• 64 KB EEPROM backup
• 128 KB EEPROM backup
• 256 KB EEPROM backup
• 512 KB EEPROM backup TBD TBD TBD TBD TBD TBD TBD TBD ms ms ms ms teewr8bers Byte-write to erased FlexRAM location execution time — 100 TBD μs 3 teewr8b64k teewr8b128k teewr8b256k teewr8b512k Byte-write to FlexRAM execution time:
• 64 KB EEPROM backup
• 128 KB EEPROM backup
• 256 KB EEPROM backup
• 512 KB EEPROM backup TBD TBD TBD TBD TBD TBD TBD TBD ms ms ms ms teewr16bers 16-bit write to erased FlexRAM location execution time — 100 TBD μs Table continues on the next page... Peripheral operating requirements and behaviors K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012. 36 Preliminary Freescale Semiconductor, Inc.

Table 20. Flash command timing specifications (continued)

• 64 KB EEPROM backup
• 128 KB EEPROM backup
• 256 KB EEPROM backup
• 512 KB EEPROM backup TBD TBD TBD TBD TBD TBD TBD TBD ms ms ms ms teewr32bers 32-bit write to erased FlexRAM location execution time — 200 TBD μs teewr32b64k teewr32b128k teewr32b256k teewr32b512k 32-bit-write to FlexRAM execution time:
• 64 KB EEPROM backup
• 128 KB EEPROM backup
• 256 KB EEPROM backup
• 512 KB EEPROM backup TBD TBD TBD TBD TBD TBD TBD TBD ms ms ms ms 1. Assumes 25MHz flash clock frequency. 2. Maximum times for erase parameters based on expectations at cycling end-of-life. 3. For byte-writes to an erased FlexRAM location, the aligned word containing the byte must be erased.

6.4.1.3 Flash (FTFE) current and power specfications

Table 21. Flash (FTFE) current and power specfications

6.4.1.4 Reliability specifications

Table 22. NVM reliability specifications Table continues on the next page... K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.

Table 22. NVM reliability specifications (continued)

• EEPROM backup to FlexRAM ratio = 16
• EEPROM backup to FlexRAM ratio = 128
• EEPROM backup to FlexRAM ratio = 512
• EEPROM backup to FlexRAM ratio = 4096
• EEPROM backup to FlexRAM ratio = 32,768 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD writes writes writes writes writes 1. Typical data retention values are based on measured response accelerated at high temperature and derated to a constant 25°C profile. Engineering Bulletin EB618 does not apply to this technology. 2. Data retention is based on Tjavg = 55°C (temperature profile over the lifetime of the application). 3. Cycling endurance represents number of program/erase cycles at -40°C ≤ Tj ≤ 125°C. 4. Write endurance represents the number of writes to each FlexRAM location at -40°C ≤Tj ≤ 125°C influenced by the cycling endurance of the FlexNVM (same value as data flash) and the allocated EEPROM backup per subsystem. Minimum and typical values assume all byte-writes to FlexRAM.

6.4.1.5 Write endurance to FlexRAM for EEPROM

6.4.2 EzPort Switching Specifications

Table 23. EzPort switching specifications Table continues on the next page... K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012. 38 Preliminary Freescale Semiconductor, Inc.

Table 23. EzPort switching specifications (continued) Figure 10. EzPort Timing Diagram

6.4.3 NFC specifications

memory devices. This section describes the timing parameters of the NFC.

• T H is the flash clock high time and
• T L is flash clock low time, which are defined as: input clockT SCALER=NFCT = HTLT + The SCALER value is derived from the fractional divider specified in the SIM's CLKDIV4 register: SCALER = SIM_CLKDIV4[NFCFRAC] + 1 SIM_CLKDIV4[NFCDIV] + 1 Peripheral operating requirements and behaviors K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012. Freescale Semiconductor, Inc. Preliminary 39

For example, if SCALER is 0.2, then TH = TL = TNFC/2. However, if SCALER is 0.667, then TL = 2/3 x TNFC and TH = 1/3 x TNFC. Table 24. NFC specifications Table continues on the next page... K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012. 40 Preliminary Freescale Semiconductor, Inc.

Figure 14. Read data latch cycle timing in non-fast mode Figure 15. Read data latch cycle timing in fast mode

6.4.4 DDR controller specifications

DDR memory bus. All timing numbers are relative to the DQS byte lanes. Table 25. DDR controller — AC timing specifications

• DDR1
• DDR2
• LPDDR 83.3 1251 150 150 150 MHz MHz MHz Table continues on the next page... Peripheral operating requirements and behaviors K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012. 42 Preliminary Freescale Semiconductor, Inc.

Table 25. DDR controller — AC timing specifications (continued)

• DDR1
• DDR2
• LPDDR 6.6 6.6 6.6 ns ns ns VOX-AC DDRCK AC differential cross point voltage
• DDR1
• DDR2
• LPDDR 0.5 x VDD_DDR – 0.2 V 0.5 x VDD_DDR – 0.125 V 0.4 x VDD_DDR 0.5 x VDD_DDR + 0.2 V 0.5 x VDD_DDR + 0.125 V 0.4 x VDD_DDR V V V tDDRCKH Pulse width high 0.45 0.55 tDDRCK 3 tDDRCKL Pulse width low 0.45 0.55 tDDRCK 3 tCMV Address, DDR_CKE, DDR_CAS, DDR_RAS, DDR_WE, DDR_CSn — output valid 0.5 x tDDRCK – — ns 4 tCMH Address, DDR_CKE, DDR_CAS, DDR_RAS, DDR_WE, DDR_CSn — output hold 0.5 x tDDRCK – — ns tDQSS Write command to first DQS latching transition WL – 0.2 x tDDRCK WL + 0.2 x tDDRCK ns tQS Data and data mask output setup (DQ→DQS) relative to DQS (DDR write mode) 0.25 x tDDRCK – 1 — ns 5, 6 tQH Data and data mask output hold (DQS→DQ) relative to DQS (DDR write mode) 0.25 x tDDRCK – 1 — ns 7 tDQSQ DQS-DQ skew for DQS and associated DQ signals – (0.25 x tDDRCK – 1) 0.25 x tDDRCK – 1 ns 8 1. This is minimum frequency of operation according to JEDEC DDR2 specification. 2. DDR data rate = 2 x DDR clock frequency 3. Pulse width high plus pulse width low cannot exceed min and max clock period. 4. Command output valid should be 1/2 the memory bus clock (tDDRCK) plus some minor adjustments for process, temperature, and voltage variations. 5. This specification relates to the required input setup time of DDR memories. The microprocessor's output setup should be larger than the input setup of the DDR memories. If it is not larger, then the input setup on the memory is in violation. DDR_DQ[15:8] is relative to DDR_DQS[1]; DDR_DQ[7:0] is relative to DDR_DQS[0]. 6. The first data beat is valid before the first rising edge of DQS and after the DQS write preamble. The remaining data beats are valid for each subsequent DQS edge. 7. This specification relates to the required hold time of DDR memories. DDR_DQ[15:8] is relative to DDR_DQS[1]; DDR_DQ[7:0] is relative to DDR_DQS[0] 8. Data input skew is derived from each DQS clock edge. It begins with a DQS transition and ends when the last data line becomes valid. This input skew must include DDR memory output skew and system level board skew (due to routing or other factors). Peripheral operating requirements and behaviors K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012. Freescale Semiconductor, Inc. Preliminary 43

Figure 16. DDR write timing K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012. 44 Preliminary Freescale Semiconductor, Inc.

Figure 17. DDR read timing Figure 18. DDR read timing, DQ vs. DQS

6.4.5 Flexbus Switching Specifications

the same as the internal system bus frequency or an integer divider of that frequency. K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.

Table 26. Flexbus limited voltage range switching specifications

1. Specification is valid for all FB_AD[31:0], FB_BE/BWEn, FB_CSn, FB_OE, FB_R/W,FB_TBST, FB_TSIZ[1:0], FB_ALE,
2. Specification is valid for all FB_AD[31:0] and FB_TA.

Table 27. Flexbus full voltage range switching specifications

1. Specification is valid for all FB_AD[31:0], FB_BE/BWEn, FB_CSn, FB_OE, FB_R/W,FB_TBST, FB_TSIZ[1:0], FB_ALE,
2. Specification is valid for all FB_AD[31:0] and FB_TA.

K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012. 46 Preliminary Freescale Semiconductor, Inc.

Figure 19. FlexBus read timing diagram K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.

Figure 20. FlexBus write timing diagram

6.5 Security and integrity modules

6.5.1 DryIce Tamper Electrical Specifications

Table 28. DryIce Tamper Electrical Specifications Table continues on the next page... K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012. 48 Preliminary Freescale Semiconductor, Inc.

Table 28. DryIce Tamper Electrical Specifications (continued)

• clock tamper enabled
• clock and voltage tamper enabled
• clock, voltage and temperature tamper enabled 0.9 1.01 1.35 TBD TBD TBD μA μA μA EXTAL32 input clock 32.768 kHz 1 Low Voltage Detect
• assertion
• negation 1.55 1.7 1.60 1.75 1.65 1.8 V V High Voltage Detect assertion 3.65 3.7 3.75 V Voltage Tamper Detect operational temperature
• no false alarms
• with possible false alarms -50 -60 150 160 Temperature Tamper Detect assertion
• low temperature detect
• high temperature detect -55 110 -45 130 Temperature Tamper Detect operational voltage
• no false alarms
• with possible false alarms 1.6 < 1.5 3.7 > 3.8 V V Clock Tamper Detect assertion
• low frequency
• high frequency
• delay after loss of clock kHz kHz ms Clock Tamper Detect operational temperature
• no false alarms
• with possible false alarms -50 -60 150 160 Clock Tamper Detect operational voltage
• no false alarms
• with possible false alarms 1.6 < 1.5 3.7 > 3.8 V V 1. EXTAL32 oscillator must be enabled before enabling DryIce tamper detect. 2. Temperature tamper detector assertion/negation is refreshed each 28 EXTAL32 clock cycles. 3. Clock tamper detector assertion/negation is refreshed each 28 EXTAL32 clock cycles.

6.6 Analog

K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.

6.6.1 ADC electrical specifications

differential pins ADCx_DP0, ADCx_DM0. Table 29. 16-bit ADC operating conditions

1.13 VDDA VDDA V

• 16 bit modes
• 8/10/12 bit modes pF RADIN Input resistance — 2 5 kΩ RAS Analog source resistance 13/12 bit modes fADCK < 4MHz kΩ fADCK ADC conversion clock frequency ≤ 13 bit modes 1.0 18.0 MHz fADCK ADC conversion clock frequency 16 bit modes 2.0 12.0 MHz Table continues on the next page... Peripheral operating requirements and behaviors K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012. 50 Preliminary Freescale Semiconductor, Inc.

Table 29. 16-bit ADC operating conditions (continued)

1. Typical values assume VDDA = 3.0 V, Temp = 25°C, fADCK = 1.0 MHz unless otherwise stated. Typical values are for

reference only and are not tested in production.

1. This resistance is external to MCU. The analog source resistance should be kept as low as possible in order to achieve the

CAS time constant should be kept to <1ns.

1. To use the maximum ADC conversion clock frequency, the ADHSC bit should be set and the ADLPC bit should be clear.
2. For guidelines and examples of conversion rate calculation, download the ADC calculator tool: http://cache.freescale.com/

Figure 21. ADC input impedance equivalency diagram K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.

Table 30. 16-bit ADC characteristics (V REFH = VDDA, VREFL = VSSA)

• ADLPC=1, ADHSC=0
• ADLPC=1, ADHSC=1
• ADLPC=0, ADHSC=0
• ADLPC=0, ADHSC=1 1.2 3.0 2.4 4.4 2.4 4.0 5.2 6.2 3.9 7.3 6.1 9.5 MHz MHz MHz MHz tADACK = 1/ fADACK Sample Time See Reference Manual chapter for sample times TUE Total unadjusted error
• 12 bit modes
• <12 bit modes ±1.4 ±6.8 ±2.1 LSB4 5 DNL Differential non- linearity
• 12 bit modes
• <12 bit modes ±0.7 ±0.2 -1.1 to +1.9 -0.3 to 0.5 LSB4 5 INL Integral non- linearity
• 12 bit modes
• <12 bit modes ±1.0 ±0.5 -2.7 to +1.9 -0.7 to +0.5 LSB4 5 EFS Full-scale error • 12 bit modes
• <12 bit modes -1.4 -5.4 -1.8 LSB4 VADIN = VDDA EQ Quantization error
• 16 bit modes
• ≤13 bit modes -1 to 0 ±0.5 LSB4 ENOB Effective number of bits 16 bit differential mode
• Avg=32
• Avg=4 16 bit single-ended mode
• Avg=32
• Avg=4 12.8 11.9 12.2 11.4 14.5 13.8 13.9 13.1 bits bits bits bits SINAD Signal-to-noise plus distortion See ENOB 6.02 × ENOB + 1.76 dB THD Total harmonic distortion 16 bit differential mode
• Avg=32 16 bit single-ended mode
• Avg=32 –94 -85 dB dB Table continues on the next page... Peripheral operating requirements and behaviors K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012. 52 Preliminary Freescale Semiconductor, Inc.

Table 30. 16-bit ADC characteristics (V REFH = VDDA, VREFL = VSSA) (continued)

• Avg=32 16 bit single-ended mode
• Avg=32 dB dB EIL Input leakage error IIn × RAS mV IIn = leakage current (refer to the MCU's voltage and current operating ratings) Temp sensor slope VTEMP25 Temp sensor voltage 25°C — 719 — mV 1. All accuracy numbers assume the ADC is calibrated with VREFH = VDDA 2. Typical values assume VDDA = 3.0 V, Temp = 25°C, fADCK = 2.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 3. The ADC supply current depends on the ADC conversion clock speed, conversion rate and the ADLPC bit (low power). For lowest power operation the ADLPC bit should be set, the HSC bit should be clear with 1MHz ADC conversion clock speed. 4. 1 LSB = (VREFH - VREFL)/2N 5. ADC conversion clock <16MHz, Max hardware averaging (AVGE = %1, AVGS = %11) 6. Input data is 100 Hz sine wave. ADC conversion clock <12MHz. 7. Input data is 1 kHz sine wave. ADC conversion clock <12MHz. Peripheral operating requirements and behaviors K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012. Freescale Semiconductor, Inc. Preliminary 53

Table 31. 16-bit ADC with PGA operating conditions

1. Typical values assume VDDA = 3.0 V, Temp = 25°C, fADCK = 6 MHz unless otherwise stated. Typical values are for

reference only and are not tested in production.

1. ADC must be configured to use the internal voltage reference (VREF_OUT)
2. PGA reference is internally connected to the VREF_OUT pin. If the user wishes to drive VREF_OUT with a voltage other

than the output of the VREF module, the VREF module must be disabled.

1. For single ended configurations the input impedance of the driven input is RPGAD/2
2. The analog source resistance (RAS), external to MCU, should be kept as minimum as possible. Increased RAS causes drop

in PGA gain without affecting other performances. This is not dependent on ADC clock frequency.

1. The minimum sampling time is dependent on input signal frequency and ADC mode of operation. A minimum of 1.25µs
2. ADC clock = 18 MHz, ADLSMP = 1, ADLST = 00, ADHSC = 1
3. ADC clock = 12 MHz, ADLSMP = 1, ADLST = 01, ADHSC = 1

K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.

Table 32. 16-bit ADC with PGA characteristics

• PGAG=1
• PGAG=2
• PGAG=3
• PGAG=4
• PGAG=5
• PGAG=6 0.95 1.9 3.8 7.6 15.2 30.0 58.8 31.6 63.3 1.05 2.1 4.2 8.4 16.6 33.2 67.8 RAS < 100Ω BW Input signal bandwidth
• 16-bit modes
• < 16-bit modes kHz kHz PSRR Power supply rejection ratio Gain=1 — -84 — dB VDDA= 3V ±100mV, fVDDA= 50Hz, 60Hz CMRR Common mode rejection ratio
• Gain=1
• Gain=64 -84 -85 dB dB VCM= 500mVpp, fVCM= 50Hz, 100Hz VOFS Input offset voltage
• Chopping disabled (ADC_PGA[PGACHPb] =1)
• Chopping enabled (ADC_PGA[PGACHPb] =0) 2.4 0.2 TBD mV mV Output offset = VOFS*(Gain+1) TGSW Gain switching settling time — — 10 µs 5 dG/dT Gain drift over temperature
• Gain=1
• Gain=64 TBD TBD TBD TBD ppm/°C ppm/°C 0 to 50°C dVOFS/dT Offset drift over temperature Gain=1 — TBD TBD ppm/°C 0 to 50°C, ADC Averaging=32 dG/dVDDA Gain drift over supply voltage
• Gain=1
• Gain=64 TBD TBD TBD TBD %/V %/V VDDA from 1.71 to 3.6V Table continues on the next page... Peripheral operating requirements and behaviors K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012. 56 Preliminary Freescale Semiconductor, Inc.

Table 32. 16-bit ADC with PGA characteristics (continued)

• Gain=1
• Gain=64 dB dB 16-bit differential mode, Average=32 THD Total harmonic distortion
• Gain=1
• Gain=64 100 dB dB 16-bit differential mode, Average=32, fin=100Hz SFDR Spurious free dynamic range
• Gain=1
• Gain=64 105 dB dB 16-bit differential mode, Average=32, fin=100Hz ENOB Effective number of bits
• Gain=1, Average=4
• Gain=1, Average=8
• Gain=64, Average=4
• Gain=64, Average=8
• Gain=1, Average=32
• Gain=2, Average=32
• Gain=4, Average=32
• Gain=8, Average=32
• Gain=16, Average=32
• Gain=32, Average=32
• Gain=64, Average=32 11.6 TBD 7.2 TBD 12.8 11.0 7.9 7.3 6.8 6.8 7.5 13.4 12.7 9.6 8.7 14.5 14.3 13.8 13.1 12.5 11.5 10.6 bits bits bits bits bits bits bits bits bits bits bits 16-bit differential mode,fin=100H z SINAD Signal-to-noise plus distortion ratio See ENOB 6.02 × ENOB + 1.76 dB 1. Typical values assume VDDA =3.0V, Temp=25°C, fADCK=6MHz unless otherwise stated. 2. This current is a PGA module adder, in addition to and ADC conversion currents. 3. Between IN+ and IN-. The PGA draws a DC current from the input terminals. The magnitude of the DC current is a strong function of input common mode voltage (VCM) and the PGA gain. 4. Gain = 2PGAG 5. After changing the PGA gain setting, a minimum of 2 ADC+PGA conversions should be ignored. Peripheral operating requirements and behaviors K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012. Freescale Semiconductor, Inc. Preliminary 57

1. Limit the input signal swing so that the PGA does not saturate during operation. Input signal swing is dependent on the

PGA reference voltage and gain setting.

6.6.2 CMP and 6-bit DAC electrical specifications

Table 33. Comparator and 6-bit DAC electrical specifications

• CR0[HYSTCTR] = 00
• CR0[HYSTCTR] = 01
• CR0[HYSTCTR] = 10
• CR0[HYSTCTR] = 11 mV mV mV mV VCMPOh Output high VDD – 0.5 — — V VCMPOl Output low — — 0.5 V tDHS Propagation delay, high-speed mode (EN=1, PMODE=1) 20 50 200 ns tDLS Propagation delay, low-speed mode (EN=1, PMODE=0) 80 250 600 ns Analog comparator initialization delay2 — — 40 μs IDAC6b 6-bit DAC current adder (enabled) — 7 — μA INL 6-bit DAC integral non-linearity –0.5 — 0.5 LSB3 DNL 6-bit DAC differential non-linearity –0.3 — 0.3 LSB 1. Typical hysteresis is measured with input voltage range limited to 0.6 to VDD-0.6V. 2. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to DACEN, VRSEL, PSEL, MSEL, VOSEL) and the comparator output settling to a stable level. 3. 1 LSB = Vreference/64 Peripheral operating requirements and behaviors K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012. 58 Preliminary Freescale Semiconductor, Inc.

Figure 24. Typical hysteresis vs. Vin level (VDD=3.3V, PMODE=0) K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.

Figure 25. Typical hysteresis vs. Vin level (VDD=3.3V, PMODE=1) Table 34. 12-bit DAC operating requirements

1. The DAC reference can be selected to be VDDA or the voltage output of the VREF module (VREF_OUT)
2. A small load capacitance (47 pF) can improve the bandwidth performance of the DAC

K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012. 60 Preliminary Freescale Semiconductor, Inc.

Table 35. 12-bit DAC operating behaviors

• High power (SP HP)
• Low power (SP LP) 1.2 0.05 1.7 0.12 V/μs CT Channel to channel cross talk — — -80 dB BW 3dB bandwidth
• High power (SP HP)
• Low power (SP LP) 550 kHz 1. Settling within ±1 LSB 2. The INL is measured for 0+100mV to VDACR−100 mV 3. The DNL is measured for 0+100 mV to VDACR−100 mV 4. The DNL is measured for 0+100mV to VDACR−100 mV with VDDA > 2.4V 5. Calculated by a best fit curve from VSS+100 mV to VDACR−100 mV Peripheral operating requirements and behaviors K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012. Freescale Semiconductor, Inc. Preliminary 61

1. VDDA = 3.0V, reference select set for VDDA (DACx_CO:DACRFS = 1), high power mode(DACx_C0:LPEN = 0), DAC set

Figure 26. Typical INL error vs. digital code K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012. 62 Preliminary Freescale Semiconductor, Inc.

Figure 27. Offset at half scale vs. temperature

6.6.4 Voltage reference electrical specifications

Table 36. VREF full-range operating requirements

1. CL must be connected to VREF_OUT if the VREF_OUT functionality is being used for either an internal or external
2. The load capacitance should not exceed +/-25% of the nominal specified CL value over the operating temperature range of

K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.

Table 37. VREF full-range operating behaviors

• current = + 1.0 mA
• current = - 1.0 mA mV 1, 2 Tstup Buffer startup time — — 100 µs Vvdrift Voltage drift (Vmax -Vmin across the full voltage range) — 2 — mV 1 1. See the chip's Reference Manual for the appropriate settings of the VREF Status and Control register. 2. Load regulation voltage is the difference between the VREF_OUT voltage with no load vs. voltage with defined load

Table 38. VREF limited-range operating requirements Table 39. VREF limited-range operating behaviors

6.7 Timers

See General switching specifications.

6.8 Communication interfaces

K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012. 64 Preliminary Freescale Semiconductor, Inc.

6.8.1 Ethernet switching specifications

appropriately to arrive at timing specs/constraints for the physical interface.

6.8.1.1 MII signal switching specifications

Table 40. MII signal switching specifications Figure 28. MII transmit signal timing diagram K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.

Figure 29. MII receive signal timing diagram

6.8.1.2 RMII signal switching specifications

Table 41. RMII signal switching specifications

6.8.2 USB electrical specifications

standards, visit http://www.usb.org. K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012. 66 Preliminary Freescale Semiconductor, Inc.

6.8.3 USB DCD electrical specifications

Table 42. USB DCD electrical specifications

6.8.4 USB VREG electrical specifications

Table 43. USB VREG electrical specifications

• VREGIN = 5.0 V and temperature=25C
• Across operating voltage and temperature 650 nA μA ILOADrun Maximum load current — Run mode — — 120 mA ILOADstby Maximum load current — Standby mode — — 1 mA VReg33out Regulator output voltage — Input supply (VREGIN) > 3.6 V
• Run mode
• Standby mode 2.1 3.3 2.8 3.6 3.6 V V VReg33out Regulator output voltage — Input supply (VREGIN) < 3.6 V, pass-through mode 2.1 — 3.6 V 2 COUT External output capacitor 1.76 2.2 8.16 μF ESR External output capacitor equivalent series resistance 1 — 100 mΩ ILIM Short circuit current — 290 — mA 1. Typical values assume VREGIN = 5.0 V, Temp = 25 °C unless otherwise stated. 2. Operating in pass-through mode: regulator output voltage equal to the input voltage minus a drop proportional to ILoad. Peripheral operating requirements and behaviors K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012. Freescale Semiconductor, Inc. Preliminary 67

6.8.5 ULPI timing specifications

measured with respect to the clock as seen at the USB_CLKIN pin. Table 44. ULPI timing specifications Figure 30. ULPI timing diagram K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012. 68 Preliminary Freescale Semiconductor, Inc.

6.8.6 CAN switching specifications

See General switching specifications.

6.8.7 DSPI switching specifications (limited voltage range)

used for communicating with slower peripheral devices. Table 45. Master mode DSPI timing (limited voltage range)

1. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
2. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].

Figure 31. DSPI classic SPI timing — master mode K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.

Table 46. Slave mode DSPI timing (limited voltage range) Figure 32. DSPI classic SPI timing — slave mode

6.8.8 DSPI switching specifications (full voltage range)

used for communicating with slower peripheral devices. Table 47. Master mode DSPI timing (full voltage range) Table continues on the next page... K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012. 70 Preliminary Freescale Semiconductor, Inc.

Table 47. Master mode DSPI timing (full voltage range) (continued)

1. The DSPI module can operate across the entire operating voltage for the processor, but to run across the full voltage

range the maximum frequency of operation is reduced.

1. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
2. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].

Figure 33. DSPI classic SPI timing — master mode Table 48. Slave mode DSPI timing (full voltage range) Table continues on the next page... K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.

Table 48. Slave mode DSPI timing (full voltage range) (continued) Figure 34. DSPI classic SPI timing — slave mode

6.8.9 I2C switching specifications

See General switching specifications.

6.8.10 UART switching specifications

See General switching specifications.

6.8.11 SDHC specifications

appropriately to arrive at timing specs/constraints for the physical interface. Table 49. SDHC switching specifications Table continues on the next page... K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012. 72 Preliminary Freescale Semiconductor, Inc.

Figure 35. SDHC timing

6.8.12 I2S/SAI Switching Specifications

K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.

frame sync (FS) signal shown in the following figures. Table 50. I2S/SAI master mode timing

1. This parameter is limited in VLPx modes.
2. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear

Figure 36. I2S/SAI timing — master modes K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012. 74 Preliminary Freescale Semiconductor, Inc.

Table 51. I2S/SAI slave mode timing

1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear

Figure 37. I2S/SAI timing — slave modes

6.9 Human-machine interfaces (HMI)

K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.

6.9.1 TSI electrical specifications

Table 52. TSI electrical specifications

• 1uA setting (REFCHRG=0)
• 32uA setting (REFCHRG=31) 1.133 1.5 μA 2, 3 IELE Electrode oscillator current source base current
• 1uA setting (EXTCHRG=0)
• 32uA setting (EXTCHRG=31) 1.133 1.5 μA 2, 4 Pres5 Electrode capacitance measurement precision — 8.3333 38.4 pF/count 5 Pres20 Electrode capacitance measurement precision — 8.3333 38.4 pF/count 6 Pres100 Electrode capacitance measurement precision — 8.3333 38.4 pF/count 7 MaxSens Maximum sensitivity 0.003 12.5 — fF/count 8 Res Resolution — — 16 bits TCon20 Response time @ 20 pF 8 15 25 μs 9 ITSI_RUN Current added in run mode — 55 — μA ITSI_LP Low power mode current adder — 1.3 TBD μA 10 1. The TSI module is functional with capacitance values outside this range. However, optimal performance is not guaranteed. 2. Fixed external capacitance of 20 pF. 3. The programmable current source value is generated by multiplying the SCANC[REFCHRG] value and the base current. 4. The programmable current source value is generated by multiplying the SCANC[EXTCHRG] value and the base current. 5. Measured with a 5 pF electrode, reference oscillator frequency of 10 MHz, PS = 128, NSCN = 8; Iext = 16. 6. Measured with a 20 pF electrode, reference oscillator frequency of 10 MHz, PS = 128, NSCN = 2; Iext = 16. 7. Measured with a 20 pF electrode, reference oscillator frequency of 10 MHz, PS = 16, NSCN = 3; Iext = 16. 8. Sensitivity defines the minimum capacitance change when a single count from the TSI module changes, it is equal to (Cref * Iext)/( Iref * PS * NSCN). Sensitivity depends on the configuration used. The typical value listed is based on the following configuration: Iext = 5 μA, EXTCHRG = 4, PS = 128, NSCN = 2, Iref = 16 μA, REFCHRG = 15, Cref = 1.0 pF. The minimum sensitivity describes the smallest possible capacitance that can be measured by a single count (this is the best sensitivity but is described as a minimum because it’s the smallest number). The minimum sensitivity parameter is based on the following configuration: Iext = 1 μA, EXTCHRG = 0, PS = 128, NSCN = 32, Iref = 32 μA, REFCHRG = 31, Cref= 0.5 pF 9. Time to do one complete measurement of the electrode. Sensitivity resolution of 0.0133 pF, PS = 0, NSCN = 0, 1 electrode, EXTCHRG = 15. 10. REFCHRG=0, EXTCHRG=4, PS=7, NSCN=0F, LPSCNITV=F, LPO is selected (1 kHz), and fixed external capacitance of 20 pF. Data is captured with an average of 7 periods window. Peripheral operating requirements and behaviors K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012. 76 Preliminary Freescale Semiconductor, Inc.

6.9.2 LCDC electrical specifications

Table 53. GLCD_LSCLK Timing GLCD_LSCLK and GLCD_D signals can also be programmed. Figure 38. GLCD_LSCLK to GLCD_D[17:0] Timing Figure 39. 4/8/12/16/18 Bit/Pixel TFT Color Mode Panel Timing K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.

Table 54. 4/8/12/16/18 Bit/Pixel TFT Color Mode Panel Timing

• Ts is the GLCD_LSCLK period. GLCD_VSYNC, GLCD_HSYNC, and GLCD_OE can be programmed as active high or active low. In the preceding figure, all 3 signals are active low. GLCD_LSCLK can be programmed to be deactivated during the GLCD_VSYNC pulse or the GLCD_OE deasserted period. In the preceding figure, GLCD_LSCLK is always active.
• XMAX is defined in number of pixels in one line. GLCD_LSCLK GLCD_D[15:0] GLCD_HSYNC T2T3 XMAX T4 TS GLCD_VSYNC

Figure 40. Non-TFT Mode Panel Timing Table 55. Non-TFT Mode Panel Timing Table continues on the next page... K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012. 78 Preliminary Freescale Semiconductor, Inc.

Table 55. Non-TFT Mode Panel Timing (continued) 4 and 8, T3 = 1, 2 and 4 Tpix respectively.

7 Dimensions

7.1 Obtaining package dimensions

Package dimensions are provided in package drawings.

8 Pinout

8.1 K70 Signal Multiplexing and Pin Assignments

for selecting which ALT functionality is available on each pin. K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.

Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort E2 PTE0 ADC1_SE4aADC1_SE4aPTE0 SPI1_PCS1UART1_TXSDHC0_D1GLCD_D0 I2C1_SDA RTC_CLKO UT F2 PTE1/ LLWU_P0 ADC1_SE5aADC1_SE5aPTE1/ LLWU_P0 SPI1_SOUTUART1_RXSDHC0_D0GLCD_D1 I2C1_SCL SPI1_SIN F3 PTE2/ LLWU_P1 ADC1_SE6aADC1_SE6aPTE2/ LLWU_P1 SPI1_SCKUART1_CTS SDHC0_DCL K GLCD_D2 G2 PTE3 ADC1_SE7aADC1_SE7aPTE3 SPI1_SIN UART1_RTS SDHC0_CM D GLCD_D3 SPI1_SOUT G7 VDD VDD VDD H7 VDDINT VDDINT VDDINT H8 VSS VSS VSS F1 PTF17 DISABLED PTF17 SPI2_SCKFTM0_CH4UART0_RXGLCD_D13 G1 PTF18 DISABLED PTF18 SPI2_SOUTFTM1_CH0UART0_TXGLCD_D14 G3 PTE4/ LLWU_P2 DISABLED PTE4/ LLWU_P2 SPI1_PCS0UART3_TXSDHC0_D3GLCD_D4 G4 PTE5 DISABLED PTE5 SPI1_PCS2UART3_RXSDHC0_D2GLCD_D5 FTM3_CH0 H2 PTE6 DISABLED PTE6 SPI1_PCS3UART3_CTS I2S0_MCLKGLCD_D6 FTM3_CH1USB_SOF_ OUT H1 PTF19 DISABLED PTF19 SPI2_SIN FTM1_CH1UART5_RXGLCD_D15 H5 PTF20 DISABLED PTF20 SPI2_PCS1FTM2_CH0UART5_TXGLCD_D16 H3 PTE7 DISABLED PTE7 UART3_RTS I2S0_RXD0GLCD_D7 FTM3_CH2 H4 PTE8 ADC2_SE16ADC2_SE16PTE8 I2S0_RXD1UART5_TXI2S0_RX_FSGLCD_D8 FTM3_CH3 J1 PTE9 ADC2_SE17ADC2_SE17PTE9 I2S0_TXD1UART5_RXI2S0_RX_BC LK GLCD_D9 FTM3_CH4 J2 PTE10 DISABLED PTE10 UART5_CTS I2S0_TXD0GLCD_D10FTM3_CH5 K1 PTE11 ADC3_SE16ADC3_SE16PTE11 UART5_RTS I2S0_TX_FSGLCD_D11FTM3_CH6 K3 PTE12 ADC3_SE17ADC3_SE17PTE12 I2S0_TX_BC LK GLCD_D12FTM3_CH7 G8 VDD VDD VDD H9 VSS VSS VSS J3 PTE16 ADC0_SE4aADC0_SE4aPTE16 SPI0_PCS0UART2_TXFTM_CLKIN FTM0_FLT3 K2 PTE17 ADC0_SE5aADC0_SE5aPTE17 SPI0_SCKUART2_RXFTM_CLKIN LPTMR0_AL L4 PTE18 ADC0_SE6aADC0_SE6aPTE18 SPI0_SOUTUART2_CTS I2C0_SDA M3 PTE19 ADC0_SE7aADC0_SE7aPTE19 SPI0_SIN UART2_RTS I2C0_SCL CMP3_OUT L2 VSS VSS VSS M1 USB0_DP USB0_DP USB0_DP M2 USB0_DM USB0_DM USB0_DM L1 VOUT33 VOUT33 VOUT33 Pinout K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012. 80 Preliminary Freescale Semiconductor, Inc.

Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort L3 VREGIN VREGIN VREGIN N1 PGA2_DP/ ADC2_DP0/ ADC3_DP3/ ADC0_DP1 PGA2_DP/ ADC2_DP0/ ADC3_DP3/ ADC0_DP1 PGA2_DP/ ADC2_DP0/ ADC3_DP3/ ADC0_DP1 N2 PGA2_DM/ ADC2_DM0/ ADC3_DM3/ ADC0_DM1 PGA2_DM/ ADC2_DM0/ ADC3_DM3/ ADC0_DM1 PGA2_DM/ ADC2_DM0/ ADC3_DM3/ ADC0_DM1 P1 PGA3_DP/ ADC3_DP0/ ADC2_DP3/ ADC1_DP1 PGA3_DP/ ADC3_DP0/ ADC2_DP3/ ADC1_DP1 PGA3_DP/ ADC3_DP0/ ADC2_DP3/ ADC1_DP1 P2 PGA3_DM/ ADC3_DM0/ ADC2_DM3/ ADC1_DM1 PGA3_DM/ ADC3_DM0/ ADC2_DM3/ ADC1_DM1 PGA3_DM/ ADC3_DM0/ ADC2_DM3/ ADC1_DM1 R1 PGA0_DP/ ADC0_DP0/ ADC1_DP3 PGA0_DP/ ADC0_DP0/ ADC1_DP3 PGA0_DP/ ADC0_DP0/ ADC1_DP3 R2 PGA0_DM/ ADC0_DM0/ ADC1_DM3 PGA0_DM/ ADC0_DM0/ ADC1_DM3 PGA0_DM/ ADC0_DM0/ ADC1_DM3 T1 PGA1_DP/ ADC1_DP0/ ADC0_DP3 PGA1_DP/ ADC1_DP0/ ADC0_DP3 PGA1_DP/ ADC1_DP0/ ADC0_DP3 T2 PGA1_DM/ ADC1_DM0/ ADC0_DM3 PGA1_DM/ ADC1_DM0/ ADC0_DM3 PGA1_DM/ ADC1_DM0/ ADC0_DM3 N5 VDDA VDDA VDDA P4 VREFH VREFH VREFH M4 VREFL VREFL VREFL N4 VSSA VSSA VSSA P3 ADC1_SE16/ CMP2_IN2/ ADC0_SE22 ADC1_SE16/ CMP2_IN2/ ADC0_SE22 ADC1_SE16/ CMP2_IN2/ ADC0_SE22 N3 ADC0_SE16/ CMP1_IN2/ ADC0_SE21 ADC0_SE16/ CMP1_IN2/ ADC0_SE21 ADC0_SE16/ CMP1_IN2/ ADC0_SE21 T3 VREF_OUT/ CMP1_IN5/ CMP0_IN5/ ADC1_SE18 VREF_OUT/ CMP1_IN5/ CMP0_IN5/ ADC1_SE18 VREF_OUT/ CMP1_IN5/ CMP0_IN5/ ADC1_SE18 R3 DAC0_OUT/ CMP1_IN3/ ADC0_SE23 DAC0_OUT/ CMP1_IN3/ ADC0_SE23 DAC0_OUT/ CMP1_IN3/ ADC0_SE23 R4 DAC1_OUT/ CMP0_IN4/ CMP2_IN3/ ADC1_SE23 DAC1_OUT/ CMP0_IN4/ CMP2_IN3/ ADC1_SE23 DAC1_OUT/ CMP0_IN4/ CMP2_IN3/ ADC1_SE23 Pinout K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012. Freescale Semiconductor, Inc. Preliminary 81

Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort M5 TAMPER0/ RTC_WAKE UP_B TAMPER0/ RTC_WAKE UP_B TAMPER0/ RTC_WAKE UP_B L5 TAMPER1 TAMPER1 TAMPER1 L6 TAMPER2 TAMPER2 TAMPER2 R5 TAMPER3 TAMPER3 TAMPER3 P6 TAMPER4 TAMPER4 TAMPER4 R6 TAMPER5 TAMPER5 TAMPER5 T6 XTAL32 XTAL32 XTAL32 T5 EXTAL32 EXTAL32 EXTAL32 P5 VBAT VBAT VBAT N6 TAMPER6 TAMPER6 TAMPER6 M6 TAMPER7 TAMPER7 TAMPER7 G9 VDD VDD VDD H10 VDDINT VDDINT VDDINT J8 VSS VSS VSS P7 PTE24 ADC0_SE17/ EXTAL1 ADC0_SE17/ EXTAL1 PTE24 CAN1_TX UART4_TXI2S1_TX_FSGLCD_D13EWM_OUT_ b I2S1_RXD1 R7 PTE25 ADC0_SE18/ XTAL1 ADC0_SE18/ XTAL1 PTE25 CAN1_RX UART4_RXI2S1_TX_BC LK GLCD_D14EWM_IN I2S1_TXD1 M7 PTE26 ADC3_SE5bADC3_SE5bPTE26 ENET_1588 _CLKIN UART4_CTS I2S1_TXD0GLCD_D15RTC_CLKO UT USB_CLKIN K7 PTE27 ADC3_SE4bADC3_SE4bPTE27 UART4_RTS I2S1_MCLKGLCD_D16 L7 PTE28 ADC3_SE7aADC3_SE7aPTE28 GLCD_D17 T7 PTA0 JTAG_TCLK/ SWD_CLK/ EZP_CLK TSI0_CH1 PTA0 UART0_CTS _b/ UART0_COL FTM0_CH5 JTAG_TCLK/ SWD_CLK EZP_CLK N8 PTA1 JTAG_TDI/ EZP_DI TSI0_CH2 PTA1 UART0_RXFTM0_CH6 JTAG_TDI EZP_DI T8 PTA2 JTAG_TDO/ TRACE_SW O/EZP_DO TSI0_CH3 PTA2 UART0_TXFTM0_CH7 JTAG_TDO/ TRACE_SW O EZP_DO P8 PTA3 JTAG_TMS/ SWD_DIO TSI0_CH4 PTA3 UART0_RTS FTM0_CH0 JTAG_TMS/ SWD_DIO R8 PTA4/ LLWU_P3 NMI_b/ EZP_CS_b TSI0_CH5 PTA4/ LLWU_P3 FTM0_CH1 NMI_b EZP_CS_b T12 PTA5 DISABLED PTA5 USB_CLKINFTM0_CH2RMII0_RXE MII0_RXER CMP2_OUTI2S0_TX_BC LK JTAG_TRST G10 VDD VDD VDD J9 VSS VSS VSS P9 PTF21 ADC3_SE6bADC3_SE6bPTF21 FTM2_CH1UART5_RTS GLCD_D17 Pinout K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012. 82 Preliminary Freescale Semiconductor, Inc.

Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort N9 PTF22 ADC3_SE7bADC3_SE7bPTF22 I2C0_SCL FTM1_CH0UART5_CTS GLCD_D18 R12 PTA6 ADC3_SE6aADC3_SE6aPTA6 ULPI_CLK FTM0_CH3I2S1_RXD0CLKOUT TRACE_CLK OUT P12 PTA7 ADC0_SE10ADC0_SE10PTA7 ULPI_DIR FTM0_CH4I2S1_RX_BC LK TRACE_D3 N12 PTA8 ADC0_SE11ADC0_SE11PTA8 ULPI_NXTFTM1_CH0I2S1_RX_FS FTM1_QD_P HA TRACE_D2 T13 PTA9 ADC3_SE5aADC3_SE5aPTA9 ULPI_STP FTM1_CH1MII0_RXD3 FTM1_QD_P HB TRACE_D1 P13 PTA10 ADC3_SE4aADC3_SE4aPTA10 ULPI_DATA FTM2_CH0MII0_RXD2 FTM2_QD_P HA TRACE_D0 R13 PTA11 ADC3_SE15ADC3_SE15PTA11 ULPI_DATA FTM2_CH1MII0_RXCLK FTM2_QD_P HB M10 PTA12 CMP2_IN0CMP2_IN0PTA12 CAN0_TX FTM1_CH0RMII0_RXD1 /MII0_RXD1 I2S0_TXD0FTM1_QD_P HA N10 PTA13/ LLWU_P4 CMP2_IN1CMP2_IN1PTA13/ LLWU_P4 CAN0_RX FTM1_CH1RMII0_RXD0 /MII0_RXD0 I2S0_TX_FSFTM1_QD_P HB R11 PTA14 CMP3_IN0CMP3_IN0PTA14 SPI0_PCS0UART0_TXRMII0_CRS_ DV/ MII0_RXDV I2S0_RX_BC LK I2S0_TXD1 P11 PTA15 CMP3_IN1CMP3_IN1PTA15 SPI0_SCKUART0_RXRMII0_TXEN /MII0_TXEN I2S0_RXD0 T14 VSS VSS VSS N11 PTA16 CMP3_IN2CMP3_IN2PTA16 SPI0_SOUTUART0_CTS _b/ UART0_COL RMII0_TXD0 /MII0_TXD0 I2S0_RX_FSI2S0_RXD1 T11 PTA17 ADC1_SE17ADC1_SE17PTA17 SPI0_SIN UART0_RTS RMII0_TXD1 /MII0_TXD1 I2S0_MCLK P10 PTF23 ADC3_SE10ADC3_SE10PTF23 I2C0_SDA FTM1_CH1 TRACE_CLK OUT GLCD_D19 R10 PTF24 ADC3_SE11ADC3_SE11PTF24 CAN1_RX FTM1_QD_P HA TRACE_D3GLCD_D20 R9 PTF25 ADC3_SE12ADC3_SE12PTF25 CAN1_TX FTM1_QD_P HB TRACE_D2GLCD_D21 T9 PTF26 ADC3_SE13ADC3_SE13PTF26 FTM2_QD_P HA TRACE_D1GLCD_D22 T10 PTF27 ADC3_SE14ADC3_SE14PTF27 FTM2_QD_P HB TRACE_D0GLCD_D23 J7 VDD VDD VDD K8 VSS VSS VSS T15 PTA18 EXTAL0 EXTAL0 PTA18 FTM0_FLT2FTM_CLKIN T16 PTA19 XTAL0 XTAL0 PTA19 FTM1_FLT0FTM_CLKIN LPTMR0_AL R16 RESET_b RESET_b RESET_b Pinout K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012. Freescale Semiconductor, Inc. Preliminary 83

Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort N13 PTA24 CMP3_IN4CMP3_IN4PTA24 ULPI_DATA MII0_TXD2 FB_A29 R14 PTA25 CMP3_IN5CMP3_IN5PTA25 ULPI_DATA MII0_TXCLK FB_A28 M13 PTA26 ADC2_SE15ADC2_SE15PTA26 ULPI_DATA MII0_TXD3 FB_A27 R15 PTA27 ADC2_SE14ADC2_SE14PTA27 ULPI_DATA MII0_CRS FB_A26 P14 PTA28 ADC2_SE13ADC2_SE13PTA28 ULPI_DATA MII0_TXER FB_A25 N14 PTA29 ADC2_SE12ADC2_SE12PTA29 ULPI_DATA MII0_COL FB_A24 P16 PTF0 ADC2_SE11ADC2_SE11PTF0 CAN0_TX FTM3_CH0 I2S1_RXD1 GLCD_PCLK L13 PTF1 ADC2_SE10ADC2_SE10PTF1 CAN0_RX FTM3_CH1 I2S1_RX_BC LK GLCD_DE M12 PTB0/ LLWU_P5 ADC0_SE8/ ADC1_SE8/ ADC2_SE8/ ADC3_SE8/ TSI0_CH0 ADC0_SE8/ ADC1_SE8/ ADC2_SE8/ ADC3_SE8/ TSI0_CH0 PTB0/ LLWU_P5 I2C0_SCL FTM1_CH0RMII0_MDIO /MII0_MDIO FTM1_QD_P HA M11 PTB1 ADC0_SE9/ ADC1_SE9/ ADC2_SE9/ ADC3_SE9/ TSI0_CH6 ADC0_SE9/ ADC1_SE9/ ADC2_SE9/ ADC3_SE9/ TSI0_CH6 PTB1 I2C0_SDA FTM1_CH1RMII0_MDC/ MII0_MDC FTM1_QD_P HB P15 PTB2 ADC0_SE12/ TSI0_CH7 ADC0_SE12/ TSI0_CH7 PTB2 I2C0_SCL UART0_RTS ENET0_158 8_TMR0 FTM0_FLT3 M14 PTB3 ADC0_SE13/ TSI0_CH8 ADC0_SE13/ TSI0_CH8 PTB3 I2C0_SDA UART0_CTS _b/ UART0_COL ENET0_158 8_TMR1 FTM0_FLT0 N15 PTB4 ADC1_SE10ADC1_SE10PTB4 GLCD_CON TRAST ENET0_158 8_TMR2 FTM1_FLT0 M15 PTB5 ADC1_SE11ADC1_SE11PTB5 ENET0_158 8_TMR3 FTM2_FLT0 L14 PTB6 ADC1_SE12ADC1_SE12PTB6 FB_AD23 L15 PTB7 ADC1_SE13ADC1_SE13PTB7 FB_AD22 K14 PTB8 DISABLED PTB8 UART3_RTS FB_AD21 K15 PTB9 DISABLED PTB9 SPI1_PCS1UART3_CTS FB_AD20 J13 PTB10 ADC1_SE14ADC1_SE14PTB10 SPI1_PCS0UART3_RXI2S1_TX_BC LK FB_AD19 FTM0_FLT1 J14 PTB11 ADC1_SE15ADC1_SE15PTB11 SPI1_SCKUART3_TXI2S1_TX_FSFB_AD18 FTM0_FLT2 K9 VSS VSS VSS J10 VDD VDD VDD N16 PTF2 ADC2_SE6aADC2_SE6aPTF2 I2C1_SCL FTM3_CH2 I2S1_RX_FS GLCD_HFS Pinout K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012. 84 Preliminary Freescale Semiconductor, Inc.

Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort M16 PTF3 ADC2_SE7aADC2_SE7aPTF3 I2C1_SDA FTM3_CH3 I2S1_RXD0 GLCD_VFS L16 PTF4 ADC2_SE4bADC2_SE4bPTF4 FTM3_CH4 I2S1_TXD0 GLCD_D0 J15 PTB16 TSI0_CH9 TSI0_CH9 PTB16 SPI1_SOUTUART0_RXI2S1_TXD0FB_AD17 EWM_IN H13 PTB17 TSI0_CH10TSI0_CH10PTB17 SPI1_SIN UART0_TXI2S1_TXD1FB_AD16 EWM_OUT_ b H14 PTB18 TSI0_CH11TSI0_CH11PTB18 CAN0_TX FTM2_CH0I2S0_TX_BC LK FB_AD15 FTM2_QD_P HA K16 PTF5 ADC2_SE5bADC2_SE5bPTF5 FTM3_CH5 I2S1_TX_FS GLCD_D1 J16 PTF6 ADC2_SE6bADC2_SE6bPTF6 FTM3_CH6 I2S1_TX_BC LK GLCD_D2 H15 PTB19 TSI0_CH12TSI0_CH12PTB19 CAN0_RX FTM2_CH1I2S0_TX_FSFB_OE_b FTM2_QD_P HB G13 PTB20 ADC2_SE4aADC2_SE4aPTB20 SPI2_PCS0 FB_AD31/ NFC_DATA1 CMP0_OUT G14 PTB21 ADC2_SE5aADC2_SE5aPTB21 SPI2_SCK FB_AD30/ NFC_DATA1 CMP1_OUT G15 PTB22 DISABLED PTB22 SPI2_SOUT FB_AD29/ NFC_DATA1 CMP2_OUT H16 PTB23 DISABLED PTB23 SPI2_SIN SPI0_PCS5 FB_AD28/ NFC_DATA1 CMP3_OUT G16 PTC0 ADC0_SE14/ TSI0_CH13 ADC0_SE14/ TSI0_CH13 PTC0 SPI0_PCS4PDB0_EXTR G FB_AD14/ NFC_DATA1 I2S0_TXD1 F13 PTC1/ LLWU_P6 ADC0_SE15/ TSI0_CH14 ADC0_SE15/ TSI0_CH14 PTC1/ LLWU_P6 SPI0_PCS3UART1_RTS FTM0_CH0FB_AD13/ NFC_DATA1 I2S0_TXD0 F14 PTC2 ADC0_SE4b/ CMP1_IN0/ TSI0_CH15 ADC0_SE4b/ CMP1_IN0/ TSI0_CH15 PTC2 SPI0_PCS2UART1_CTS FTM0_CH1FB_AD12/ NFC_DATA9 I2S0_TX_FS E13 PTC3/ LLWU_P7 CMP1_IN1CMP1_IN1PTC3/ LLWU_P7 SPI0_PCS1UART1_RXFTM0_CH2CLKOUT I2S0_TX_BC LK F15 PTF7 ADC2_SE7bADC2_SE7bPTF7 FTM3_CH7UART3_RXI2S1_TXD1 GLCD_D3 L9 VSS VSS VSS K10 VDD VDD VDD F16 PTF8 DISABLED PTF8 FTM3_FLT0UART3_TXI2S1_MCLK GLCD_D4 E14 PTC4/ LLWU_P8 DISABLED PTC4/ LLWU_P8 SPI0_PCS0UART1_TXFTM0_CH3FB_AD11/ NFC_DATA8 CMP1_OUTI2S1_TX_BC LK E15 PTC5/ LLWU_P9 DISABLED PTC5/ LLWU_P9 SPI0_SCKLPTMR0_AL I2S0_RXD0FB_AD10/ NFC_DATA7 CMP0_OUTI2S1_TX_FS F12 PTC6/ LLWU_P10 CMP0_IN0CMP0_IN0PTC6/ LLWU_P10 SPI0_SOUTPDB0_EXTR G I2S0_RX_BC LK FB_AD9/ NFC_DATA6 I2S0_MCLK G12 PTC7 CMP0_IN1CMP0_IN1PTC7 SPI0_SIN USB_SOF_ OUT I2S0_RX_FSFB_AD8/ NFC_DATA5 Pinout K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012. Freescale Semiconductor, Inc. Preliminary 85

Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort H12 PTC8 ADC1_SE4b/ CMP0_IN2 ADC1_SE4b/ CMP0_IN2 PTC8 FTM3_CH4I2S0_MCLKFB_AD7/ NFC_DATA4 F11 PTC9 ADC1_SE5b/ CMP0_IN3 ADC1_SE5b/ CMP0_IN3 PTC9 FTM3_CH5I2S0_RX_BC LK FB_AD6/ NFC_DATA3 FTM2_FLT0 G11 PTC10 ADC1_SE6bADC1_SE6bPTC10 I2C1_SCL FTM3_CH6I2S0_RX_FSFB_AD5/ NFC_DATA2 I2S1_MCLK H11 PTC11/ LLWU_P11 ADC1_SE7bADC1_SE7bPTC11/ LLWU_P11 I2C1_SDA FTM3_CH7I2S0_RXD1FB_RW_b/ NFC_WE J12 PTC12 DISABLED PTC12 UART4_RTS FB_AD27 FTM3_FLT0 K13 PTC13 DISABLED PTC13 UART4_CTS FB_AD26 J11 PTC14 DISABLED PTC14 UART4_RX FB_AD25 K12 PTF9 CMP2_IN4CMP2_IN4PTF9 UART3_RTS GLCD_D5 L12 PTF10 CMP2_IN5CMP2_IN5PTF10 UART3_CTS GLCD_D6 F10 PTC15 DISABLED PTC15 UART4_TX FB_AD24 N7 VSS VSS VSS L10 VDD VDD VDD K11 PTF11 DISABLED PTF11 UART2_RTS GLCD_D7 L11 PTF12 DISABLED PTF12 UART2_CTS GLCD_D8 F9 PTC16 DISABLED PTC16 CAN1_RX UART3_RXENET0_158 8_TMR0 FB_CS5_b/ FB_TSIZ1/ FB_BE23_16 NFC_RB E9 PTC17 DISABLED PTC17 CAN1_TX UART3_TXENET0_158 8_TMR1 FB_CS4_b/ FB_TSIZ0/ FB_BE31_24 NFC_CE0_b M9 PTC18 DISABLED PTC18 UART3_RTS ENET0_158 8_TMR2 FB_TBST_b/ FB_CS2_b/ FB_BE15_8_ b NFC_CE1_b M8 PTC19 DISABLED PTC19 UART3_CTS ENET0_158 8_TMR3 FB_CS3_b/ FB_BE7_0_b FB_TA_b L8 PTD0/ LLWU_P12 DISABLED PTD0/ LLWU_P12 SPI0_PCS0UART2_RTS FTM3_CH0FB_ALE/ FB_CS1_b/ FB_TS_b I2S1_RXD1 F8 PTD1 ADC0_SE5bADC0_SE5bPTD1 SPI0_SCKUART2_CTS FTM3_CH1FB_CS0_bI2S1_RXD0 K6 PTD2/ LLWU_P13 DISABLED PTD2/ LLWU_P13 SPI0_SOUTUART2_RXFTM3_CH2FB_AD4 I2S1_RX_FS J6 PTD3 DISABLED PTD3 SPI0_SIN UART2_TXFTM3_CH3FB_AD3 I2S1_RX_BC LK Pinout K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012. 86 Preliminary Freescale Semiconductor, Inc.

Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort K5 PTD4/ LLWU_P14 DISABLED PTD4/ LLWU_P14 SPI0_PCS1UART0_RTS FTM0_CH4FB_AD2/ NFC_DATA1 EWM_IN J5 PTD5 ADC0_SE6bADC0_SE6bPTD5 SPI0_PCS2UART0_CTS _b/ UART0_COL FTM0_CH5FB_AD1/ NFC_DATA0 EWM_OUT_ b K4 PTD6/ LLWU_P15 ADC0_SE7bADC0_SE7bPTD6/ LLWU_P15 SPI0_PCS3UART0_RXFTM0_CH6FB_AD0 FTM0_FLT0 H6 PTF13 DISABLED PTF13 UART2_RX GLCD_D9 G6 PTF14 DISABLED PTF14 UART2_TX GLCD_D10 T4 VSS VSS VSS E7 PTD7 DISABLED PTD7 CMT_IRO UART0_TXFTM0_CH7 FTM0_FLT1 J4 PTD8 DISABLED PTD8 I2C0_SCL UART5_RX FB_A16/ NFC_CLE F7 PTD9 DISABLED PTD9 I2C0_SDA UART5_TX FB_A17/ NFC_ALE E6 PTD10 DISABLED PTD10 UART5_RTS FB_A18/ NFC_RE G5 PTD11 DISABLED PTD11 SPI2_PCS0UART5_CTS SDHC0_CLK IN FB_A19 GLCD_CON TRAST F5 PTD12 DISABLED PTD12 SPI2_SCKFTM3_FLT0SDHC0_D4 FB_A20 GLCD_PCLK F4 PTD13 DISABLED PTD13 SPI2_SOUT SDHC0_D5 FB_A21 GLCD_DE E5 PTD14 DISABLED PTD14 SPI2_SIN SDHC0_D6 FB_A22 GLCD_HFS E4 PTD15 DISABLED PTD15 SPI2_PCS1 SDHC0_D7 FB_A23 GLCD_VFS F6 PTF15 DISABLED PTF15 UART0_RTS GLCD_D11 E1 PTF16 DISABLED PTF16 SPI2_PCS0FTM0_CH3UART0_CTS _b/ UART0_COL GLCD_D12 B1 DDR_VDDDDR_VDD DDR_VDD A1 DDR_VSS DDR_VSS DDR_VSS D3 DDR_DQS1DISABLED DDR_DQS1 D1 DDR_DQ8DISABLED DDR_DQ8 C1 DDR_DQ9DISABLED DDR_DQ9 B5 DDR_VDDDDR_VDD DDR_VDD A5 DDR_VSS DDR_VSS DDR_VSS D5 DDR_VSS DDR_VSS DDR_VSS C2 DDR_DQ10DISABLED DDR_DQ10 B2 DDR_DQ11DISABLED DDR_DQ11 C3 DDR_DQ12DISABLED DDR_DQ12 B8 DDR_VDDDDR_VDD DDR_VDD A12 DDR_VSS DDR_VSS DDR_VSS C4 DDR_DQ13DISABLED DDR_DQ13 Pinout K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012. Freescale Semiconductor, Inc. Preliminary 87

Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort B3 DDR_DQ14DISABLED DDR_DQ14 A2 DDR_DQ15DISABLED DDR_DQ15 A3 DDR_DM1DISABLED DDR_DM1 E8 DDR_VSS DDR_VSS DDR_VSS B12 DDR_VDDDDR_VDD DDR_VDD A16 DDR_VSS DDR_VSS DDR_VSS C6 DDR_VREFDDR_VREF DDR_VREF C5 DDR_DQ0DISABLED DDR_DQ0 B4 DDR_DQ1DISABLED DDR_DQ1 A4 DDR_DQ2DISABLED DDR_DQ2 C16 DDR_VDDDDR_VDD DDR_VDD C7 DDR_VSS DDR_VSS DDR_VSS B6 DDR_DQ3DISABLED DDR_DQ3 D6 DDR_DQ4DISABLED DDR_DQ4 A6 DDR_DQ5DISABLED DDR_DQ5 A7 DDR_ODTDISABLED DDR_ODT E11 DDR_VSS DDR_VSS DDR_VSS D2 DDR_VDDDDR_VDD DDR_VDD C9 DDR_VSS DDR_VSS DDR_VSS B7 DDR_DQ6DISABLED DDR_DQ6 A8 DDR_DQ7DISABLED DDR_DQ7 C8 DDR_DQS0DISABLED DDR_DQS0 D9 DDR_DM0DISABLED DDR_DM0 D4 DDR_VDDDDR_VDD DDR_VDD C14 DDR_VSS DDR_VSS DDR_VSS A9 DDR_BA0 DISABLED DDR_BA0 B10 DDR_BA1 DISABLED DDR_BA1 B9 DDR_BA2 DISABLED DDR_BA2 A10 DDR_CKBDISABLED DDR_CKB A11 DDR_CK DISABLED DDR_CK D7 DDR_VDDDDR_VDD DDR_VDD D8 DDR_VSS DDR_VSS DDR_VSS D10 DDR_A0 DISABLED DDR_A0 C11 DDR_A1 DISABLED DDR_A1 B11 DDR_A2 DISABLED DDR_A2 C12 DDR_A3 DISABLED DDR_A3 E10 DDR_VDDDDR_VDD DDR_VDD D12 DDR_VSS DDR_VSS DDR_VSS C10 DDR_A4 DISABLED DDR_A4 A13 DDR_A5 DISABLED DDR_A5 Pinout K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012. 88 Preliminary Freescale Semiconductor, Inc.

Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort A14 DDR_A6 DISABLED DDR_A6 D11 DDR_A7 DISABLED DDR_A7 A15 DDR_A8 DISABLED DDR_A8 E12 DDR_VDDDDR_VDD DDR_VDD E3 DDR_VSS DDR_VSS DDR_VSS B16 DDR_CKEDISABLED DDR_CKE B15 DDR_A9 DISABLED DDR_A9 B13 DDR_A10 DISABLED DDR_A10 B14 DDR_A11 DISABLED DDR_A11 C15 DDR_A12 DISABLED DDR_A12 D16 DDR_A13 DISABLED DDR_A13 D15 DDR_A14 DISABLED DDR_A14 E16 DDR_RAS_ B DISABLED DDR_RAS_ B C13 DDR_CAS_ B DISABLED DDR_CAS_ B D14 DDR_CS_BDISABLED DDR_CS_B D13 DDR_WE_BDISABLED DDR_WE_B

8.2 K70 Pinouts

The below figure shows the pinout diagram for the devices supported by this document. Many signals may be multiplexed onto a single pin. To determine what signals can be used on which pin, see the previous section. Pinout K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012. Freescale Semiconductor, Inc. Preliminary 89

A DDR_VSS B DDR_VDD C DDR_DQ9 D DDR_DQ8 E PTF16 F PTF17 G PTF18 H PTF19 J PTE9 K PTE11 L VOUT33 M USB0_DP N PGA2_DP/ P PGA3_DP/ R PGA0_DP/ T PGA1_DP/ DDR_DQ15 DDR_DQ11 DDR_DQ10 DDR_VDD PTE0 PTE1/ PTE3 PTE6 PTE10 PTE17 VSS USB0_DM PGA2_DM/ PGA3_DM/ PGA0_DM/ PGA1_DM/ DDR_DM1 DDR_DQ14 DDR_DQ12 DDR_DQS1 DDR_VSS PTE2/ PTE4/ PTE7 PTE16 PTE12 VREGIN PTE19 ADC0_SE16/ ADC1_SE16/ DAC0_OUT/ VREF_OUT/ DDR_DQ2 DDR_DQ1 DDR_DQ13 DDR_VDD PTD15 PTD13 PTE5 PTE8 PTD8 PTD6/ PTE18 VREFL VSSA VREFH DAC1_OUT/ VSS DDR_VSS DDR_VDD DDR_DQ0 DDR_VSS PTD14 PTD12 PTD11 PTF20 PTD5 PTD4/ TAMPER1 TAMPER0/ VDDA VBAT TAMPER3 EXTAL32 DDR_DQ5 DDR_DQ3 DDR_VREF DDR_DQ4 PTD10 PTF15 PTF14 PTF13 PTD3 PTD2/ TAMPER2 TAMPER7 TAMPER6 TAMPER4 TAMPER5 XTAL32 DDR_ODT DDR_DQ6 DDR_VSS DDR_VDD PTD7 PTD9 VDD VDDINT VDD PTE27 PTE28 PTE26 VSS PTE24 PTE25 PTA0 DDR_DQ7 DDR_VDD DDR_DQS0 DDR_VSS DDR_VSS PTD1 VDD VSS VSS VSS PTD0/ PTC19 PTA1 PTA3 PTA4/ PTA2 DDR_BA0 DDR_BA2 DDR_VSS DDR_DM0 PTC17 PTC16 VDD VSS VSS VSS VSS PTC18 PTF22 PTF21 PTF25 PTF26 DDR_CKB DDR_BA1 DDR_A4 DDR_A0 DDR_VDD PTC15 VDD VDDINT VDD VDD VDD PTA12 PTA13/ PTF23 PTF24 PTF27 DDR_CK DDR_A2 DDR_A1 DDR_A7 DDR_VSS PTC9 PTC10 PTC11/ PTC14 PTF11 PTF12 PTB1 PTA16 PTA15 PTA14 PTA17 DDR_VSS DDR_VDD DDR_A3 DDR_VSS DDR_VDD PTC6/ PTC7 PTC8 PTC12 PTF9 PTF10 PTB0/ PTA8 PTA7 PTA6 PTA5 DDR_A5 DDR_A10 DDR_CAS_B DDR_WE_B PTC3/ PTC1/ PTB20 PTB17 PTB10 PTC13 PTF1 PTA26 PTA24 PTA10 PTA11 PTA9 DDR_A6 DDR_A11 DDR_VSS DDR_CS_B PTC4/ PTC2 PTB21 PTB18 PTB11 PTB8 PTB6 PTB3 PTA29 PTA28 PTA25 VSS DDR_A8 DDR_A9 DDR_A12 DDR_A14 PTC5/ PTF7 PTB22 PTB19 PTB16 PTB9 PTB7 PTB5 PTB4 PTB2 PTA27 PTA18 ADDR_VSS BDDR_CKE CDDR_VDD DDDR_A13 EDDR_RAS_B FPTF8 GPTC0 HPTB23 JPTF6 KPTF5 LPTF4 MPTF3 NPTF2 PPTF0 RRESET_b TPTA19 LLWU_P7 LLWU_P8 LLWU_P9 LLWU_P0 LLWU_P1 LLWU_P10 LLWU_P6 LLWU_P2 LLWU_P11 LLWU_P15 LLWU_P14 LLWU_P13 LLWU_P12 RTC_ WAKEUP_B LLWU_P5 CMP1_IN2/ ADC0_SE21 ADC2_DP0/ ADC3_DP3/ ADC0_DP1 ADC2_DM0/ ADC3_DM3/ ADC0_DM1 LLWU_P4 CMP2_IN2/ ADC0_SE22 ADC3_DM0/ ADC2_DM3/ ADC1_DM1 ADC3_DP0/ ADC2_DP3/ ADC1_DP1 LLWU_P3CMP0_IN4/ CMP2_IN3/ ADC1_SE23 CMP1_IN3/ ADC0_SE23 ADC0_DM0/ ADC1_DM3 ADC0_DP0/ ADC1_DP3 ADC1_DM0/ ADC0_DM3 CMP1_IN5/ CMP0_IN5/ ADC1_SE18 ADC1_DP0/ ADC0_DP3 Figure 41. K70 256 MAPBGA Pinout Diagram

9 Revision History

The following table provides a revision history for this document.

Revision History

K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012. 90 Preliminary Freescale Semiconductor, Inc.

Table 56. Revision History 1 6/2011 Initial public revision. Corrected USB conditions. 2 11/2011 • Added AC electrical specifications.

• Updated Part identification section for 120 MHz CPU frequency.
• Updated Voltage and current operating ratings section.
• Updated Voltage and current operating requirements section.
• Updated LVD and POR operating requirements section.
• Updated Voltage and current operating behaviors section.
• Updated Power mode transition operating behaviors section.
• Updated Power consumption operating behaviors section.
• In Device clock specifications section, updated flash clock frequency and DDR clock frequency.
• Updated Thermal attributes.
• In MCG specifications section, updated total deviation of trimmed average DCO output Frequency, PLL reference frequency range, and lock detector detection time.
• In Oscillator frequency specifications section, updated crystal startup time — 32 kHz.
• Updated NFC specifications section.
• Updated DDR controller specifications section.
• In DryIce Tamper Electrical Specifications section, updated supply current.
• In USB DCD electrical specifications section, updated data detect voltage.
• In TSI electrical specifications, updated reference oscillator frequency.
• In LCDC electrical specifications section, updated signal names as per pinouts.
• Updated Pinouts.
• Updated Pinouts.

K70 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012. Freescale Semiconductor, Inc. Preliminary 91

How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, EL516

2100 East Elliot Road

Tempe, Arizona 85284 +1-800-521-6274 or +1-480-768-2130 www.freescale.com/support Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7

81829 Muenchen, Germany

+44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) www.freescale.com/support Japan: Freescale Semiconductor Japan Ltd. Headquarters ARCO Tower 15F 1-8-1, Shimo-Meguro, Meguro-ku, Tokyo 153-0064 Japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com Asia/Pacific: Freescale Semiconductor China Ltd. Exchange Building 23F No. 118 Jianguo Road Chaoyang District Beijing 100022 China +86 10 5879 8000 support.asia@freescale.com Document Number: K70P256M150SF3 Rev. 3, 2/2012 Preliminary Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductors products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any liability, including without limitation consequential or incidental damages. "Typical" parameters that may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals", must be validated for each customer application by customer's technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claims alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. RoHS-compliant and/or Pb-free versions of Freescale products have the functionality and electrical characteristics as their non-RoHS-complaint and/or non-Pb-free counterparts. For further information, see http://www.freescale.com or contact your Freescale sales representative. For information on Freescale's Environmental Products program, go to http://www.freescale.com/epp. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc.